2018-12-21 | Paul M Stillwell Jr | net/ice/base: add structures for Rx/Tx queues Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add protocol structures and defines Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add various headers Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add common functions Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add code to work with the NVM Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add virtual switch code Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add basic Tx scheduler Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add control queue information Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add device IDs for Intel E800 Series... Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add sideband queue info Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add admin queue structures and commands Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add basic structures Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-12-21 | Paul M Stillwell Jr | net/ice/base: add registers for Intel E800 Series NIC Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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2018-09-27 | Paul M Stillwell Jr | ethdev: fix doxygen comment to be with structure Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> |
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