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net/ice/base: fix alignment
2019-10-07 Qi Zhangnet/ice/base: fix alignment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: use bitmap copy where appropriate
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove unnecessary error log
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix 4 bytes alignment for PPPoE dummy...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: search field vector indices for result...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove unused DDP package macros
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix segment in remove existing RSS rule
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix bitmap for TCP in RSS
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support FDIR for GTPU QFI field
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: replace alloc-followed-by-copy with memdup
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enable symmetric hash for RSS
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update FW API minor version
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support destination MAC field for FDIR
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enable setting up FDIR counters
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enable FDIR queue region
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enable RSS for PPPoE with SCTP
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: associate switch recipe to profiles
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: refactor data structure
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support switch rule about VLAN PPPoE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove RSS code as iavf host
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove null check of port info
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: propagate errors from functions
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix mask for checking protocol header
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add non-word aligned IPv6 field support
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add non-word aligned IPv4 field support
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support tunnel packets
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove redundant empty lines
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: ignore inverse switch recipes
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update profile to recipe bitmap array
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add GENEVE offset
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enable RSS with ether layer for PPPoE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove Rx flex descriptor programming
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add AQC get link topology handle support
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: delay less
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: replace open-code duplication
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update to register definition file
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: correct abbreviations
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove unnecessary if branch
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove unnecessary dummy packet finding
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update switch training packets with open...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: maximize switch recipe words per line
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: refactor removal of VLAN promiscuous...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix flag settings in AQ call
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove unnecessary conditional check
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add RSS support for PPPoE and GTPU
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: packet encapsulation for RSS
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix for RSS hash on inner UDP port
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: consolidate packet type group
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add routine for tunnel port query
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: move and add some help function and macros
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: improve switch chained recipe
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update UDP tunnel switch training packets
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: return switch error on invalid match...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: associate recipes by profile type
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support not locking sideband queue
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add function to configure Tx AQ command
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: initialize driver NVM data earlier
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: set status when global cfg lock is unavailable
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add more opcode and macros
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update flag bits
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add 32-byte Flex Rx descriptor
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add 16-byte Flex Rx descriptor
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: move function declaration
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: improve switch advanced rule
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add locks for flow functions
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support GTP and PPPoE protocols
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support NVM access commands
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: update Boot Configuration Section read...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix overrun
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix type-mismatch
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: check root pointer for validity
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: fix memory leak
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: resolve static analysis issues
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enable masking for RSS and FD field vectors
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: move VSI to VSI group
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add NVM pkg flag
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: adjust DCB INIT for SW mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support reading REPC statistics
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add helper functions for PHY caching
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add capabilities when in safe mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: improve debug print message
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add SFF EEPROM AQ command
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: remove debug code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: correct argument port info
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add read PBA module function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: store number of functions for the device
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support init RXDID descs fields
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: support NVM rollback detection
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: add function to get FW mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-10-07 Qi Zhangnet/ice/base: enhance NVM read
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-26 Qi Zhangnet/iavf: fix endless loop
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-24 Qi Zhangnet/ice/base: fix bitmap and/or routines
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-24 Qi Zhangnet/ice/base: cleanup hardware register macros
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-24 Qi Zhangnet/ice/base: use macro instead of function name
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-24 Qi Zhangnet/ice/base: fix packet type size
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-24 Qi Zhangnet/ice/base: fix resource leak
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-24 Qi Zhangnet/ice/base: fix inner TCP and UDP support for GRE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-23 Qi Zhangnet/iavf: fix Rx bytes stats
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-23 Qi Zhangnet/ice: add safe mode devarg
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-07-23 Qi Zhangnet/ice: remove unused devargs
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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