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net/ice/base: specify global RSS LUT id in get/set RSS LUT
2020-11-03 Qi Zhangnet/ice/base: specify global RSS LUT id in get/set...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: refactor RSS configure API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: use macro to get variable size array...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: remove duplicated AQ command flag setting
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: support extended GPIO access
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: fix parameter name in comment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: recognize 860 as iSCSI port in CEE mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: implement shared rate limiter
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: return error directly
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: support class 5+ modules
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: use malloc instead of calloc
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: use package info from ice segment metadata
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: add more capability to admin queue
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: allocate and free RSS global lookup table
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: read security revision
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: move sched function prototypes
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: rename ptype bitmap
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: modify ptype bitmap for outer MAC
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: add NVM write response flags
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: support tunnel for flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-10-16 Qi Zhangcommon/iavf: support VF with more than 16 queues
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-10-16 Qi Zhangcommon/iavf: replace macro for MAC address length
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-21 Qi Zhangnet/iavf: fix iterator for RSS LUT
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice: support new devices
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/iavf: reject floating RSS attribute
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: preserve default aggregator VSI information
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: rename ACL priority values
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove unnecessary conditional
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: rename function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cache NVM module bank information
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cleanup code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove unused parameter
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: separate NVM version struct
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: enable QinQ filter for switch advanced...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: adjust rate limit profile ids runtime...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: change misc ACL style
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: preserve NVM capabilities in safe mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove function ACL count query
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove repeated words
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: check failed acts allocation
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: move a function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: clear advanced rules in reset preparation
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: move a function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: filter for GTPU outer IP without inner IP
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: support outer IP filter for GTPC
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: refactor DCB related variables
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: reduce profile to recip info get from...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce Tx rate limiting on port level
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: join format strings to same line
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: support GTP-U type switch rule
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: add AQ LLDP filter control command
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: fix abbreviations
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce and use for each bit iterator
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: add function header
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce and use bitmap hamming weight API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce and use bitmap set API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: replace single-element array hack
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: silence static analysis warning
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cleanup misleading comment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: clean code wrapping
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cleanup stack hog
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: fix issues around move nodes
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: avoid single-member variable-length structs
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: split capabilities discovering
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: handle error gracefully in HW table calloc
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangcommon/iavf: add IPv6 prefix protocol header fields
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangcommon/iavf: support GTPC
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangcommon/iavf: save max MTU received from PF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangcommon/iavf: cleanup virtual channel code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangcommon/iavf: use pad byte to specify MAC type
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/iavf: refactor RSS
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: fix outer IPv6 packet type table
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-08-06 Qi Zhangdoc: update release notes for ice and iavf
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-29 Qi Zhangnet/ice: remove RSS for SCTP in PPPoE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-29 Qi Zhangnet/ice/base: fix RSS interference
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: update version
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: clear and free XLT entries on reset
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: split capability parse into separate...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: add capability list AQ function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: clean code in flow director module
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: move LLDP function to common module
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: cleanup some code style
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-07-07 Qi Zhangnet/ice: support original VF action for DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangdoc: update for ice DCF datapath configuration
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: set MAC filter during start for DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: enable stats for DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: add queue start and stop for DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: add queue config in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: init RSS during DCF start
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: add Rx queue init in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: add stop flag for device start/stop
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: complete queue setup in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: complete device configure in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: complete device info get in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice: init RSS and supported RXDID in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice/base: replace RSS profile locks
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice/base: fix VSI ID mask to 10 bits
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice/base: choose TCP dummy packet by protocol
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-06-30 Qi Zhangnet/ice/base: get tunnel type for recipe
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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