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raw/ifpga: add miscellaneous APIs
2021-03-05 Wei Huangraw/ifpga: add miscellaneous APIs
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2021-03-05 Wei Huangraw/ifpga: add APIs to get FPGA information
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2021-03-05 Wei Huangraw/ifpga: add FPGA RSU APIs
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2021-03-05 Beilei Xingnet/i40evf: fix packet loss for X722
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2021-03-05 Zhirun Yannet/ice: clean GTPU flow type for flow director
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Zhirun Yannet/ice: distinguish input set outer fields
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Zhirun Yannet/ice: refactor input set config
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Zhirun Yannet/ice: refactor flow pattern parser
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Zhirun Yannet/ice: refactor flow director filter structure
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Zhirun Yannet/ice: clean input set macro definition
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: cleanup filter list on error
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: fix uninitialized struct
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: update GTPU EH dummy packets for FDIR
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: update boost TCAM for DVM
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: mark ptype 2 as reserved
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: fix payload indicator on ptype
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support GTPU IP inner IPv6 for flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support switch filter (GTP tunnel+IP...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: enable more GTPU inner L3 fields for...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: expose link configuration error
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: enable GTPU inner L3/L4 for flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: indicate double reset solution restriction
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support external device secure programming
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support firmware log
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Dapeng Yunet/e1000: remove MTU setting limitation
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2021-03-05 Dapeng Yunet/igc: remove MTU setting limitation
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2021-03-05 Alvin Zhangnet/ice: fix VLAN filter with PF
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-02-23 Haiyue Wangnet/iavf: fix VLAN tag extraction handling
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-08-06 Xiao Zhangnet/fm10k: fix address of first segment
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2019-08-06 Xiao Zhangnet/iavf: fix address of first segment
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2019-08-06 Xiao Zhangnet/i40e: fix address of first segment
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2019-08-06 Xiao Zhangnet/ice: fix address of first segment
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2019-08-06 Xiao Zhangnet/ixgbe: fix address of first segment
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2019-08-06 Xiaolong Yenet/ice: fix null pointer dereferences for tunnels
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2019-08-06 Xiao Zhangnet/e1000: fix PCI config read check
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2019-08-06 Xiaolong Yenet/ice: remove unused parameter tag
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2018-11-05 Beilei Xingnet/i40e: fix Rx instability with vector mode
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2018-08-02 Xiaoyun Linet/avf: fix offload capabilities
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2018-08-01 Wei Zhaonet/i40e: revert fix of flow director check
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2018-08-01 Harry van Haarennet/i40e: fix rearm check in AVX2 Rx
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2018-07-30 Xiaoyun Lidoc: add recommended versions for i40e
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2018-07-30 Yanglong Wunet/i40e: fix maximum frame size check
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2018-07-26 Beilei Xingnet/i40e: fix device parameter parsing
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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