/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016 NXP
+ * Copyright 2016-2019 NXP
*
*/
#define DPAA2_PER_LCORE_ETHRX_DPIO RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
#define DPAA2_PER_LCORE_ETHRX_PORTAL DPAA2_PER_LCORE_ETHRX_DPIO->sw_portal
-/* Variable to store DPAA2 platform type */
-extern uint32_t dpaa2_svr_family;
/* Variable to store DPAA2 DQRR size */
extern uint8_t dpaa2_dqrr_size;
/* Variable to store DPAA2 EQCR size */
extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
/* Affine a DPIO portal to current processing thread */
+__rte_internal
int dpaa2_affine_qbman_swp(void);
/* Affine additional DPIO portal to current crypto processing thread */
+__rte_internal
int dpaa2_affine_qbman_ethrx_swp(void);
/* allocate memory for FQ - dq storage */
+__rte_internal
int
dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage);
/* free memory for FQ- dq storage */
+__rte_internal
void
dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage);
/* free the enqueue response descriptors */
+__rte_internal
uint32_t
dpaa2_free_eq_descriptors(void);