/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2020 NXP
*
*/
#define DPAA2_SWP_CINH_REGION 1
#define DPAA2_SWP_CENA_MEM_REGION 2
+#define DPAA2_MAX_TX_RETRY_COUNT 10000
+
#define MC_PORTAL_INDEX 0
#define NUM_DPIO_REGIONS 2
#define NUM_DQS_PER_QUEUE 2
struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
};
+struct dpaa2_dpcon_dev {
+ TAILQ_ENTRY(dpaa2_dpcon_dev) next;
+ struct fsl_mc_io dpcon;
+ uint16_t token;
+ rte_atomic16_t in_use;
+ uint32_t dpcon_id;
+ uint16_t qbman_ch_id;
+ uint8_t num_priorities;
+ uint8_t channel_index;
+};
+
/*! Global MCP list */
extern void *(*rte_mcp_ptr_list);
#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
extern uint8_t dpaa2_virt_mode;
-static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
+static void *dpaa2_mem_ptov(phys_addr_t paddr) __rte_unused;
static void *dpaa2_mem_ptov(phys_addr_t paddr)
{
return va;
}
-static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
+static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __rte_unused;
static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
{
#else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
#define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
-#define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
-#define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
+#define DPAA2_VADDR_TO_IOVA(_vaddr) (phys_addr_t)(_vaddr)
+#define DPAA2_IOVA_TO_VADDR(_iova) (void *)(_iova)
#define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
#endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
{
rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
}
+
+__rte_internal
struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
+
+__rte_internal
void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
+
+__rte_internal
int dpaa2_dpbp_supported(void);
+__rte_internal
struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
+
+__rte_internal
void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);
#endif