common/mlx5: disable relaxed ordering in unsuitable CPUs

[dpdk.git] / drivers / common / mlx5 / mlx5_common.c

diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c
index 4261045..1c77763 100644 (file)
--- a/drivers/common/mlx5/mlx5_common.c
+++ b/drivers/common/mlx5/mlx5_common.c
@@ -22,6 +22,8 @@ int mlx5_common_logtype;
 const struct mlx5_glue *mlx5_glue;
 #endif
 
+uint8_t haswell_broadwell_cpu;
+
 /**
  * Get PCI information by sysfs device path.
  *
@@ -292,6 +294,29 @@ glue_error:
 
 #endif
 
+/* In case this is an x86_64 intel processor to check if
+ * we should use relaxed ordering.
+ */
+#ifdef RTE_ARCH_X86_64
+/**
+ * This function returns processor identification and feature information
+ * into the registers.
+ *
+ * @param eax, ebx, ecx, edx
+ *             Pointers to the registers that will hold cpu information.
+ * @param level
+ *             The main category of information returned.
+ */
+static inline void mlx5_cpu_id(unsigned int level,
+                               unsigned int *eax, unsigned int *ebx,
+                               unsigned int *ecx, unsigned int *edx)
+{
+       __asm__("cpuid\n\t"
+               : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+               : "0" (level));
+}
+#endif
+
 RTE_INIT_PRIO(mlx5_log_init, LOG)
 {
        mlx5_common_logtype = rte_log_register("pmd.common.mlx5");
@@ -350,3 +375,60 @@ glue_error:
        mlx5_glue = NULL;
        return;
 }
+
+/**
+ * This function is responsible of initializing the variable
+ *  haswell_broadwell_cpu by checking if the cpu is intel
+ *  and reading the data returned from mlx5_cpu_id().
+ *  since haswell and broadwell cpus don't have improved performance
+ *  when using relaxed ordering we want to check the cpu type before
+ *  before deciding whether to enable RO or not.
+ *  if the cpu is haswell or broadwell the variable will be set to 1
+ *  otherwise it will be 0.
+ */
+RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
+{
+#ifdef RTE_ARCH_X86_64
+       unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
+       unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
+       unsigned int i, model, family, brand_id, vendor;
+       unsigned int signature_intel_ebx = 0x756e6547;
+       unsigned int extended_model;
+       unsigned int eax = 0;
+       unsigned int ebx = 0;
+       unsigned int ecx = 0;
+       unsigned int edx = 0;
+       int max_level;
+
+       mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
+       vendor = ebx;
+       max_level = eax;
+       if (max_level < 1) {
+               haswell_broadwell_cpu = 0;
+               return;
+       }
+       mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
+       model = (eax >> 4) & 0x0f;
+       family = (eax >> 8) & 0x0f;
+       brand_id = ebx & 0xff;
+       extended_model = (eax >> 12) & 0xf0;
+       /* Check if the processor is Haswell or Broadwell */
+       if (vendor == signature_intel_ebx) {
+               if (family == 0x06)
+                       model += extended_model;
+               if (brand_id == 0 && family == 0x6) {
+                       for (i = 0; i < RTE_DIM(broadwell_models); i++)
+                               if (model == broadwell_models[i]) {
+                                       haswell_broadwell_cpu = 1;
+                                       return;
+                               }
+                       for (i = 0; i < RTE_DIM(haswell_models); i++)
+                               if (model == haswell_models[i]) {
+                                       haswell_broadwell_cpu = 1;
+                                       return;
+                               }
+               }
+       }
+#endif
+       haswell_broadwell_cpu = 0;
+}