common/mlx5: share Netlink commands

[dpdk.git] / drivers / common / mlx5 / mlx5_common.h

diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h
index 2988f4b..d9c2d26 100644 (file)
--- a/drivers/common/mlx5/mlx5_common.h
+++ b/drivers/common/mlx5/mlx5_common.h
@@ -17,6 +17,35 @@
 #include "mlx5_prm.h"
 
 
+/*
+ * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11.
+ * Otherwise there would be a type conflict between stdbool and altivec.
+ */
+#if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__)
+#undef bool
+/* redefine as in stdbool.h */
+#define bool _Bool
+#endif
+
+/* Bit-field manipulation. */
+#define BITFIELD_DECLARE(bf, type, size) \
+       type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
+                !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
+#define BITFIELD_DEFINE(bf, type, size) \
+       BITFIELD_DECLARE((bf), type, (size)) = { 0 }
+#define BITFIELD_SET(bf, b) \
+       (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \
+        (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
+               ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
+#define BITFIELD_RESET(bf, b) \
+       (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \
+        (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
+               ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
+#define BITFIELD_ISSET(bf, b) \
+       (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \
+        !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
+            ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))))
+
 /*
  * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
  * manner.
@@ -112,6 +141,33 @@ enum {
        PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
 };
 
+/* Maximum number of simultaneous unicast MAC addresses. */
+#define MLX5_MAX_UC_MAC_ADDRESSES 128
+/* Maximum number of simultaneous Multicast MAC addresses. */
+#define MLX5_MAX_MC_MAC_ADDRESSES 128
+/* Maximum number of simultaneous MAC addresses. */
+#define MLX5_MAX_MAC_ADDRESSES \
+       (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
+
+/* Recognized Infiniband device physical port name types. */
+enum mlx5_nl_phys_port_name_type {
+       MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
+       MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
+       MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
+       MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
+       MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
+};
+
+/** Switch information returned by mlx5_nl_switch_info(). */
+struct mlx5_switch_info {
+       uint32_t master:1; /**< Master device. */
+       uint32_t representor:1; /**< Representor device. */
+       enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
+       int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
+       int32_t port_name; /**< Representor port name. */
+       uint64_t switch_id; /**< Switch identifier. */
+};
+
 /* CQE status. */
 enum mlx5_cqe_status {
        MLX5_CQE_STATUS_SW_OWN = -1,
@@ -159,6 +215,9 @@ enum mlx5_class {
        MLX5_CLASS_VDPA,
        MLX5_CLASS_INVALID,
 };
+
 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
+void mlx5_translate_port_name(const char *port_name_in,
+                             struct mlx5_switch_info *port_info_out);
 
 #endif /* RTE_PMD_MLX5_COMMON_H_ */