common/mlx5: fix user mode register access command

[dpdk.git] / drivers / common / mlx5 / mlx5_devx_cmds.h

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index bb14ca5..1c84cea 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -29,6 +29,8 @@ struct mlx5_devx_mkey_attr {
 struct mlx5_hca_qos_attr {
        uint32_t sup:1; /* Whether QOS is supported. */
        uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
+       uint32_t packet_pacing:1; /* Packet pacing is supported. */
+       uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
        uint32_t flow_meter_reg_share:1;
        /* Whether reg_c share is supported. */
        uint8_t log_max_flow_meter;
@@ -68,6 +70,7 @@ struct mlx5_hca_attr {
        uint32_t eswitch_manager:1;
        uint32_t flow_counters_dump:1;
        uint32_t log_max_rqt_size:5;
+       uint32_t parse_graph_flex_node:1;
        uint8_t flow_counter_bulk_alloc_bitmap;
        uint32_t eth_net_offloads:1;
        uint32_t eth_virt:1;
@@ -90,6 +93,13 @@ struct mlx5_hca_attr {
        uint32_t vhca_id:16;
        uint32_t relaxed_ordering_write:1;
        uint32_t relaxed_ordering_read:1;
+       uint32_t access_register_user:1;
+       uint32_t wqe_index_ignore:1;
+       uint32_t cross_channel:1;
+       uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
+       uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
+       uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
+       uint32_t scatter_fcs_w_decap_disable:1;
        uint32_t regex:1;
        uint32_t regexp_num_of_engines;
        struct mlx5_hca_qos_attr qos;
@@ -209,6 +219,8 @@ struct mlx5_devx_create_sq_attr {
        uint32_t reg_umr:1;
        uint32_t allow_swp:1;
        uint32_t hairpin:1;
+       uint32_t non_wire:1;
+       uint32_t static_sq_wq:1;
        uint32_t user_index:24;
        uint32_t cqn:24;
        uint32_t packet_pacing_rate_limit_index:16;
@@ -232,6 +244,9 @@ struct mlx5_devx_cq_attr {
        uint32_t db_umem_valid:1;
        uint32_t use_first_only:1;
        uint32_t overrun_ignore:1;
+       uint32_t cqe_comp_en:1;
+       uint32_t mini_cqe_res_format:2;
+       uint32_t cqe_size:3;
        uint32_t log_cq_size:5;
        uint32_t log_page_size:5;
        uint32_t uar_page_id;
@@ -301,6 +316,50 @@ struct mlx5_devx_virtio_q_couners_attr {
        uint32_t invalid_buffer;
 };
 
+/*
+ * graph flow match sample attributes structure,
+ * used by flex parser operations.
+ */
+struct mlx5_devx_match_sample_attr {
+       uint32_t flow_match_sample_en:1;
+       uint32_t flow_match_sample_field_offset:16;
+       uint32_t flow_match_sample_offset_mode:4;
+       uint32_t flow_match_sample_field_offset_mask;
+       uint32_t flow_match_sample_field_offset_shift:4;
+       uint32_t flow_match_sample_field_base_offset:8;
+       uint32_t flow_match_sample_tunnel_mode:3;
+       uint32_t flow_match_sample_field_id;
+};
+
+/* graph node arc attributes structure, used by flex parser operations. */
+struct mlx5_devx_graph_arc_attr {
+       uint32_t compare_condition_value:16;
+       uint32_t start_inner_tunnel:1;
+       uint32_t arc_parse_graph_node:8;
+       uint32_t parse_graph_node_handle;
+};
+
+/* Maximal number of samples per graph node. */
+#define MLX5_GRAPH_NODE_SAMPLE_NUM 8
+
+/* Maximal number of input/output arcs per graph node. */
+#define MLX5_GRAPH_NODE_ARC_NUM 8
+
+/* parse graph node attributes structure, used by flex parser operations. */
+struct mlx5_devx_graph_node_attr {
+       uint32_t modify_field_select;
+       uint32_t header_length_mode:4;
+       uint32_t header_length_base_value:16;
+       uint32_t header_length_field_shift:4;
+       uint32_t header_length_field_offset:16;
+       uint32_t header_length_field_mask;
+       struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
+       uint32_t next_header_field_offset:16;
+       uint32_t next_header_field_size:5;
+       struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
+       struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
+};
+
 /* mlx5_devx_cmds.c */
 
 __rte_internal
@@ -374,7 +433,17 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
 __rte_internal
 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
                             struct mlx5_devx_rqt_attr *rqt_attr);
+__rte_internal
+int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
+                                     uint32_t ids[], uint32_t num);
 
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
+                                       struct mlx5_devx_graph_node_attr *data);
+
+__rte_internal
+int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
+                               uint32_t arg, uint32_t *data, uint32_t dw_cnt);
 /**
  * Create virtio queue counters object DevX API.
  *