#ifndef RTE_PMD_MLX5_PRM_H_
#define RTE_PMD_MLX5_PRM_H_
-#include <assert.h>
-/* Verbs header. */
-/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
-#ifdef PEDANTIC
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
-#include <infiniband/mlx5dv.h>
-#ifdef PEDANTIC
-#pragma GCC diagnostic error "-Wpedantic"
-#endif
+#include <unistd.h>
#include <rte_vect.h>
#include <rte_byteorder.h>
+#include <mlx5_glue.h>
#include "mlx5_autoconf.h"
/* RSS hash key size. */
/* Invalidate a CQE. */
#define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
+/* Hardware index widths. */
+#define MLX5_CQ_INDEX_WIDTH 24
+#define MLX5_WQ_INDEX_WIDTH 16
+
/* WQE Segment sizes in bytes. */
#define MLX5_WSEG_SIZE 16u
#define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
*/
#define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
#define MLX5_MPW_MAX_PACKETS 6
-#define MLX5_MPW_INLINE_MAX_PACKETS 2
+#define MLX5_MPW_INLINE_MAX_PACKETS 6
/*
* Default packet length threshold to be inlined with
MLX5_ESEG_MIN_INLINE_SIZE)
/* Missed in mlv5dv.h, should define here. */
+#ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
#define MLX5_OPCODE_ENHANCED_MPSW 0x29u
+#endif
+
+#ifndef HAVE_MLX5_OPCODE_SEND_EN
+#define MLX5_OPCODE_SEND_EN 0x17u
+#endif
+
+#ifndef HAVE_MLX5_OPCODE_WAIT
+#define MLX5_OPCODE_WAIT 0x0fu
+#endif
/* CQE value to inform that VLAN is stripped. */
#define MLX5_CQE_VLAN_STRIPPED (1u << 0)
#define MLX5_MAX_LOG_RQ_SEGS 5u
/* The alignment needed for WQ buffer. */
-#define MLX5_WQE_BUF_ALIGNMENT 512
+#define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
+
+/* The alignment needed for CQ buffer. */
+#define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
/* Completion mode. */
enum mlx5_completion_mode {
};
} __rte_packed;
+struct mlx5_wqe_qseg {
+ uint32_t reserved0;
+ uint32_t reserved1;
+ uint32_t max_index;
+ uint32_t qpn_cqn;
+} __rte_packed;
+
/* The title WQEBB, header of WQE. */
struct mlx5_wqe {
union {
uint8_t op_own;
};
+struct mlx5_cqe_ts {
+ uint64_t timestamp;
+ uint32_t sop_drop_qpn;
+ uint16_t wqe_counter;
+ uint8_t rsvd5;
+ uint8_t op_own;
+};
+
+/* MMO metadata segment */
+
+#define MLX5_OPCODE_MMO 0x2f
+#define MLX5_OPC_MOD_MMO_REGEX 0x4
+
+struct mlx5_wqe_metadata_seg {
+ uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
+ uint32_t lkey;
+ uint64_t addr;
+};
+
+struct mlx5_ifc_regexp_mmo_control_bits {
+ uint8_t reserved_at_31[0x2];
+ uint8_t le[0x1];
+ uint8_t reserved_at_28[0x1];
+ uint8_t subset_id_0[0xc];
+ uint8_t reserved_at_16[0x4];
+ uint8_t subset_id_1[0xc];
+ uint8_t ctrl[0x4];
+ uint8_t subset_id_2[0xc];
+ uint8_t reserved_at_16_1[0x4];
+ uint8_t subset_id_3[0xc];
+};
+
+struct mlx5_ifc_regexp_metadata_bits {
+ uint8_t rof_version[0x10];
+ uint8_t latency_count[0x10];
+ uint8_t instruction_count[0x10];
+ uint8_t primary_thread_count[0x10];
+ uint8_t match_count[0x8];
+ uint8_t detected_match_count[0x8];
+ uint8_t status[0x10];
+ uint8_t job_id[0x20];
+ uint8_t reserved[0x80];
+};
+
+struct mlx5_ifc_regexp_match_tuple_bits {
+ uint8_t length[0x10];
+ uint8_t start_ptr[0x10];
+ uint8_t rule_id[0x20];
+};
+
/* Adding direct verbs to data-path. */
/* CQ sequence number mask. */
/* CQE format value. */
#define MLX5_COMPRESSED 0x3
+/* CQ doorbell cmd types. */
+#define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
+#define MLX5_CQ_DBR_CMD_ALL (0 << 24)
+
/* Action type of header modification. */
enum {
MLX5_MODIFICATION_TYPE_SET = 0x1,
#define MLX5_SET64(typ, p, fld, v) \
do { \
- assert(__mlx5_bit_sz(typ, fld) == 64); \
+ MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
rte_cpu_to_be_64(v); \
} while (0)
__mlx5_16_bit_off(typ, fld))); \
} while (0)
+#define MLX5_GET_VOLATILE(typ, p, fld) \
+ ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
+ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
+ __mlx5_mask(typ, fld))
#define MLX5_GET(typ, p, fld) \
((rte_be_to_cpu_32(*((__be32 *)(p) +\
__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
u8 tcp_flags[0x9];
u8 tcp_sport[0x10];
u8 tcp_dport[0x10];
- u8 reserved_at_c0[0x20];
+ u8 reserved_at_c0[0x18];
+ u8 ip_ttl_hoplimit[0x8];
u8 udp_sport[0x10];
u8 udp_dport[0x10];
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
u8 reserved_at_170[0x90];
};
+struct mlx5_ifc_fte_match_set_misc4_bits {
+ u8 prog_sample_field_value_0[0x20];
+ u8 prog_sample_field_id_0[0x20];
+ u8 prog_sample_field_value_1[0x20];
+ u8 prog_sample_field_id_1[0x20];
+ u8 prog_sample_field_value_2[0x20];
+ u8 prog_sample_field_id_2[0x20];
+ u8 prog_sample_field_value_3[0x20];
+ u8 prog_sample_field_id_3[0x20];
+ u8 reserved_at_100[0x100];
+};
+
/* Flow matcher. */
struct mlx5_ifc_fte_match_param_bits {
struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
+ struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
};
enum {
MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
- MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
+ MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
+ MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
};
enum {
MLX5_CMD_OP_SUSPEND_QP = 0x50F,
MLX5_CMD_OP_RESUME_QP = 0x510,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+ MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_CREATE_SQ = 0X904,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_CREATE_RQT = 0x916,
+ MLX5_CMD_OP_MODIFY_RQT = 0x917,
MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
+ MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
+ MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
+ MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
+ MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
+ MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
};
enum {
#define MLX5_ADAPTER_PAGE_SHIFT 12
#define MLX5_LOG_RQ_STRIDE_SHIFT 4
+/**
+ * The batch counter dcs id starts from 0x800000 and none batch counter
+ * starts from 0. As currently, the counter is changed to be indexed by
+ * pool index and the offset of the counter in the pool counters_raw array.
+ * It means now the counter index is same for batch and none batch counter.
+ * Add the 0x800000 batch counter offset to the batch counter index helps
+ * indicate the counter index is from batch or none batch container pool.
+ */
+#define MLX5_CNT_BATCH_OFFSET 0x800000
+
+/* The counter batch query requires ID align with 4. */
+#define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
/* Flow counters. */
struct mlx5_ifc_alloc_flow_counter_out_bits {
u8 translations_octword_size[0x20];
- u8 reserved_at_1c0[0x1b];
+ u8 reserved_at_1c0[0x19];
+ u8 relaxed_ordering_read[0x1];
+ u8 reserved_at_1da[0x1];
u8 log_page_size[0x5];
u8 reserved_at_1e0[0x20];
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
};
-enum {
- MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
-};
+#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q (1ULL << 0xd)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS (1ULL << 0x1c)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE (1ULL << 0x22)
enum {
MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
u8 reserved_at_40[0x40];
u8 log_max_srq_sz[0x8];
u8 log_max_qp_sz[0x8];
- u8 reserved_at_90[0xb];
+ u8 reserved_at_90[0x9];
+ u8 wqe_index_ignore_cap[0x1];
+ u8 dynamic_qp_allocation[0x1];
u8 log_max_qp[0x5];
- u8 reserved_at_a0[0xb];
+ u8 regexp[0x1];
+ u8 reserved_at_a1[0x3];
+ u8 regexp_num_of_engines[0x4];
+ u8 reserved_at_a8[0x3];
u8 log_max_srq[0x5];
- u8 reserved_at_b0[0x10];
+ u8 reserved_at_b0[0x3];
+ u8 regexp_log_crspace_size[0x5];
+ u8 reserved_at_b8[0x3];
+ u8 scatter_fcs_w_decap_disable[0x1];
+ u8 reserved_at_bc[0x4];
u8 reserved_at_c0[0x8];
u8 log_max_cq_sz[0x8];
u8 reserved_at_d0[0xb];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
- u8 reserved_at_e8[0x2];
- u8 log_max_mkey[0x6];
+ u8 relaxed_ordering_write[0x1];
+ u8 relaxed_ordering_read[0x1];
+ u8 access_register_user[0x1];
+ u8 log_max_mkey[0x5];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];
u8 reserved_at_f9[0x3];
u8 umr_extended_translation_offset[0x1];
u8 null_mkey[0x1];
u8 log_max_klm_list_size[0x6];
- u8 reserved_at_120[0xa];
+ u8 non_wire_sq[0x1];
+ u8 reserved_at_121[0x9];
u8 log_max_ra_req_dc[0x6];
- u8 reserved_at_130[0xa];
+ u8 reserved_at_130[0x3];
+ u8 log_max_static_sq_wq[0x5];
+ u8 reserved_at_138[0x2];
u8 log_max_ra_res_dc[0x6];
u8 reserved_at_140[0xa];
u8 log_max_ra_req_qp[0x6];
u8 reserved_at_8[0x8];
u8 log_max_flow_meter[0x8];
u8 flow_meter_reg_id[0x8];
- u8 reserved_at_25[0x8];
+ u8 wqe_rate_pp[0x1];
+ u8 reserved_at_25[0x7];
u8 flow_meter_reg_share[0x1];
u8 reserved_at_2e[0x17];
u8 packet_pacing_max_rate[0x20];
struct mlx5_ifc_rqc_bits ctx;
};
+enum {
+ MLX5_L3_PROT_TYPE_IPV4 = 0,
+ MLX5_L3_PROT_TYPE_IPV6 = 1,
+};
+
+enum {
+ MLX5_L4_PROT_TYPE_TCP = 0,
+ MLX5_L4_PROT_TYPE_UDP = 1,
+};
+
enum {
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
u8 reserved_at_40[0xc0];
struct mlx5_ifc_rqtc_bits rqt_context;
};
+
+struct mlx5_ifc_modify_rqt_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 rqtn[0x18];
+ u8 reserved_at_60[0x20];
+ u8 modify_bitmask[0x40];
+ u8 reserved_at_c0[0x40];
+ struct mlx5_ifc_rqtc_bits rqt_context;
+};
#ifdef PEDANTIC
#pragma GCC diagnostic error "-Wpedantic"
#endif
+struct mlx5_ifc_modify_rqt_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
enum {
MLX5_SQC_STATE_RST = 0x0,
MLX5_SQC_STATE_RDY = 0x1,
u8 reg_umr[0x1];
u8 allow_swp[0x1];
u8 hairpin[0x1];
- u8 reserved_at_f[0x11];
+ u8 non_wire[0x1];
+ u8 static_sq_wq[0x1];
+ u8 reserved_at_11[0xf];
u8 reserved_at_20[0x8];
u8 user_index[0x18];
u8 reserved_at_40[0x8];
u8 reserved_at_8[0x60]; // 14h-1Ch
};
+enum {
+ MLX5_CQE_SIZE_64B = 0x0,
+ MLX5_CQE_SIZE_128B = 0x1,
+};
+
struct mlx5_ifc_cqc_bits {
u8 status[0x4];
u8 as_notify[0x1];
enum {
MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
+ MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
+ MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
};
struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
u8 reserved_at_60[0x20];
};
+struct mlx5_ifc_virtio_q_counters_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x40];
+ u8 received_desc[0x40];
+ u8 completed_desc[0x40];
+ u8 error_cqes[0x20];
+ u8 bad_desc_errors[0x20];
+ u8 exceed_max_chain[0x20];
+ u8 invalid_buffer[0x20];
+ u8 reserved_at_180[0x50];
+};
+
+struct mlx5_ifc_create_virtio_q_counters_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
+};
+
+struct mlx5_ifc_query_virtio_q_counters_out_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
+};
enum {
MLX5_VIRTQ_STATE_INIT = 0,
MLX5_VIRTQ_STATE_RDY = 1,
u8 umem_3_id[0x20];
u8 umem_3_size[0x20];
u8 umem_3_offset[0x40];
- u8 reserved_at_300[0x100];
+ u8 counter_set_id[0x20];
+ u8 reserved_at_320[0x8];
+ u8 pd[0x18];
+ u8 reserved_at_340[0xc0];
};
struct mlx5_ifc_virtio_net_q_bits {
u8 reserved_at_60[0x20];
};
+enum {
+ MLX5_DATA_RATE = 0x0,
+ MLX5_WQE_RATE = 0x1,
+};
+
+struct mlx5_ifc_set_pp_rate_limit_context_bits {
+ u8 rate_limit[0x20];
+ u8 burst_upper_bound[0x20];
+ u8 reserved_at_40[0xC];
+ u8 rate_mode[0x4];
+ u8 typical_packet_size[0x10];
+ u8 reserved_at_60[0x120];
+};
+
+#define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_access_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ u8 register_data[0][0x20];
+};
+
+struct mlx5_ifc_access_register_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x10];
+ u8 register_id[0x10];
+ u8 argument[0x20];
+ u8 register_data[0][0x20];
+};
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
+enum {
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
+};
+
+enum {
+ MLX5_REGISTER_ID_MTUTC = 0x9055,
+};
+
+struct mlx5_ifc_register_mtutc_bits {
+ u8 time_stamp_mode[0x2];
+ u8 time_stamp_state[0x2];
+ u8 reserved_at_4[0x18];
+ u8 operation[0x4];
+ u8 freq_adjustment[0x20];
+ u8 reserved_at_40[0x40];
+ u8 utc_sec[0x20];
+ u8 utc_nsec[0x20];
+ u8 time_adjustment[0x20];
+};
+
+#define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
+#define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
+
+struct mlx5_ifc_parse_graph_arc_bits {
+ u8 start_inner_tunnel[0x1];
+ u8 reserved_at_1[0x7];
+ u8 arc_parse_graph_node[0x8];
+ u8 compare_condition_value[0x10];
+ u8 parse_graph_node_handle[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_parse_graph_flow_match_sample_bits {
+ u8 flow_match_sample_en[0x1];
+ u8 reserved_at_1[0x3];
+ u8 flow_match_sample_offset_mode[0x4];
+ u8 reserved_at_5[0x8];
+ u8 flow_match_sample_field_offset[0x10];
+ u8 reserved_at_32[0x4];
+ u8 flow_match_sample_field_offset_shift[0x4];
+ u8 flow_match_sample_field_base_offset[0x8];
+ u8 reserved_at_48[0xd];
+ u8 flow_match_sample_tunnel_mode[0x3];
+ u8 flow_match_sample_field_offset_mask[0x20];
+ u8 flow_match_sample_field_id[0x20];
+};
+
+struct mlx5_ifc_parse_graph_flex_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_64[0x20];
+ u8 header_length_base_value[0x10];
+ u8 reserved_at_112[0x4];
+ u8 header_length_field_shift[0x4];
+ u8 reserved_at_120[0x4];
+ u8 header_length_mode[0x4];
+ u8 header_length_field_offset[0x10];
+ u8 next_header_field_offset[0x10];
+ u8 reserved_at_160[0x1b];
+ u8 next_header_field_size[0x5];
+ u8 header_length_field_mask[0x20];
+ u8 reserved_at_224[0x20];
+ struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
+ struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
+ struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
+};
+
+struct mlx5_ifc_create_flex_parser_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_parse_graph_flex_bits flex;
+};
+
+struct mlx5_ifc_create_flex_parser_out_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_parse_graph_flex_bits flex;
+};
+
+struct mlx5_ifc_parse_graph_flex_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ struct mlx5_ifc_parse_graph_flex_bits capability;
+};
+
+struct regexp_params_field_select_bits {
+ u8 reserved_at_0[0x1e];
+ u8 stop_engine[0x1];
+ u8 db_umem_id[0x1];
+};
+
+struct mlx5_ifc_regexp_params_bits {
+ u8 reserved_at_0[0x1f];
+ u8 stop_engine[0x1];
+ u8 db_umem_id[0x20];
+ u8 db_umem_offset[0x40];
+ u8 reserved_at_80[0x100];
+};
+
+struct mlx5_ifc_set_regexp_params_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ struct regexp_params_field_select_bits field_select;
+ struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_params_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_18[0x40];
+};
+
+struct mlx5_ifc_query_regexp_params_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 reserved[0x20];
+};
+
+struct mlx5_ifc_query_regexp_params_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x40];
+ struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_register_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 register_address[0x20];
+ u8 register_data[0x20];
+ u8 reserved[0x40];
+};
+
+struct mlx5_ifc_set_regexp_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x40];
+};
+
+struct mlx5_ifc_query_regexp_register_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x18];
+ u8 engine_id[0x8];
+ u8 register_address[0x20];
+};
+
+struct mlx5_ifc_query_regexp_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved[0x20];
+ u8 register_data[0x20];
+};
+
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc
/* The bits meter color use. */
#define MLX5_MTR_COLOR_BITS 8
+/* Length mode of dynamic flex parser graph node. */
+enum mlx5_parse_graph_node_len_mode {
+ MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
+ MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
+ MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
+};
+
+/* Offset mode of the samples of flex parser. */
+enum mlx5_parse_graph_flow_match_sample_offset_mode {
+ MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
+ MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
+ MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
+};
+
+/* Node index for an input / output arc of the flex parser graph. */
+enum mlx5_parse_graph_arc_node_index {
+ MLX5_GRAPH_ARC_NODE_NULL = 0x0,
+ MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
+ MLX5_GRAPH_ARC_NODE_MAC = 0x2,
+ MLX5_GRAPH_ARC_NODE_IP = 0x3,
+ MLX5_GRAPH_ARC_NODE_GRE = 0x4,
+ MLX5_GRAPH_ARC_NODE_UDP = 0x5,
+ MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
+ MLX5_GRAPH_ARC_NODE_TCP = 0x7,
+ MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
+ MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
+ MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
+ MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
+};
+
/**
* Convert a user mark to flow mark.
*
git.droids-corp.org / dpdk.git / blobdiff