common/mlx5: fix user mode register access command

[dpdk.git] / drivers / common / mlx5 / mlx5_prm.h

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index adf5299..0fa42bb 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -6,21 +6,12 @@
 #ifndef RTE_PMD_MLX5_PRM_H_
 #define RTE_PMD_MLX5_PRM_H_
 
-/* Verbs header. */
-/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
-#ifdef PEDANTIC
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
-#include <infiniband/mlx5dv.h>
-#ifdef PEDANTIC
-#pragma GCC diagnostic error "-Wpedantic"
-#endif
-
 #include <unistd.h>
 
 #include <rte_vect.h>
 #include <rte_byteorder.h>
 
+#include <mlx5_glue.h>
 #include "mlx5_autoconf.h"
 
 /* RSS hash key size. */
@@ -267,10 +258,10 @@
 #define MLX5_MAX_LOG_RQ_SEGS 5u
 
 /* The alignment needed for WQ buffer. */
-#define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
+#define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 
 /* The alignment needed for CQ buffer. */
-#define MLX5_CQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
+#define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 
 /* Completion mode. */
 enum mlx5_completion_mode {
@@ -877,6 +868,9 @@ enum {
  */
 #define MLX5_CNT_BATCH_OFFSET 0x800000
 
+/* The counter batch query requires ID align with 4. */
+#define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
+
 /* Flow counters. */
 struct mlx5_ifc_alloc_flow_counter_out_bits {
        u8         status[0x8];
@@ -1110,7 +1104,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 log_max_eq_sz[0x8];
        u8 relaxed_ordering_write[0x1];
        u8 relaxed_ordering_read[0x1];
-       u8 log_max_mkey[0x6];
+       u8 access_register_user[0x1];
+       u8 log_max_mkey[0x5];
        u8 reserved_at_f0[0x8];
        u8 dump_fill_mkey[0x1];
        u8 reserved_at_f9[0x3];