common/mlx5: add DevX command to create CQ

[dpdk.git] / drivers / common / mlx5 / mlx5_prm.h

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index db15bb6..a4082b9 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -710,6 +710,7 @@ enum {
 enum {
        MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
        MLX5_CMD_OP_CREATE_MKEY = 0x200,
+       MLX5_CMD_OP_CREATE_CQ = 0x400,
        MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
        MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
        MLX5_CMD_OP_CREATE_TIR = 0x900,
@@ -1846,6 +1847,76 @@ struct mlx5_ifc_flow_meter_parameters_bits {
        u8         reserved_at_8[0x60];         // 14h-1Ch
 };
 
+struct mlx5_ifc_cqc_bits {
+       u8 status[0x4];
+       u8 as_notify[0x1];
+       u8 initiator_src_dct[0x1];
+       u8 dbr_umem_valid[0x1];
+       u8 reserved_at_7[0x1];
+       u8 cqe_sz[0x3];
+       u8 cc[0x1];
+       u8 reserved_at_c[0x1];
+       u8 scqe_break_moderation_en[0x1];
+       u8 oi[0x1];
+       u8 cq_period_mode[0x2];
+       u8 cqe_comp_en[0x1];
+       u8 mini_cqe_res_format[0x2];
+       u8 st[0x4];
+       u8 reserved_at_18[0x8];
+       u8 dbr_umem_id[0x20];
+       u8 reserved_at_40[0x14];
+       u8 page_offset[0x6];
+       u8 reserved_at_5a[0x6];
+       u8 reserved_at_60[0x3];
+       u8 log_cq_size[0x5];
+       u8 uar_page[0x18];
+       u8 reserved_at_80[0x4];
+       u8 cq_period[0xc];
+       u8 cq_max_count[0x10];
+       u8 reserved_at_a0[0x18];
+       u8 c_eqn[0x8];
+       u8 reserved_at_c0[0x3];
+       u8 log_page_size[0x5];
+       u8 reserved_at_c8[0x18];
+       u8 reserved_at_e0[0x20];
+       u8 reserved_at_100[0x8];
+       u8 last_notified_index[0x18];
+       u8 reserved_at_120[0x8];
+       u8 last_solicit_index[0x18];
+       u8 reserved_at_140[0x8];
+       u8 consumer_counter[0x18];
+       u8 reserved_at_160[0x8];
+       u8 producer_counter[0x18];
+       u8 local_partition_id[0xc];
+       u8 process_id[0x14];
+       u8 reserved_at_1A0[0x20];
+       u8 dbr_addr[0x40];
+};
+
+struct mlx5_ifc_create_cq_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x8];
+       u8 cqn[0x18];
+       u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_cq_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x40];
+       struct mlx5_ifc_cqc_bits cq_context;
+       u8 cq_umem_offset[0x40];
+       u8 cq_umem_id[0x20];
+       u8 cq_umem_valid[0x1];
+       u8 reserved_at_2e1[0x1f];
+       u8 reserved_at_300[0x580];
+       u8 pas[];
+};
+
 /* CQE format mask. */
 #define MLX5E_CQE_FORMAT_MASK 0xc