* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
*/
+#include <rte_string_fns.h>
#include <rte_bus_pci.h>
#include <rte_bus_vdev.h>
#include <rte_common.h>
-#include <rte_config.h>
#include <rte_cryptodev.h>
#include <rte_cryptodev_pmd.h>
#include <rte_pci.h>
*/
static unsigned int ccp_pmd_init_done;
uint8_t ccp_cryptodev_driver_id;
+uint8_t cryptodev_cnt;
struct ccp_pmd_init_params {
struct rte_cryptodev_pmd_init_params def_p;
return NULL;
sess = (struct ccp_session *)
- get_session_private_data(
+ get_sym_session_private_data(
op->sym->session,
ccp_cryptodev_driver_id);
} else if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS) {
if (unlikely(ccp_set_session_parameters(sess, op->sym->xform,
internals) != 0)) {
rte_mempool_put(qp->sess_mp, _sess);
- rte_mempool_put(qp->sess_mp, _sess_private_data);
+ rte_mempool_put(qp->sess_mp_priv, _sess_private_data);
sess = NULL;
}
op->sym->session = (struct rte_cryptodev_sym_session *)_sess;
- set_session_private_data(op->sym->session,
+ set_sym_session_private_data(op->sym->session,
ccp_cryptodev_driver_id,
_sess_private_data);
}
struct ccp_queue *cmd_q;
struct rte_cryptodev *dev = qp->dev;
uint16_t i, enq_cnt = 0, slots_req = 0;
+ uint16_t tmp_ops = nb_ops, b_idx, cur_ops = 0;
if (nb_ops == 0)
return 0;
if (unlikely(rte_ring_full(qp->processed_pkts) != 0))
return 0;
+ if (tmp_ops >= cryptodev_cnt)
+ cur_ops = nb_ops / cryptodev_cnt + (nb_ops)%cryptodev_cnt;
+ else
+ cur_ops = tmp_ops;
+ while (tmp_ops) {
+ b_idx = nb_ops - tmp_ops;
+ slots_req = 0;
+ if (cur_ops <= tmp_ops) {
+ tmp_ops -= cur_ops;
+ } else {
+ cur_ops = tmp_ops;
+ tmp_ops = 0;
+ }
+ for (i = 0; i < cur_ops; i++) {
+ sess = get_ccp_session(qp, ops[i + b_idx]);
+ if (unlikely(sess == NULL) && (i == 0)) {
+ qp->qp_stats.enqueue_err_count++;
+ return 0;
+ } else if (sess == NULL) {
+ cur_ops = i;
+ break;
+ }
+ slots_req += ccp_compute_slot_count(sess);
+ }
- for (i = 0; i < nb_ops; i++) {
- sess = get_ccp_session(qp, ops[i]);
- if (unlikely(sess == NULL) && (i == 0)) {
- qp->qp_stats.enqueue_err_count++;
+ cmd_q = ccp_allot_queue(dev, slots_req);
+ if (unlikely(cmd_q == NULL))
return 0;
- } else if (sess == NULL) {
- nb_ops = i;
- break;
- }
- slots_req += ccp_compute_slot_count(sess);
+ enq_cnt += process_ops_to_enqueue(qp, ops, cmd_q, cur_ops,
+ nb_ops, slots_req, b_idx);
+ i++;
}
- cmd_q = ccp_allot_queue(dev, slots_req);
- if (unlikely(cmd_q == NULL))
- return 0;
-
- enq_cnt = process_ops_to_enqueue(qp, ops, cmd_q, nb_ops, slots_req);
qp->qp_stats.enqueued_count += enq_cnt;
return enq_cnt;
}
uint16_t nb_ops)
{
struct ccp_qp *qp = queue_pair;
- uint16_t nb_dequeued = 0, i;
+ uint16_t nb_dequeued = 0, i, total_nb_ops;
- nb_dequeued = process_ops_to_dequeue(qp, ops, nb_ops);
+ nb_dequeued = process_ops_to_dequeue(qp, ops, nb_ops, &total_nb_ops);
+
+ if (total_nb_ops) {
+ while (nb_dequeued != total_nb_ops) {
+ nb_dequeued = process_ops_to_dequeue(qp,
+ ops, nb_ops, &total_nb_ops);
+ }
+ }
/* Free session if a session-less crypto op */
for (i = 0; i < nb_dequeued; i++)
if (unlikely(ops[i]->sess_type ==
RTE_CRYPTO_OP_SESSIONLESS)) {
+ struct ccp_session *sess = (struct ccp_session *)
+ get_sym_session_private_data(
+ ops[i]->sym->session,
+ ccp_cryptodev_driver_id);
+
+ rte_mempool_put(qp->sess_mp_priv,
+ sess);
rte_mempool_put(qp->sess_mp,
ops[i]->sym->session);
ops[i]->sym->session = NULL;
{
RTE_PCI_DEVICE(0x1022, 0x1468), /* AMD CCP-5b */
},
+ {
+ RTE_PCI_DEVICE(0x1022, 0x15df), /* AMD CCP RV */
+ },
{.device_id = 0},
};
{
struct rte_cryptodev *dev;
struct ccp_private *internals;
- uint8_t cryptodev_cnt = 0;
if (init_params->def_p.name[0] == '\0')
- snprintf(init_params->def_p.name,
- sizeof(init_params->def_p.name),
- "%s", name);
+ strlcpy(init_params->def_p.name, name,
+ sizeof(init_params->def_p.name));
dev = rte_cryptodev_pmd_create(init_params->def_p.name,
&vdev->device,