net/bnxt: support process key tables

[dpdk.git] / drivers / net / bnxt / tf_ulp / ulp_template_db.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index e52cc3f..733836a 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -13,6 +13,37 @@
 
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 
+enum bnxt_ulp_action_bit {
+       BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
+       BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
+       BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
+       BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
+       BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
+       BNXT_ULP_ACTION_BIT_VNIC             = 0x0000000000000020,
+       BNXT_ULP_ACTION_BIT_VPORT            = 0x0000000000000040,
+       BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000080,
+       BNXT_ULP_ACTION_BIT_NVGRE_DECAP      = 0x0000000000000100,
+       BNXT_ULP_ACTION_BIT_OF_POP_MPLS      = 0x0000000000000200,
+       BNXT_ULP_ACTION_BIT_OF_PUSH_MPLS     = 0x0000000000000400,
+       BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000800,
+       BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000001000,
+       BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000002000,
+       BNXT_ULP_ACTION_BIT_OF_POP_VLAN      = 0x0000000000004000,
+       BNXT_ULP_ACTION_BIT_OF_PUSH_VLAN     = 0x0000000000008000,
+       BNXT_ULP_ACTION_BIT_OF_SET_VLAN_PCP  = 0x0000000000010000,
+       BNXT_ULP_ACTION_BIT_OF_SET_VLAN_VID  = 0x0000000000020000,
+       BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000040000,
+       BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000080000,
+       BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000100000,
+       BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000200000,
+       BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000400000,
+       BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000800000,
+       BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000001000000,
+       BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000002000000,
+       BNXT_ULP_ACTION_BIT_NVGRE_ENCAP      = 0x0000000004000000,
+       BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
+};
+
 enum bnxt_ulp_byte_order {
        BNXT_ULP_BYTE_ORDER_BE,
        BNXT_ULP_BYTE_ORDER_LE,
@@ -35,8 +66,48 @@ enum bnxt_ulp_fmf_mask {
        BNXT_ULP_FMF_MASK_LAST
 };
 
+enum bnxt_ulp_mark_enable {
+       BNXT_ULP_MARK_ENABLE_NO = 0,
+       BNXT_ULP_MARK_ENABLE_YES = 1,
+       BNXT_ULP_MARK_ENABLE_LAST = 2
+};
+
+enum bnxt_ulp_mask_opc {
+       BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
+       BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
+       BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
+       BNXT_ULP_MASK_OPC_ADD_PAD = 3,
+       BNXT_ULP_MASK_OPC_LAST = 4
+};
+
+enum bnxt_ulp_priority {
+       BNXT_ULP_PRIORITY_LEVEL_0 = 0,
+       BNXT_ULP_PRIORITY_LEVEL_1 = 1,
+       BNXT_ULP_PRIORITY_LEVEL_2 = 2,
+       BNXT_ULP_PRIORITY_LEVEL_3 = 3,
+       BNXT_ULP_PRIORITY_LEVEL_4 = 4,
+       BNXT_ULP_PRIORITY_LEVEL_5 = 5,
+       BNXT_ULP_PRIORITY_LEVEL_6 = 6,
+       BNXT_ULP_PRIORITY_LEVEL_7 = 7,
+       BNXT_ULP_PRIORITY_NOT_USED = 8,
+       BNXT_ULP_PRIORITY_LAST = 9
+};
+
 enum bnxt_ulp_regfile_index {
-       BNXT_ULP_REGFILE_INDEX_LAST
+       BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 0,
+       BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 1,
+       BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 2,
+       BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 3,
+       BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 4,
+       BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 5,
+       BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 6,
+       BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 7,
+       BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 8,
+       BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 9,
+       BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 10,
+       BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 11,
+       BNXT_ULP_REGFILE_INDEX_NOT_USED = 12,
+       BNXT_ULP_REGFILE_INDEX_LAST = 13
 };
 
 enum bnxt_ulp_resource_func {
@@ -56,9 +127,78 @@ enum bnxt_ulp_result_opc {
        BNXT_ULP_RESULT_OPC_LAST = 4
 };
 
+enum bnxt_ulp_spec_opc {
+       BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
+       BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
+       BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
+       BNXT_ULP_SPEC_OPC_ADD_PAD = 3,
+       BNXT_ULP_SPEC_OPC_LAST = 4
+};
+
 enum bnxt_ulp_sym {
+       BNXT_ULP_SYM_BIG_ENDIAN = 0,
        BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+       BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+       BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
+       BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
+       BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+       BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+       BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
+       BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
+       BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
+       BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+       BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+       BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+       BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+       BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
+       BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
+       BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
+       BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+       BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+       BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+       BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+       BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
+       BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+       BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
+       BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
+       BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+       BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
+       BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
+       BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
+       BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
+       BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+       BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+       BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+       BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+       BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
+       BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
+       BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+       BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
        BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
+       BNXT_ULP_SYM_NO = 0,
+       BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+       BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+       BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
+       BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+       BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
+       BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+       BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
        BNXT_ULP_SYM_YES = 1
 };