* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <rte_string_fns.h>
#include <rte_ether.h>
#include <rte_ethdev_driver.h>
#include <rte_ethdev_pci.h>
host_info->os_type = ENA_ADMIN_OS_DPDK;
host_info->kernel_ver = RTE_VERSION;
- snprintf((char *)host_info->kernel_ver_str,
- sizeof(host_info->kernel_ver_str),
- "%s", rte_version());
+ strlcpy((char *)host_info->kernel_ver_str, rte_version(),
+ sizeof(host_info->kernel_ver_str));
host_info->os_dist = RTE_VERSION;
- snprintf((char *)host_info->os_dist_str,
- sizeof(host_info->os_dist_str),
- "%s", rte_version());
+ strlcpy((char *)host_info->os_dist_str, rte_version(),
+ sizeof(host_info->os_dist_str));
host_info->driver_version =
(DRV_MODULE_VER_MAJOR) |
(DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
- io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
- io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
+ io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
static int adapters_found;
bool wd_state;
- memset(adapter, 0, sizeof(struct ena_adapter));
- ena_dev = &adapter->ena_dev;
-
eth_dev->dev_ops = &ena_dev_ops;
eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
- adapter->rte_eth_dev_data = eth_dev->data;
- adapter->rte_dev = eth_dev;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
+ memset(adapter, 0, sizeof(struct ena_adapter));
+ ena_dev = &adapter->ena_dev;
+
+ adapter->rte_eth_dev_data = eth_dev->data;
+ adapter->rte_dev = eth_dev;
+
pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
adapter->pdev = pci_dev;
/* Set max MTU for this device */
adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
- /* set device support for TSO */
- adapter->tso4_supported = get_feat_ctx.offload.tx &
- ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
+ /* set device support for offloads */
+ adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
+ ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
+ adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
+ ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
+ adapter->offloads.rx_csum_supported =
+ (get_feat_ctx.offload.rx_supported &
+ ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
/* Copy MAC address and point DPDK to it */
- eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
- ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
- (struct ether_addr *)adapter->mac_addr);
+ eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
+ rte_ether_addr_copy((struct rte_ether_addr *)
+ get_feat_ctx.dev_attr.mac_addr,
+ (struct rte_ether_addr *)adapter->mac_addr);
/*
* Pass the information to the rte_eth_dev_close() that it should also
{
struct ena_adapter *adapter;
struct ena_com_dev *ena_dev;
- struct ena_com_dev_get_features_ctx feat;
uint64_t rx_feat = 0, tx_feat = 0;
- int rc = 0;
ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
ETH_LINK_SPEED_50G |
ETH_LINK_SPEED_100G;
- /* Get supported features from HW */
- rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
- if (unlikely(rc)) {
- RTE_LOG(ERR, PMD,
- "Cannot get attribute for ena device rc= %d\n", rc);
- return;
- }
-
/* Set Tx & Rx features available for device */
- if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
+ if (adapter->offloads.tso4_supported)
tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
- if (feat.offload.tx &
- ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
+ if (adapter->offloads.tx_csum_supported)
tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
DEV_TX_OFFLOAD_TCP_CKSUM;
- if (feat.offload.rx_supported &
- ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
+ if (adapter->offloads.rx_csum_supported)
rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM;
uint32_t i;
struct rte_mbuf *m;
struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
- struct ipv4_hdr *ip_hdr;
+ struct rte_ipv4_hdr *ip_hdr;
uint64_t ol_flags;
uint16_t frag_field;
* length of the ethernet header.
*/
if (unlikely(m->l2_len == 0))
- m->l2_len = sizeof(struct ether_hdr);
+ m->l2_len = sizeof(struct rte_ether_hdr);
- ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
+ ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
m->l2_len);
frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
- if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
+ if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
m->packet_type |= RTE_PTYPE_L4_NONFRAG;
/* If IPv4 header has DF flag enabled and TSO support is
* disabled, partial chcecksum should not be calculated.
*/
- if (!tx_ring->adapter->tso4_supported)
+ if (!tx_ring->adapter->offloads.tso4_supported)
continue;
}
if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
(ol_flags & PKT_TX_L4_MASK) ==
PKT_TX_SCTP_CKSUM) {
- rte_errno = -ENOTSUP;
+ rte_errno = ENOTSUP;
return i;
}
#ifdef RTE_LIBRTE_ETHDEV_DEBUG
ret = rte_validate_tx_offload(m);
if (ret != 0) {
- rte_errno = ret;
+ rte_errno = -ret;
return i;
}
#endif
ret = rte_net_intel_cksum_flags_prepare(m,
ol_flags & ~PKT_TX_TCP_SEG);
if (ret != 0) {
- rte_errno = ret;
+ rte_errno = -ret;
return i;
}
}