net/i40evf: add multicast MAC address filtering

[dpdk.git] / drivers / net / i40e / i40e_ethdev.h

diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index d446f1a..151ed1a 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -78,6 +78,15 @@
        (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
        ((vf)->version_minor == 1))
 
+#define I40E_WRITE_GLB_REG(hw, reg, value)                             \
+       do {                                                            \
+               I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw),              \
+                                                    (reg)), (value));  \
+               PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
+                           "with value 0x%08x",                        \
+                           (reg), (value));                            \
+       } while (0)
+
 /* index flex payload per layer */
 enum i40e_flxpld_layer_idx {
        I40E_FLXPLD_L2_IDX    = 0,
@@ -941,6 +950,7 @@ struct i40e_pf {
        bool gtp_replace_flag;   /* 1 - GTP-C/U filter replace is done */
        bool qinq_replace_flag;  /* QINQ filter replace is done */
        struct i40e_tm_conf tm_conf;
+       bool support_multi_driver; /* 1 - support multiple driver */
 
        /* Dynamic Device Personalization */
        bool gtp_support; /* 1 - support GTP-C and GTP-U */
@@ -995,6 +1005,9 @@ struct i40e_vf {
        uint16_t promisc_flags; /* Promiscuous setting */
        uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
 
+       struct ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; /* Multicast addrs */
+       uint16_t mc_addrs_num;   /* Multicast mac addresses number */
+
        /* Event from pf */
        bool dev_closed;
        bool link_up;
@@ -1187,6 +1200,8 @@ int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
                                 uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
+void i40e_check_write_global_reg(struct i40e_hw *hw,
+                                uint32_t addr, uint32_t val);
 
 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
 void i40e_tm_conf_init(struct rte_eth_dev *dev);
@@ -1280,13 +1295,17 @@ i40e_align_floor(int n)
 }
 
 static inline uint16_t
-i40e_calc_itr_interval(int16_t interval, bool is_pf)
+i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)
 {
        if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
-               if (is_pf)
-                       interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
-               else
-                       interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
+               if (is_multi_drv) {
+                       interval = I40E_QUEUE_ITR_INTERVAL_MAX;
+               } else {
+                       if (is_pf)
+                               interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
+                       else
+                               interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
+               }
        }
 
        /* Convert to hardware count, as writing each 1 represents 2 us */