PMD_DRV_LOG(ERR, "command mismatch, expect %u, get %u",
args->ops, info.ops);
- return (err | info.result);
+ return err | info.result;
}
/*
if (err)
PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
rx_queue_id);
+ else
+ dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
}
return err;
i40e_rx_queue_release_mbufs(rxq);
i40e_reset_rx_queue(rxq);
+ dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
}
return 0;
if (err)
PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
tx_queue_id);
+ else
+ dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
}
return err;
i40e_tx_queue_release_mbufs(txq);
i40e_reset_tx_queue(txq);
+ dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
}
return 0;
I40E_VFINT_DYN_CTL01,
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return;
}
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
}
static inline void
if (!rte_intr_allow_others(intr_handle)) {
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return;
}
else
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
}
static int
(interval <<
I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
rte_intr_enable(&dev->pci_dev->intr_handle);
I40E_RX_VEC_START),
0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return 0;
}
static void
i40evf_dev_stop(struct rte_eth_dev *dev)
{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct ether_addr mac_addr;
PMD_INIT_FUNC_TRACE();
rte_free(intr_handle->intr_vec);
intr_handle->intr_vec = NULL;
}
+ /* Set mac addr */
+ (void)rte_memcpy(mac_addr.addr_bytes, hw->mac.addr,
+ sizeof(mac_addr.addr_bytes));
+ /* Delete mac addr of this vf */
+ i40evf_del_mac_addr(dev, &mac_addr);
}
static int
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
int ret = 0;
- if (!key || key_len != ((I40E_VFQF_HKEY_MAX_INDEX + 1) *
- sizeof(uint32_t)))
+ if (!key || key_len == 0) {
+ PMD_DRV_LOG(DEBUG, "No key to be configured");
+ return 0;
+ } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
+ sizeof(uint32_t)) {
+ PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
return -EINVAL;
+ }
if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
struct i40e_aqc_get_set_rss_key_data *key_dw =
return 0;
}
- if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < nb_q) {
+ if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
+ (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
/* Calculate the default hash key */
for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
rss_key_default[i] = (uint32_t)rte_rand();
rss_conf.rss_key = (uint8_t *)rss_key_default;
- rss_conf.rss_key_len = nb_q;
+ rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
+ sizeof(uint32_t);
}
return i40evf_hw_rss_hash_set(vf, &rss_conf);