net/mlx5: create advanced Rx object via DevX

[dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 7ec709b..970dee0 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -627,6 +627,7 @@ enum {
        MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
        MLX5_CMD_OP_CREATE_MKEY = 0x200,
        MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+       MLX5_CMD_OP_CREATE_TIR = 0x900,
        MLX5_CMD_OP_CREATE_RQ = 0x908,
        MLX5_CMD_OP_MODIFY_RQ = 0x909,
        MLX5_CMD_OP_QUERY_TIS = 0x915,
@@ -1407,6 +1408,86 @@ struct mlx5_ifc_modify_rq_in_bits {
        struct mlx5_ifc_rqc_bits ctx;
 };
 
+enum {
+       MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
+       MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
+       MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
+       MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
+       MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
+};
+
+struct mlx5_ifc_rx_hash_field_select_bits {
+       u8 l3_prot_type[0x1];
+       u8 l4_prot_type[0x1];
+       u8 selected_fields[0x1e];
+};
+
+enum {
+       MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
+       MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
+};
+
+enum {
+       MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
+       MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
+};
+
+enum {
+       MLX5_RX_HASH_FN_NONE           = 0x0,
+       MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
+       MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
+};
+
+enum {
+       MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
+       MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
+};
+
+struct mlx5_ifc_tirc_bits {
+       u8 reserved_at_0[0x20];
+       u8 disp_type[0x4];
+       u8 reserved_at_24[0x1c];
+       u8 reserved_at_40[0x40];
+       u8 reserved_at_80[0x4];
+       u8 lro_timeout_period_usecs[0x10];
+       u8 lro_enable_mask[0x4];
+       u8 lro_max_msg_sz[0x8];
+       u8 reserved_at_a0[0x40];
+       u8 reserved_at_e0[0x8];
+       u8 inline_rqn[0x18];
+       u8 rx_hash_symmetric[0x1];
+       u8 reserved_at_101[0x1];
+       u8 tunneled_offload_en[0x1];
+       u8 reserved_at_103[0x5];
+       u8 indirect_table[0x18];
+       u8 rx_hash_fn[0x4];
+       u8 reserved_at_124[0x2];
+       u8 self_lb_block[0x2];
+       u8 transport_domain[0x18];
+       u8 rx_hash_toeplitz_key[10][0x20];
+       struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
+       struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
+       u8 reserved_at_2c0[0x4c0];
+};
+
+struct mlx5_ifc_create_tir_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x8];
+       u8 tirn[0x18];
+       u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_tir_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0xc0];
+       struct mlx5_ifc_tirc_bits ctx;
+};
+
 /* CQE format mask. */
 #define MLX5E_CQE_FORMAT_MASK 0xc