-/*
- * BSD LICENSE
- *
- * Copyright (C) Cavium Inc. 2017. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Cavium networks nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
*/
+
#include <stdio.h>
#include <stdarg.h>
#include <stdbool.h>
#include <rte_dev.h>
#include <rte_kvargs.h>
#include <rte_malloc.h>
+#include <rte_mbuf_pool_ops.h>
#include <rte_prefetch.h>
#include <rte_bus_vdev.h>
uint8_t nr_port;
};
+uint16_t
+rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX];
+
enum octeontx_link_speed {
OCTEONTX_LINK_SPEED_SGMII,
OCTEONTX_LINK_SPEED_XAUI,
OCTEONTX_LINK_SPEED_RESERVE2
};
+int otx_net_logtype_mbox;
+int otx_net_logtype_init;
+int otx_net_logtype_driver;
+
+RTE_INIT(otx_net_init_log);
+static void
+otx_net_init_log(void)
+{
+ otx_net_logtype_mbox = rte_log_register("pmd.net.octeontx.mbox");
+ if (otx_net_logtype_mbox >= 0)
+ rte_log_set_level(otx_net_logtype_mbox, RTE_LOG_NOTICE);
+
+ otx_net_logtype_init = rte_log_register("pmd.net.octeontx.init");
+ if (otx_net_logtype_init >= 0)
+ rte_log_set_level(otx_net_logtype_init, RTE_LOG_NOTICE);
+
+ otx_net_logtype_driver = rte_log_register("pmd.net.octeontx.driver");
+ if (otx_net_logtype_driver >= 0)
+ rte_log_set_level(otx_net_logtype_driver, RTE_LOG_NOTICE);
+}
+
/* Parse integer from integer argument */
static int
parse_integer_arg(const char *key __rte_unused,
int res;
res = 0;
-
+ memset(&bgx_port_conf, 0x0, sizeof(bgx_port_conf));
PMD_INIT_FUNC_TRACE();
res = octeontx_bgx_port_open(nic->port_id, &bgx_port_conf);
struct rte_eth_rxmode *rxmode = &conf->rxmode;
struct rte_eth_txmode *txmode = &conf->txmode;
struct octeontx_nic *nic = octeontx_pmd_priv(dev);
+ uint64_t configured_offloads;
+ uint64_t unsupported_offloads;
int ret;
PMD_INIT_FUNC_TRACE();
return -EINVAL;
}
- if (!rxmode->hw_strip_crc) {
+ configured_offloads = rxmode->offloads;
+
+ if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
PMD_INIT_LOG(NOTICE, "can't disable hw crc strip");
- rxmode->hw_strip_crc = 1;
+ configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
}
- if (rxmode->hw_ip_checksum) {
- PMD_INIT_LOG(NOTICE, "rxcksum not supported");
- rxmode->hw_ip_checksum = 0;
- }
+ unsupported_offloads = configured_offloads & ~OCTEONTX_RX_OFFLOADS;
- if (rxmode->split_hdr_size) {
- octeontx_log_err("rxmode does not support split header");
- return -EINVAL;
+ if (unsupported_offloads) {
+ PMD_INIT_LOG(ERR, "Rx offloads 0x%" PRIx64 " are not supported. "
+ "Requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
+ unsupported_offloads, configured_offloads,
+ (uint64_t)OCTEONTX_RX_OFFLOADS);
+ return -ENOTSUP;
}
- if (rxmode->hw_vlan_filter) {
- octeontx_log_err("VLAN filter not supported");
- return -EINVAL;
- }
+ configured_offloads = txmode->offloads;
- if (rxmode->hw_vlan_extend) {
- octeontx_log_err("VLAN extended not supported");
- return -EINVAL;
+ if (!(configured_offloads & DEV_TX_OFFLOAD_MT_LOCKFREE)) {
+ PMD_INIT_LOG(NOTICE, "cant disable lockfree tx");
+ configured_offloads |= DEV_TX_OFFLOAD_MT_LOCKFREE;
}
- if (rxmode->enable_lro) {
- octeontx_log_err("LRO not supported");
- return -EINVAL;
+ unsupported_offloads = configured_offloads & ~OCTEONTX_TX_OFFLOADS;
+
+ if (unsupported_offloads) {
+ PMD_INIT_LOG(ERR, "Tx offloads 0x%" PRIx64 " are not supported."
+ "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
+ unsupported_offloads, configured_offloads,
+ (uint64_t)OCTEONTX_TX_OFFLOADS);
+ return -ENOTSUP;
}
if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
octeontx_port_promisc_set(nic, 0);
}
-static inline int
-octeontx_atomic_write_link_status(struct rte_eth_dev *dev,
- struct rte_eth_link *link)
-{
- struct rte_eth_link *dst = &dev->data->dev_link;
- struct rte_eth_link *src = link;
-
- if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
- *(uint64_t *)src) == 0)
- return -1;
-
- return 0;
-}
-
static int
octeontx_port_link_status(struct octeontx_nic *nic)
{
struct rte_eth_link link;
int res;
- res = 0;
PMD_INIT_FUNC_TRACE();
res = octeontx_port_link_status(nic);
case OCTEONTX_LINK_SPEED_RESERVE1:
case OCTEONTX_LINK_SPEED_RESERVE2:
default:
+ link.link_speed = ETH_SPEED_NUM_NONE;
octeontx_log_err("incorrect link speed %d", nic->speed);
break;
}
- link.link_duplex = ETH_LINK_AUTONEG;
- link.link_autoneg = ETH_LINK_SPEED_AUTONEG;
+ link.link_duplex = ETH_LINK_FULL_DUPLEX;
+ link.link_autoneg = ETH_LINK_AUTONEG;
- return octeontx_atomic_write_link_status(dev, &link);
+ return rte_eth_linkstatus_set(dev, &link);
}
static int
octeontx_port_stats_clr(nic);
}
-static void
+static int
octeontx_dev_default_mac_addr_set(struct rte_eth_dev *dev,
struct ether_addr *addr)
{
if (ret != 0)
octeontx_log_err("failed to set MAC address on port %d",
nic->port_id);
+
+ return ret;
}
static void
ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
ETH_LINK_SPEED_40G;
- dev_info->driver_name = RTE_STR(rte_octeontx_pmd);
dev_info->max_mac_addrs = 1;
dev_info->max_rx_pktlen = PKI_MAX_PKTLEN;
dev_info->max_rx_queues = 1;
dev_info->max_tx_queues = PKO_MAX_NUM_DQ;
dev_info->min_rx_bufsize = 0;
- dev_info->pci_dev = NULL;
dev_info->default_rxconf = (struct rte_eth_rxconf) {
.rx_free_thresh = 0,
.rx_drop_en = 0,
+ .offloads = OCTEONTX_RX_OFFLOADS,
};
dev_info->default_txconf = (struct rte_eth_txconf) {
ETH_TXQ_FLAGS_NOXSUMS,
};
- dev_info->tx_offload_capa = DEV_TX_OFFLOAD_MT_LOCKFREE;
+ dev_info->rx_offload_capa = OCTEONTX_RX_OFFLOADS;
+ dev_info->tx_offload_capa = OCTEONTX_TX_OFFLOADS;
}
static void
struct octeontx_txq *txq = NULL;
uint16_t dq_num;
int res = 0;
+ uint64_t configured_offloads;
+ uint64_t unsupported_offloads;
RTE_SET_USED(nb_desc);
RTE_SET_USED(socket_id);
- RTE_SET_USED(tx_conf);
dq_num = (nic->port_id * PKO_VF_NUM_DQ) + qidx;
dev->data->tx_queues[qidx] = NULL;
}
+ configured_offloads = tx_conf->offloads;
+
+ if (!(configured_offloads & DEV_TX_OFFLOAD_MT_LOCKFREE)) {
+ PMD_INIT_LOG(NOTICE, "cant disable lockfree tx");
+ configured_offloads |= DEV_TX_OFFLOAD_MT_LOCKFREE;
+ }
+
+ unsupported_offloads = configured_offloads & ~OCTEONTX_TX_OFFLOADS;
+ if (unsupported_offloads) {
+ PMD_INIT_LOG(ERR, "Tx offloads 0x%" PRIx64 " are not supported."
+ "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
+ unsupported_offloads, configured_offloads,
+ (uint64_t)OCTEONTX_TX_OFFLOADS);
+ return -ENOTSUP;
+ }
+
/* Allocating tx queue data structure */
txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct octeontx_txq),
RTE_CACHE_LINE_SIZE, nic->node);
uint8_t gaura;
unsigned int ev_queues = (nic->ev_queues * nic->port_id) + qidx;
unsigned int ev_ports = (nic->ev_ports * nic->port_id) + qidx;
+ uint64_t configured_offloads;
+ uint64_t unsupported_offloads;
RTE_SET_USED(nb_desc);
port = nic->port_id;
+ configured_offloads = rx_conf->offloads;
+
+ if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
+ PMD_INIT_LOG(NOTICE, "can't disable hw crc strip");
+ configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
+ }
+
+ unsupported_offloads = configured_offloads & ~OCTEONTX_RX_OFFLOADS;
+
+ if (unsupported_offloads) {
+ PMD_INIT_LOG(ERR, "Rx offloads 0x%" PRIx64 " are not supported. "
+ "Requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
+ unsupported_offloads, configured_offloads,
+ (uint64_t)OCTEONTX_RX_OFFLOADS);
+ return -ENOTSUP;
+ }
/* Rx deferred start is not supported */
if (rx_conf->rx_deferred_start) {
octeontx_log_err("rx deferred start not supported");
return NULL;
}
+static int
+octeontx_pool_ops(struct rte_eth_dev *dev, const char *pool)
+{
+ RTE_SET_USED(dev);
+
+ if (!strcmp(pool, "octeontx_fpavf"))
+ return 0;
+
+ return -ENOTSUP;
+}
+
/* Initialize and register driver with DPDK Application */
static const struct eth_dev_ops octeontx_dev_ops = {
.dev_configure = octeontx_dev_configure,
.rx_queue_setup = octeontx_dev_rx_queue_setup,
.rx_queue_release = octeontx_dev_rx_queue_release,
.dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get,
+ .pool_ops_supported = octeontx_pool_ops,
};
/* Create Ethdev interface per BGX LMAC ports */
nic->num_tx_queues);
PMD_INIT_LOG(DEBUG, "speed %d mtu %d", nic->speed, nic->mtu);
+ rte_octeontx_pchan_map[(nic->base_ochan >> 8) & 0x7]
+ [(nic->base_ochan >> 4) & 0xF] = data->port_id;
+
return data->port_id;
err:
- if (port)
+ if (nic)
octeontx_port_close(nic);
if (eth_dev != NULL) {
res = -ENOTSUP;
goto parse_error;
}
+ rte_mbuf_set_platform_mempool_ops("octeontx_fpavf");
probe_once = 1;
return 0;
git.droids-corp.org / dpdk.git / blobdiff