#ifndef __OTX2_ETHDEV_H__
#define __OTX2_ETHDEV_H__
+#include <math.h>
#include <stdint.h>
#include <rte_common.h>
#include "otx2_common.h"
#include "otx2_dev.h"
+#include "otx2_flow.h"
#include "otx2_irq.h"
#include "otx2_mempool.h"
#include "otx2_rx.h"
(NIX_MAX_FRS - NIX_L2_OVERHEAD)
#define NIX_MAX_SQB 512
-#define NIX_MIN_SQB 32
+#define NIX_DEF_SQB 16
+#define NIX_MIN_SQB 8
#define NIX_SQB_LIST_SPACE 2
#define NIX_RSS_RETA_SIZE_MAX 256
/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
#define NIX_CQ_ALIGN 512
#define NIX_SQB_LOWER_THRESH 90
#define LMT_SLOT_MASK 0x7f
+#define NIX_RX_DEFAULT_RING_SZ 4096
/* If PTP is enabled additional SEND MEM DESC is required which
* takes 2 words, hence max 7 iova address are possible
#define NIX_TX_NB_SEG_MAX 9
#endif
-/* Apply BP when CQ is 75% full */
-#define NIX_CQ_BP_LEVEL (25 * 256 / 100)
+#define NIX_TX_MSEG_SG_DWORDS \
+ ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
+ + NIX_TX_NB_SEG_MAX)
+
+/* Apply BP/DROP when CQ is 95% full */
+#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
+#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
#define CQ_OP_STAT_OP_ERR 63
#define CQ_OP_STAT_CQ_ERR 46
#define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
#define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
+#define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
+ * NIX_LF_CINTX_CNT[QCOUNT]
+ * crosses this value
+ */
+#define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
+#define CQ_TIMER_THRESH_MAX 255
+
#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
ETH_RSS_TCP | ETH_RSS_SCTP | \
ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
uint16_t nb_desc;
};
-struct otx2_npc_flow_info {
- uint16_t channel; /*rx channel */
- uint16_t flow_prealloc_size;
- uint16_t flow_max_priority;
-};
-
struct otx2_fc_info {
enum rte_eth_fc_mode mode; /**< Link flow control mode */
uint8_t rx_pause;
uint16_t bpid[NIX_MAX_CHAN];
};
+struct vlan_mkex_info {
+ struct npc_xtract_info la_xtract;
+ struct npc_xtract_info lb_xtract;
+ uint64_t lb_lt_offset;
+};
+
+struct vlan_entry {
+ uint32_t mcam_idx;
+ uint16_t vlan_id;
+ TAILQ_ENTRY(vlan_entry) next;
+};
+
+TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
+
+struct otx2_vlan_info {
+ struct otx2_vlan_filter_tbl fltr_tbl;
+ /* MKEX layer info */
+ struct mcam_entry def_tx_mcam_ent;
+ struct mcam_entry def_rx_mcam_ent;
+ struct vlan_mkex_info mkex;
+ /* Default mcam entry that matches vlan packets */
+ uint32_t def_rx_mcam_idx;
+ uint32_t def_tx_mcam_idx;
+ /* MCAM entry that matches double vlan packets */
+ uint32_t qinq_mcam_idx;
+ /* Indices of tx_vtag def registers */
+ uint32_t outer_vlan_idx;
+ uint32_t inner_vlan_idx;
+ uint16_t outer_vlan_tpid;
+ uint16_t inner_vlan_tpid;
+ uint16_t pvid;
+ /* QinQ entry allocated before default one */
+ uint8_t qinq_before_def;
+ uint8_t pvid_insert_on;
+ /* Rx vtag action type */
+ uint8_t vtag_type_idx;
+ uint8_t filter_on;
+ uint8_t strip_on;
+ uint8_t qinq_on;
+ uint8_t promisc_on;
+};
+
struct otx2_eth_dev {
OTX2_DEV; /* Base class */
MARKER otx2_eth_dev_data_start;
uint8_t lso_tsov4_idx;
uint8_t lso_tsov6_idx;
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
+ uint8_t mkex_pfl_name[MKEX_NAME_LEN];
uint8_t max_mac_entries;
uint8_t lf_tx_stats;
uint8_t lf_rx_stats;
uint16_t qints;
uint8_t configured;
uint8_t configured_qints;
+ uint8_t configured_cints;
uint8_t configured_nb_rx_qs;
uint8_t configured_nb_tx_qs;
uint16_t nix_msixoff;
uint64_t rx_offload_capa;
uint64_t tx_offload_capa;
struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
+ struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
uint16_t txschq[NIX_TXSCH_LVL_CNT];
uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
struct otx2_npc_flow_info npc_flow;
+ struct otx2_vlan_info vlan_info;
struct otx2_eth_qconf *tx_qconf;
struct otx2_eth_qconf *rx_qconf;
struct rte_eth_dev *eth_dev;
+ eth_rx_burst_t rx_pkt_burst_no_offload;
/* PTP counters */
bool ptp_en;
struct otx2_timesync_info tstamp;
struct rte_timecounter systime_tc;
struct rte_timecounter rx_tstamp_tc;
struct rte_timecounter tx_tstamp_tc;
+ double clk_freq_mult;
+ uint64_t clk_delta;
} __rte_cache_aligned;
struct otx2_eth_txq {
enum nix_q_size_e qsize;
struct rte_eth_dev *eth_dev;
struct otx2_eth_qconf qconf;
+ uint16_t cq_drop;
} __rte_cache_aligned;
static inline struct otx2_eth_dev *
}
/* Ops */
-void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
- struct rte_eth_dev_info *dev_info);
+int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_dev_info *dev_info);
+int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
+ enum rte_filter_type filter_type,
+ enum rte_filter_op filter_op, void *arg);
+int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
+ size_t fw_size);
int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_module_info *modinfo);
int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
-void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
-void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
+int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
+int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
+/* MTU */
+int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
+int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
+
/* Link */
void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
struct cgx_link_user_info *link);
+int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
+int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
/* IRQ */
int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
+int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
+void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
+
+int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
+ uint16_t rx_queue_id);
+int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
+ uint16_t rx_queue_id);
/* Debug */
int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
+/* VLAN */
+int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
+int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
+int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
+void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
+int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
+ int on);
+void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
+ uint16_t queue, int on);
+int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
+ enum rte_vlan_type type, uint16_t tpid);
+int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
+
/* Lookup configuration */
void *otx2_nix_fastpath_lookup_mem_get(void);
struct otx2_eth_dev *dev);
/* Rx and Tx routines */
+void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
+void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
/* Timesync - PTP routines */
int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
struct timespec *ts);
int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
+int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
+int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
#endif /* __OTX2_ETHDEV_H__ */
git.droids-corp.org / dpdk.git / blobdiff