net: add rte prefix to ether structures

[dpdk.git] / examples / l3fwd / l3fwd_neon.h

diff --git a/examples/l3fwd/l3fwd_neon.h b/examples/l3fwd/l3fwd_neon.h
index 42d50d3..af2dc47 100644 (file)
--- a/examples/l3fwd/l3fwd_neon.h
+++ b/examples/l3fwd/l3fwd_neon.h
@@ -1,38 +1,8 @@
-/*-
- *   BSD LICENSE
- *
- *   Copyright(c) 2016 Intel Corporation. All rights reserved.
- *   Copyright(c) 2017, Linaro Limited
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016-2018 Intel Corporation.
+ * Copyright(c) 2017-2018 Linaro Limited.
  */
 
-
 #ifndef _L3FWD_NEON_H_
 #define _L3FWD_NEON_H_
 
@@ -78,13 +48,13 @@ processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP])
        vst1q_u32(p[2], ve[2]);
        vst1q_u32(p[3], ve[3]);
 
-       rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[0] + 1),
+       rfc1812_process((struct ipv4_hdr *)((struct rte_ether_hdr *)p[0] + 1),
                &dst_port[0], pkt[0]->packet_type);
-       rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[1] + 1),
+       rfc1812_process((struct ipv4_hdr *)((struct rte_ether_hdr *)p[1] + 1),
                &dst_port[1], pkt[1]->packet_type);
-       rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[2] + 1),
+       rfc1812_process((struct ipv4_hdr *)((struct rte_ether_hdr *)p[2] + 1),
                &dst_port[2], pkt[2]->packet_type);
-       rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[3] + 1),
+       rfc1812_process((struct ipv4_hdr *)((struct rte_ether_hdr *)p[3] + 1),
                &dst_port[3], pkt[3]->packet_type);
 }
 
@@ -114,6 +84,7 @@ port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, uint16x8_t dp1,
 
        /* update last port counter. */
        lp[0] += gptbl[v].lpv;
+       rte_compiler_barrier();
 
        /* if dest port value has changed. */
        if (v != GRPMSK) {
@@ -133,10 +104,10 @@ port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, uint16x8_t dp1,
 static inline void
 process_packet(struct rte_mbuf *pkt, uint16_t *dst_port)
 {
-       struct ether_hdr *eth_hdr;
+       struct rte_ether_hdr *eth_hdr;
        uint32x4_t te, ve;
 
-       eth_hdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *);
+       eth_hdr = rte_pktmbuf_mtod(pkt, struct rte_ether_hdr *);
 
        te = vld1q_u32((uint32_t *)eth_hdr);
        ve = vreinterpretq_u32_s32(val_eth[dst_port[0]]);
@@ -192,7 +163,7 @@ send_packets_multi(struct lcore_conf *qconf, struct rte_mbuf **pkts_burst,
                         * dp1:
                         * <d[j], d[j+1], d[j+2], d[j+3], ... >
                         */
-                       dp1 = vextq_u16(dp1, dp1, FWDSTEP - 1);
+                       dp1 = vextq_u16(dp2, dp1, FWDSTEP - 1);
                }
 
                /*