mem: rename segment address from physical to IOVA

[dpdk.git] / lib / librte_eal / common / include / rte_memory.h

diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h
index 7f21244..d16b284 100644 (file)
--- a/lib/librte_eal/common/include/rte_memory.h
+++ b/lib/librte_eal/common/include/rte_memory.h
@@ -42,61 +42,88 @@
 
 #include <stdint.h>
 #include <stddef.h>
-
-#ifdef RTE_EXEC_ENV_LINUXAPP
-#include <exec-env/rte_dom0_common.h>
-#endif
+#include <stdio.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include <rte_common.h>
+
+__extension__
 enum rte_page_sizes {
-       RTE_PGSIZE_4K = 1 << 12,
-       RTE_PGSIZE_2M = RTE_PGSIZE_4K << 9,
-       RTE_PGSIZE_1G = RTE_PGSIZE_2M <<9
+       RTE_PGSIZE_4K    = 1ULL << 12,
+       RTE_PGSIZE_64K   = 1ULL << 16,
+       RTE_PGSIZE_256K  = 1ULL << 18,
+       RTE_PGSIZE_2M    = 1ULL << 21,
+       RTE_PGSIZE_16M   = 1ULL << 24,
+       RTE_PGSIZE_256M  = 1ULL << 28,
+       RTE_PGSIZE_512M  = 1ULL << 29,
+       RTE_PGSIZE_1G    = 1ULL << 30,
+       RTE_PGSIZE_4G    = 1ULL << 32,
+       RTE_PGSIZE_16G   = 1ULL << 34,
 };
 
 #define SOCKET_ID_ANY -1                    /**< Any NUMA socket. */
-#ifndef CACHE_LINE_SIZE
-#define CACHE_LINE_SIZE 64                  /**< Cache line size. */
-#endif
-#define CACHE_LINE_MASK (CACHE_LINE_SIZE-1) /**< Cache line mask. */
+#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */
 
-#define CACHE_LINE_ROUNDUP(size) \
-       (CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE))
+#define RTE_CACHE_LINE_ROUNDUP(size) \
+       (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
 /**< Return the first cache-aligned value greater or equal to size. */
 
+/**< Cache line size in terms of log2 */
+#if RTE_CACHE_LINE_SIZE == 64
+#define RTE_CACHE_LINE_SIZE_LOG2 6
+#elif RTE_CACHE_LINE_SIZE == 128
+#define RTE_CACHE_LINE_SIZE_LOG2 7
+#else
+#error "Unsupported cache line size"
+#endif
+
+#define RTE_CACHE_LINE_MIN_SIZE 64     /**< Minimum Cache line size. */
+
 /**
  * Force alignment to cache line.
  */
-#define __rte_cache_aligned __attribute__((__aligned__(CACHE_LINE_SIZE)))
+#define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE)
 
-typedef uint64_t phys_addr_t; /**< Physical address definition. */
+/**
+ * Force minimum cache line alignment.
+ */
+#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
+
+typedef uint64_t phys_addr_t; /**< Physical address. */
 #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)
+/**
+ * IO virtual address type.
+ * When the physical addressing mode (IOVA as PA) is in use,
+ * the translation from an IO virtual address (IOVA) to a physical address
+ * is a direct mapping, i.e. the same value.
+ * Otherwise, in virtual mode (IOVA as VA), an IOMMU may do the translation.
+ */
+typedef uint64_t rte_iova_t;
+#define RTE_BAD_IOVA ((rte_iova_t)-1)
 
 /**
  * Physical memory segment descriptor.
  */
 struct rte_memseg {
-       phys_addr_t phys_addr;      /**< Start physical address. */
+       RTE_STD_C11
+       union {
+               phys_addr_t phys_addr;  /**< deprecated - Start physical address. */
+               rte_iova_t iova;        /**< Start IO address. */
+       };
+       RTE_STD_C11
        union {
                void *addr;         /**< Start virtual address. */
                uint64_t addr_64;   /**< Makes sure addr is always 64 bits */
        };
-#ifdef RTE_LIBRTE_IVSHMEM
-       phys_addr_t ioremap_addr; /**< Real physical address inside the VM */
-#endif
        size_t len;               /**< Length of the segment. */
-       size_t hugepage_sz;       /**< The pagesize of underlying memory */
+       uint64_t hugepage_sz;       /**< The pagesize of underlying memory */
        int32_t socket_id;          /**< NUMA socket ID. */
        uint32_t nchannel;          /**< Number of channels. */
        uint32_t nrank;             /**< Number of ranks. */
-#ifdef RTE_LIBRTE_XEN_DOM0
-        /**< store segment MFNs */
-       uint64_t mfn[DOM0_NUM_MEMBLOCK];
-#endif
-} __attribute__((__packed__));
+} __rte_packed;
 
 /**
  * Lock page in physical memory and prevent from swapping.
@@ -116,7 +143,7 @@ int rte_mem_lock_page(const void *virt);
  * @param virt
  *   The virtual address.
  * @return
- *   The physical address or RTE_BAD_PHYS_ADDR on error.
+ *   The physical address or RTE_BAD_IOVA on error.
  */
 phys_addr_t rte_mem_virt2phy(const void *virt);
 
@@ -138,7 +165,7 @@ phys_addr_t rte_mem_virt2phy(const void *virt);
 const struct rte_memseg *rte_eal_get_physmem_layout(void);
 
 /**
- * Dump the physical memory layout to the console.
+ * Dump the physical memory layout to a file.
  *
  * @param f
  *   A pointer to a file for output
@@ -171,42 +198,17 @@ unsigned rte_memory_get_nchannel(void);
  */
 unsigned rte_memory_get_nrank(void);
 
-#ifdef RTE_LIBRTE_XEN_DOM0
-/**
- * Return the physical address of elt, which is an element of the pool mp.
- *
- * @param memseg_id
- *   The mempool is from which memory segment.
- * @param phy_addr
- *   physical address of elt.
- *
- * @return
- *   The physical address or error.
- */
-phys_addr_t rte_mem_phy2mch(uint32_t memseg_id, const phys_addr_t phy_addr);
-
 /**
- * Memory init for supporting application running on Xen domain0.
- *
- * @param void
+ * Drivers based on uio will not load unless physical
+ * addresses are obtainable. It is only possible to get
+ * physical addresses when running as a privileged user.
  *
  * @return
- *       0: successfully
- *      negative: error
+ *   1 if the system is able to obtain physical addresses.
+ *   0 if using DMA addresses through an IOMMU.
  */
-int rte_xen_dom0_memory_init(void);
+int rte_eal_using_phys_addrs(void);
 
-/**
- * Attach to memory setments of primary process on Xen domain0.
- *
- * @param void
- *
- * @return
- *       0: successfully
- *       negative: error
- */
-int rte_xen_dom0_memory_attach(void);
-#endif
 #ifdef __cplusplus
 }
 #endif