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(parent: 68bda43) | patch
examples/ipsec-secgw: fix SPI byte order in flow item
authorNélio Laranjeiro <nelio.laranjeiro@6wind.com>
Thu, 11 Jan 2018 09:15:59 +0000 (10:15 +0100)
committerPablo de Lara <pablo.de.lara.guarch@intel.com>
Sat, 20 Jan 2018 15:10:53 +0000 (16:10 +0100)
commit0bca1d26780e2cdbe03a2cf007839cbba8c830c8
tree4b449287cbd005b4e1380fc2e27bd62e57940d91tree | snapshot
parent68bda436a35c0fcad1dcc86ea6559361f87f64d5commit | diff
examples/ipsec-secgw: fix SPI byte order in flow item

SPI field is defined in the RFC2406 [1] as a big endian field it should be
provided in its final form to the drivers through RTE flow.

[1] https://tools.ietf.org/html/rfc2406

Fixes: ec17993a145a ("examples/ipsec-secgw: support security offload")
Cc: stable@dpdk.org
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
examples/ipsec-secgw/ipsec.c diff | blob | history
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