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(parent: 515e4ea) | patch
net/enetc: init SI transactions attribute register
authorAlex Marginean <alexandru.marginean@nxp.com>
Mon, 2 Mar 2020 14:32:09 +0000 (20:02 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Wed, 18 Mar 2020 09:21:41 +0000 (10:21 +0100)
commitd84612e9bd6b2f106558ffb515d32000288ee73d
tree5ec6ca2f7717b71c93f0985da29630993c78eb62tree | snapshot
parent515e4eab2bfea860ed0176a35f8dfa9f14a6ef0ccommit | diff
net/enetc: init SI transactions attribute register

This was left to its default value.  With the patch transactions are:
- coherent,
- do not allocate in downstream cache (there is none on LS1028a),
- merge surrounding data for BD writes,
- overwrite surrounding data for frame data writes.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Gagandeep Singh <g.singh@nxp.com>
drivers/net/enetc/base/enetc_hw.h diff | blob | history
drivers/net/enetc/enetc_ethdev.c diff | blob | history
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