net/mlx5: fix eCPRI common header endianness
authorBing Zhao <bingz@nvidia.com>
Tue, 3 Nov 2020 05:41:58 +0000 (13:41 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 13 Nov 2020 15:26:54 +0000 (16:26 +0100)
commitebda282cbb1066af2e2c14770bb36572ecf6ba95
treeebfa935425ba7e32d1e1f63b1633d7bc8762542d
parente6dc14c8008c1e559bd75a5c9eba4b39e0e07d33
net/mlx5: fix eCPRI common header endianness

The input header of a RTE flow item is with network byte order. In
the host with little endian, the bit field order are the same as the
byte order.
When checking the eCPRI message type, the wrong field will be selected.
Fixing to use correct field.

Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
drivers/net/mlx5/mlx5_flow_dv.c