dpdk.git
3 years agoexamples/l3fwd: skip Tx queue drain on first iteration
Kathleen Capella [Thu, 8 Apr 2021 21:35:49 +0000 (21:35 +0000)]
examples/l3fwd: skip Tx queue drain on first iteration

Initialize prev_tsc to cur_tsc. This avoids running the TX queue drain
in the first iteration of the packet processing loop.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
3 years agoexamples/ptpclient: remove wrong comment
Min Hu (Connor) [Sat, 27 Mar 2021 07:36:26 +0000 (15:36 +0800)]
examples/ptpclient: remove wrong comment

This patch deletes the comments which are wrong and unnecessary.

Fixes: ab129e9065a5 ("examples/ptpclient: add minimal PTP client")
Cc: stable@dpdk.org
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
3 years agoexamples/pipeline: add newline to error messages
Cristian Dumitrescu [Wed, 31 Mar 2021 13:51:53 +0000 (14:51 +0100)]
examples/pipeline: add newline to error messages

Add newline to some error messages that were missing it.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agopipeline: fix endianness conversions
Cristian Dumitrescu [Sat, 3 Apr 2021 00:17:09 +0000 (01:17 +0100)]
pipeline: fix endianness conversions

The SWX pipeline instructions work with operands of different types:
header fields (h.header.field), packet meta-data (m.field), extern
object mailbox field (e.obj.field), extern function (f.field), action
data read from table entries (t.field), or immediate values; hence the
HMEFTI acronym. The H operands are stored in network byte order (NBO),
while the MEFT operands are stored in host byte order (HBO), hence the
need to operate endianness conversions.

Some of the endianness conversion macros were not working correctly
for some cases such as operands of different sizes, and they are fixed
now. Affected instructions: mov, and, or, xor, jmpeq, jmpneq.

Fixes: 7210349d5baa ("pipeline: add SWX move instruction")
Fixes: 650195cf965a ("pipeline: introduce SWX and instruction")
Fixes: 8f796198dcda ("pipeline: introduce SWX or instruction")
Fixes: b4e607f9fd5e ("pipeline: introduce SWX XOR instruction")
Fixes: b3947e25bed4 ("pipeline: introduce SWX jump and return instructions")
Cc: stable@dpdk.org
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agopipeline: adjust error code for internal function
Cristian Dumitrescu [Tue, 30 Mar 2021 10:19:04 +0000 (11:19 +0100)]
pipeline: adjust error code for internal function

Adjusting the error code for the internal function instruction_config
to match the rest of the code which is returning a negative value on
error. Cosmetic change.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agopipeline: validate header on SWX emit
Cristian Dumitrescu [Fri, 26 Mar 2021 20:29:35 +0000 (20:29 +0000)]
pipeline: validate header on SWX emit

Enhance the behavior of the emit instruction to ignore invalid
headers, as mandated by the P4 language specification.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agopipeline: add table statistics to SWX
Cristian Dumitrescu [Fri, 16 Apr 2021 23:46:41 +0000 (00:46 +0100)]
pipeline: add table statistics to SWX

Add support for table statistics for the SWX pipeline. For each table,
we maintain a counter for lookup hit packets, one for lookup miss
packets and one packet counter for each table action.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com>
3 years agopipeline: add drop instruction to SWX
Cristian Dumitrescu [Fri, 26 Mar 2021 22:11:08 +0000 (22:11 +0000)]
pipeline: add drop instruction to SWX

Enabled the TX instruction to accept an immediate value for the output
port argument. The drop instruction is simply an alias to the TX
instruction for the last output port of the pipeline.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agopipeline: relax table match field requirements
Cristian Dumitrescu [Thu, 15 Apr 2021 21:15:35 +0000 (22:15 +0100)]
pipeline: relax table match field requirements

The match fields for a given table have to be part of the same header
or the metadata structure. This commit removes the requirement that
the list of match fields must observe the order of fields within their
structure. For example, the h.ipv4.dst_addr field can now be listed
before the h.ipv4.src_addr field in a table match field list, even
though within the IPv4 header the dst_addr field is present after the
src_addr field.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agotable: relax requirements for entry action data
Churchill Khangar [Fri, 26 Mar 2021 20:22:24 +0000 (20:22 +0000)]
table: relax requirements for entry action data

Currently, the table entry action data is required to be NULL when the
action data size is zero. We now require that action data is ignored
when the action data size is zero. This is to allow for a table entry
instance to be allocated once with max action data size for the table
and reused repeatedly for actions of different sizes, including zero.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Churchill Khangar <churchill.khangar@intel.com>
3 years agotable: fix out of bounds write
Cristian Dumitrescu [Wed, 7 Apr 2021 10:59:53 +0000 (11:59 +0100)]
table: fix out of bounds write

Fix out of bounds write. The allocated string size was incorrect.

Coverity issue: 369670
Fixes: 66440b7b22f2 ("table: add wildcard match table type")

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agoport: fix allocation check in ring SWX
Cristian Dumitrescu [Wed, 7 Apr 2021 10:59:45 +0000 (11:59 +0100)]
port: fix allocation check in ring SWX

Fix logically dead code in ring port.

Coverity issue: 369664
Fixes: 77a413017c2d ("port: add ring SWX port")

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agodevargs: fix list entry update
Xueming Li [Sat, 17 Apr 2021 15:15:32 +0000 (23:15 +0800)]
devargs: fix list entry update

When inserting devargs that is already in list,
existing one was reset and replaced completely by new one,
the entry info was lost during copy.

This patch backups entry info before copy.

Fixes: 64051bb1f144 ("devargs: unify scratch buffer storage")

Reported-by: Jim Harris <james.r.harris@intel.com>
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
3 years agovfio: fix duplicated user mem map
Yunjian Wang [Sat, 10 Apr 2021 09:37:57 +0000 (17:37 +0800)]
vfio: fix duplicated user mem map

Currently, new user mem maps are checked if they are adjacent to
an existing mem map and if so, the mem map entries are merged.

It didn't check for duplicate mem maps, so if the API is called
with the same mem map multiple times, they will occupy multiple
mem map entries. This will reduce the amount of entries available
for unique mem maps.

So check for duplicate mem maps and merge them into one mem map
entry if any found.

Fixes: 0cbce3a167f1 ("vfio: skip DMA map failure if already mapped")
Cc: stable@dpdk.org
Suggested-by: Kevin Traynor <ktraynor@redhat.com>
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
3 years agopower: replace unsigned -1 with unsigned maximum
Tyler Retzlaff [Tue, 16 Mar 2021 00:13:31 +0000 (17:13 -0700)]
power: replace unsigned -1 with unsigned maximum

Use UINT64_MAX instead of -1ULL.

Some compilers generate a warning when applying a '-' to
an unsigned literal so avoid this by initializing with
unsigned preprocessor definition.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
3 years agoeal: replace unsigned -1 with unsigned maximums
Tyler Retzlaff [Tue, 16 Mar 2021 00:13:31 +0000 (17:13 -0700)]
eal: replace unsigned -1 with unsigned maximums

Use UINT64_MAX and UINT32_MAX instead of -1 or ~0 literal variations
of different explicit widths when creating masks and sentinel values.

Some compilers generate a warning when applying a '-' to an unsigned
literal so avoid this by initializing with unsigned preprocessor
definitions where appropriate.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
3 years agoeal: check vsnprintf failure in devargs parsing
Tyler Retzlaff [Mon, 15 Mar 2021 23:55:24 +0000 (16:55 -0700)]
eal: check vsnprintf failure in devargs parsing

Check for failure, while here just increment len once after checking for
failure instead of duplicating len + 1 math in two different argument
lists.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
3 years agoconfig/arm: add Hisilicon kunpeng
Chengchang Tang [Fri, 16 Apr 2021 09:57:03 +0000 (17:57 +0800)]
config/arm: add Hisilicon kunpeng

Here adds configs for Kunpeng server.

Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agoeventdev: fix case to initiate crypto adapter service
Shijith Thotton [Mon, 12 Apr 2021 08:53:39 +0000 (14:23 +0530)]
eventdev: fix case to initiate crypto adapter service

Initiate software crypto adapter service, only if hardware capabilities
are not reported. In OP_FORWARD mode, software service is not required
to enqueue events if OP_FORWARD capability is supported by the PMD.

Fixes: 7901eac3409a ("eventdev: add crypto adapter implementation")
Cc: stable@dpdk.org
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
3 years agotest/event_crypto: use crypto adapter enqueue API
Shijith Thotton [Thu, 15 Apr 2021 09:13:51 +0000 (14:43 +0530)]
test/event_crypto: use crypto adapter enqueue API

Use rte_event_crypto_adapter_enqueue() API to enqueue events to crypto
adapter if forward mode is supported in driver.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
3 years agoevent/octeontx2: support crypto adapter forward mode
Shijith Thotton [Thu, 15 Apr 2021 09:13:50 +0000 (14:43 +0530)]
event/octeontx2: support crypto adapter forward mode

Advertise crypto adapter forward mode capability and set crypto adapter
enqueue function in driver.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
3 years agoeventdev: introduce crypto adapter enqueue API
Akhil Goyal [Thu, 15 Apr 2021 09:13:49 +0000 (14:43 +0530)]
eventdev: introduce crypto adapter enqueue API

In case an event from a previous stage is required to be forwarded
to a crypto adapter and PMD supports internal event port in crypto
adapter, exposed via capability
RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD, we do not have
a way to check in the API rte_event_enqueue_burst(), whether it is
for crypto adapter or for eth tx adapter.

Hence we need a new API similar to rte_event_eth_tx_adapter_enqueue(),
which can send to a crypto adapter.

Note that RTE_EVENT_TYPE_* cannot be used to make that decision,
as it is meant for event source and not event destination.
And event port designated for crypto adapter is designed to be used
for OP_NEW mode.

Hence, in order to support an event PMD which has an internal event port
in crypto adapter (RTE_EVENT_CRYPTO_ADAPTER_OP_FORWARD mode), exposed
via capability RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD,
application should use rte_event_crypto_adapter_enqueue() API to enqueue
events.

When internal port is not available(RTE_EVENT_CRYPTO_ADAPTER_OP_NEW mode),
application can use API rte_event_enqueue_burst() as it was doing earlier,
i.e. retrieve event port used by crypto adapter and bind its event queues
to that port and enqueue events using the API rte_event_enqueue_burst().

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agonet/ice: add Rx AVX512 offload path
Leyi Rong [Thu, 15 Apr 2021 08:58:11 +0000 (16:58 +0800)]
net/ice: add Rx AVX512 offload path

Split AVX512 Rx data path into two, one is for basic,
the other one can support additional Rx offload features,
including Rx checksum offload, Rx vlan offload, RSS offload.

Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: Qin Sun <qinx.sun@intel.com>
3 years agonet/ice: add Tx AVX512 offload path
Leyi Rong [Thu, 15 Apr 2021 08:58:10 +0000 (16:58 +0800)]
net/ice: add Tx AVX512 offload path

Add alternative Tx data path for AVX512 which can support partial
Tx offload features, including Tx checksum offload, vlan/QinQ
insertion offload.

Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: Qin Sun <qinx.sun@intel.com>
3 years agonet/iavf: fix lack of MAC type when set MAC address
Robin Zhang [Fri, 19 Mar 2021 09:20:19 +0000 (09:20 +0000)]
net/iavf: fix lack of MAC type when set MAC address

When set default MAC address, use type VIRTCHNL_ETHER_ADDR_PRIMARY as this
case is changing device/primary unicast MAC. For other cases, such as
adding or deleting extra unicast addresses and multicast addresses, use
type VIRTCHNL_ETHER_ADDR_EXTRA.

Fixes: cb25d4323fbf ("net/avf: enable MAC VLAN and promisc ops")
Cc: stable@dpdk.org
Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
Tested-by: Yan Xia <yanx.xia@intel.com>
3 years agonet/i40e: fix lack of MAC type when set MAC address
Robin Zhang [Fri, 19 Mar 2021 09:20:18 +0000 (09:20 +0000)]
net/i40e: fix lack of MAC type when set MAC address

Currently, there is no way for a VF driver to specify that it wants to
change its device/primary unicast MAC address. This makes it
difficult/impossible for the PF driver to track the VF's device/primary
unicast MAC address, which is used for VM/VF reboot and displaying on
the host. Fix this by using 2 bits of a pad byte in the
virtchnl_ether_addr structure so the VF can specify what type of MAC
it's adding/deleting.

Below are the values that should be used by all VF drivers going
forward.

VIRTCHNL_ETHER_ADDR_LEGACY(0):
- The type should only ever be 0 for legacy AVF drivers (i.e.
  drivers that don't support the new type bits). The PF drivers
  will track VF's device/primary unicast MAC using with best
  effort.

VIRTCHNL_ETHER_ADDR_PRIMARY(1):
- This type should only be used when the VF is changing their
  device/primary unicast MAC. It should be used for both delete
  and add cases related to the device/primary unicast MAC.

VIRTCHNL_ETHER_ADDR_EXTRA(2):
- This type should be used when the VF is adding and/or deleting
  MAC addresses that are not the device/primary unicast MAC. For
  example, extra unicast addresses and multicast addresses
  assuming the PF supports "extra" addresses at all.

If a PF is parsing the type field of the virtchnl_ether_addr, then it
should use the VIRTCHNL_ETHER_ADDR_TYPE_MASK to mask the first two bits
of the type field since 0, 1, and 2 are the only valid values.

For i40evf PMD, when set default MAC address, use type
VIRTCHNL_ETHER_ADDR_PRIMARY as this case is changing device/primary
unicast MAC. For other cases, such as adding or deleting extra unicast
addresses and multicast addresses, use type VIRTCHNL_ETHER_ADDR_EXTRA.

Fixes: 6d13ea8e8e49 ("net: add rte prefix to ether structures")
Fixes: caccf8b318ca ("ethdev: return diagnostic when setting MAC address")
Cc: stable@dpdk.org
Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
Tested-by: Yan Xia <yanx.xia@intel.com>
3 years agonet/ice: support flow priority for DCF switch filter
Yuying Zhang [Thu, 15 Apr 2021 15:38:45 +0000 (15:38 +0000)]
net/ice: support flow priority for DCF switch filter

Support rte flow priority attribute for DCF switch filter.
When a packet is matched by two rules, the behavior of it
is not defined. This patch supports flow priority to create
different recipes for this situation. Only priority 0 and 1
are supported and higher value denotes higher priority.

for example:
1. flow create 0 priority 0 ingress pattern eth / vlan tci is 2 / vlan
   tci is 2 / end actions vf id 2 / end
2. flow create 0 priority 1 ingress pattern eth / vlan / vlan / ipv4 dst
   is 192.168.0.1 / end actions vf id 1 / end

These two rules can be created at the same time in DCF switch
filter and priority of rule 2 is higher. Packet hits rule 2
when two conditions of rules are satisfied.

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/i40e: support 25G AOC/ACC cables
Yury Kylulin [Tue, 13 Apr 2021 15:29:50 +0000 (18:29 +0300)]
net/i40e: support 25G AOC/ACC cables

Enable additional PHY types (25G-AOC and 25G-ACC) for set PHY config
command.

Signed-off-by: Yury Kylulin <yury.kylulin@intel.com>
Tested-by: Ashish Paul <apaul@juniper.net>
3 years agonet/ice: support GTPU TEID pattern for switch filter
Yuying Zhang [Thu, 15 Apr 2021 10:47:51 +0000 (10:47 +0000)]
net/ice: support GTPU TEID pattern for switch filter

Enable GTPU pattern for CVL switch filter. Support teid and
qfi field of GTPU pattern. Patterns without inner l3/l4 field
support outer dst/src ip. Patterns with inner l3/l4 field only
support inner dst/src ip and inner dst/src port.

+----------------------------------+------------------------------------+
| Pattern                          | Input Set                          |
+----------------------------------+------------------------------------+
| pattern_eth_ipv4_gtpu            | teid, dst/src ip                   |
| pattern_eth_ipv6_gtpu            | teid, dst/src ip                   |
| pattern_eth_ipv4_gtpu_ipv4       | teid, dst/src ip                   |
| pattern_eth_ipv4_gtpu_ipv4_tcp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv4_gtpu_ipv4_udp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv4_gtpu_ipv6       | teid, dst/src ip                   |
| pattern_eth_ipv4_gtpu_ipv6_tcp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv4_gtpu_ipv6_udp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv6_gtpu_ipv4       | teid, dst/src ip                   |
| pattern_eth_ipv6_gtpu_ipv4_tcp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv6_gtpu_ipv4_udp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv6_gtpu_ipv6       | teid, dst/src ip                   |
| pattern_eth_ipv6_gtpu_ipv6_tcp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv6_gtpu_ipv6_udp   | teid, dst/src ip, dst/src port     |
| pattern_eth_ipv4_gtpu_eh_ipv4    | teid, qfi, dst/src ip              |
| pattern_eth_ipv4_gtpu_eh_ipv4_tcp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv4_gtpu_eh_ipv4_udp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv4_gtpu_eh_ipv6    | teid, qfi, dst/src ip              |
| pattern_eth_ipv4_gtpu_eh_ipv6_tcp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv4_gtpu_eh_ipv6_udp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv6_gtpu_eh_ipv4    | teid, qfi, dst/src ip              |
| pattern_eth_ipv6_gtpu_eh_ipv4_tcp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv6_gtpu_eh_ipv4_udp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv6_gtpu_eh_ipv6    | teid, qfi, dst/src ip              |
| pattern_eth_ipv6_gtpu_eh_ipv6_tcp| teid, qfi, dst/src ip, dst/src port|
| pattern_eth_ipv6_gtpu_eh_ipv6_udp| teid, qfi, dst/src ip, dst/src port|
+----------------------------------+------------------------------------+

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice/base: support GTPU for DCF switch filter
Yuying Zhang [Thu, 15 Apr 2021 10:47:50 +0000 (10:47 +0000)]
net/ice/base: support GTPU for DCF switch filter

Enable GTPU filtering for DCF switch filter.

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/mlx5: separate Tx burst functions to different files
Michael Baum [Mon, 12 Apr 2021 06:32:25 +0000 (06:32 +0000)]
net/mlx5: separate Tx burst functions to different files

This patch separates Tx burst function implementations to different
source files, thus allowing them to compile in parallel.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: separate Tx function implementations to new file
Michael Baum [Mon, 12 Apr 2021 06:32:24 +0000 (06:32 +0000)]
net/mlx5: separate Tx function implementations to new file

This patch separates Tx function implementations to different source
file as an optional preparation step for Tx cleanup.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: separate Tx burst template to header file
Michael Baum [Mon, 12 Apr 2021 06:32:23 +0000 (06:32 +0000)]
net/mlx5: separate Tx burst template to header file

This patch moves Tx burst and its inline functions declarations to
header file to allow its use from several separate source files and as a
possible preparation for Tx cleanup.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: separate Tx function declarations to another file
Michael Baum [Mon, 12 Apr 2021 06:32:22 +0000 (06:32 +0000)]
net/mlx5: separate Tx function declarations to another file

This patch separates Tx function declarations to different header file
in preparation for removing their implementation from the source file
and as an optional preparation for Tx cleanup.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: separate Rx function implementations to new file
Michael Baum [Mon, 12 Apr 2021 06:32:21 +0000 (06:32 +0000)]
net/mlx5: separate Rx function implementations to new file

This patch separates Rx function implementations to different source
file as an optional preparation step for further consolidation of Rx
burst functions.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: separate Rx function declarations to another file
Michael Baum [Mon, 12 Apr 2021 06:32:20 +0000 (06:32 +0000)]
net/mlx5: separate Rx function declarations to another file

The mlx5_rxtx.c file contains a lot of Tx burst functions, each of those
is performance-optimized for the specific set of requested offloads.
These ones are generated on the basis of the template function and it
takes significant time to compile, just due to a large number of giant
functions generated in the same file and this compilation is not being
done in parallel with using multithreading.

Therefore we can split the mlx5_rxtx.c file into several separate files
to allow different functions to be compiled simultaneously.
In this patch, we separate Rx function declarations to different header
file in preparation for removing them from the source file and as an
optional preparation step for further consolidation of Rx burst
functions.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/hns3: rename Rx burst function
Chengwen Feng [Thu, 15 Apr 2021 08:35:21 +0000 (16:35 +0800)]
net/hns3: rename Rx burst function

Currently, user could use runtime config "rx_func_hint=simple" to
select the hns3_recv_pkts API, but the API's name get from
rte_eth_rx_burst_mode_get is "Scalar" which has not reflected "simple".

So this patch renames hns3_recv_pkts to hns3_recv_pkts_simple, and
also change it's name which gets from rte_eth_rx_burst_mode_get to
"Scalar Simple" to maintain conceptual consistency.

Fixes: 521ab3e93361 ("net/hns3: add simple Rx path")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
3 years agonet/virtio: fix kernel set owner for multi-queue devices
Thierry Herbelot [Thu, 8 Apr 2021 12:37:29 +0000 (14:37 +0200)]
net/virtio: fix kernel set owner for multi-queue devices

Restore the original code, where VHOST_SET_OWNER is applied to
all vhostfds of the device.

Fixes: 06856cabb89b ("net/virtio: add virtio-user ops to set owner")
Cc: stable@dpdk.org
Signed-off-by: Thierry Herbelot <thierry.herbelot@6wind.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
3 years agonet/hns3: support fixed link speed
Huisong Li [Tue, 13 Apr 2021 13:47:19 +0000 (21:47 +0800)]
net/hns3: support fixed link speed

This patch adds the configuration of fixed speed for the PF device.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: support flow control autoneg for copper port
Huisong Li [Tue, 13 Apr 2021 13:47:18 +0000 (21:47 +0800)]
net/hns3: support flow control autoneg for copper port

If the flow control auto-negotiation is not supported and the flow
control modes on the local and link partner is asymmetric, the flow
control on the NIC does not take effect. The support of the
auto-negotiation capability requires the cooperation of the firmware
and driver.

This patch supports the flow control auto-negotiation only for copper
port. For optical ports, the forced flow control mode is still used.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: support link speed autoneg for PF
Huisong Li [Tue, 13 Apr 2021 13:47:17 +0000 (21:47 +0800)]
net/hns3: support link speed autoneg for PF

This patch supports link speed auto-negotiation for PF. If the
device supports auto-negotiation, the device negotiates with
the link partner at all speeds supported by the device.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: report speed capability for PF
Huisong Li [Tue, 13 Apr 2021 13:47:16 +0000 (21:47 +0800)]
net/hns3: report speed capability for PF

The speed capability of the device can be reported to the upper-layer app
in rte_eth_dev_info_get API. In this API, the speed capability is derived
from the 'supported_speed', which is the speed capability actually
supported by the NIC. The value of the 'supported_speed' is obtained
once in the probe stage and may be updated in the scheduled task to deal
with the change of the transmission interface.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: obtain supported speed for fiber port
Huisong Li [Tue, 13 Apr 2021 13:47:15 +0000 (21:47 +0800)]
net/hns3: obtain supported speed for fiber port

Currently, the speed of fiber port is obtained by using the default
query type of HNS3_OPC_GET_SFP_INFO opcode. In this way, only
the speed of the optical module can be obtained. In fact, the opcode
also supports an active query type, which is a channel for obtaining
information such as the speed, the supported speed, auto-negotiation
capability, and FEC mode. This patch changes the query type of the
opcode from the default query type to the active query type to obtain
the supported speed of fiber port.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix firmware compatibility configuration
Huisong Li [Tue, 13 Apr 2021 13:47:14 +0000 (21:47 +0800)]
net/hns3: fix firmware compatibility configuration

The firmware compatibility configuration in PF driver is used to
maintain the compatibility of some features of the driver and
firmware, and requires firmware to enable these features. Currently,
the configuration is in hns3_init_hardware(), which is a little back.
Because firmware may clear some configurations (such as, MAC related)
after receiving the command. And firmware can not be aware of some
default initializations (such as, flow control) before executing the
command to set the copper PHY when the PHY is controlled by firmware.
Therefore, it is recommended that no other hardware resources are
configured before the compatibility configuration. And it should be
moved to hns3_cmd_init(), which is responsible for the firmware
command initialization of driver.

In addition, the driver needs to perform corresponding processing
if the command fails to be sent.
1) If firmware fails to take over the copper PHY, the copper port fails
   to initialize.
2) If fails to enable the report of link events, the device does not
   support the LSC capability.

Fixes: bff6ebfe30d4 ("net/hns3: refactor PF LSC event report")
Fixes: bac6a0644121 ("net/hns3: fix link status change from firmware")
Cc: stable@dpdk.org
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix flow control mode
Huisong Li [Tue, 13 Apr 2021 13:47:13 +0000 (21:47 +0800)]
net/hns3: fix flow control mode

Currently, hns3 driver doesn't support to flow control auto-negotiation.
The FC mode requested by user is the same as the current FC mode. It is
not necessary to maintain the current FC mode. We only report the current
FC mode based on actual flow control mode in hns3_flow_ctrl_get().

This patch removes this redundant field. In addition, "requested_mode" in
hns3_hw struct indicates the FC mode requested by user, and the name is
unreasonable. It needs to be modified to "requested_fc_mode".

Fixes: 62e3ccc2b94c ("net/hns3: support flow control")
Cc: stable@dpdk.org
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: add 1000M speed bit for copper PHYs
Huisong Li [Tue, 13 Apr 2021 13:47:12 +0000 (21:47 +0800)]
net/hns3: add 1000M speed bit for copper PHYs

The bit(5) of supported, advertising and lp_advertising for copper
PHYs obtained from the firmware indicates 1000M full-duplex. This
speed capability bit is missing in the current codes.

Fixes: 2e4859f3b362 ("net/hns3: support PF device with copper PHYs")

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix supported speed of copper ports
Huisong Li [Tue, 13 Apr 2021 13:47:11 +0000 (21:47 +0800)]
net/hns3: fix supported speed of copper ports

The "supported capability" obtained from firmware on copper ports
includes the speed capability, auto-negotiation capability, and flow
control capability. Therefore, this patch changes "supported_capa" to
"supported_speed" and parses the speed capability supported by the
driver from the "supported capability".

Fixes: 2e4859f3b362 ("net/hns3: support PF device with copper PHYs")

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: remove VLAN/QinQ ptypes from support list
Chengwen Feng [Tue, 13 Apr 2021 11:50:11 +0000 (19:50 +0800)]
net/hns3: remove VLAN/QinQ ptypes from support list

In the previous patch, driver will calculate packet type by ignoring
VLAN information because the packet type may calculate error when
exist VLAN and VLAN strip.

So here remove the following ptypes from support list:
1) RTE_PTYPE_L2_ETHER_VLAN
2) RTE_PTYPE_L2_ETHER_QINQ
3) RTE_PTYPE_INNER_L2_ETHER_VLAN
4) RTE_PTYPE_INNER_L2_ETHER_QINQ

Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: list supported ptypes for advanced Rx descriptor
Chengwen Feng [Tue, 13 Apr 2021 11:50:10 +0000 (19:50 +0800)]
net/hns3: list supported ptypes for advanced Rx descriptor

Kunpeng 930 supports RXD advanced layout. If enabled the layout, the
hardware will report packet type by 8-bit PTYPE filed in the Rx
descriptor, and the supported ptypes are different from original
scheme. So this patch adds supported list for RXD advanced layout.

Fixes: fb5e90694022 ("net/hns3: support Rx descriptor advanced layout")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix PTP capability report
Chengwen Feng [Tue, 13 Apr 2021 11:50:08 +0000 (19:50 +0800)]
net/hns3: fix PTP capability report

The PTP depends on special packet type reported by hardware which
enabled rxd advanced layout, so if the hardware doesn't support rxd
advanced layout, driver should ignore the PTP capability.

Fixes: 438752358158 ("net/hns3: get device capability from firmware")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: add reporting tunnel GRE packet type
Chengwen Feng [Tue, 13 Apr 2021 11:50:07 +0000 (19:50 +0800)]
net/hns3: add reporting tunnel GRE packet type

This patch supports reporting TUNNEL GRE packet type when rxd advanced
layout enabled.

Fixes: fb5e90694022 ("net/hns3: support Rx descriptor advanced layout")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix missing outer L4 UDP flag for VXLAN
Chengwen Feng [Tue, 13 Apr 2021 11:50:06 +0000 (19:50 +0800)]
net/hns3: fix missing outer L4 UDP flag for VXLAN

This patch adds RTE_PTYPE_L4_UDP flag when parsed tunnel vxlan packet.

Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix verification of NEON support
Chengwen Feng [Tue, 13 Apr 2021 11:50:05 +0000 (19:50 +0800)]
net/hns3: fix verification of NEON support

This patch adds verification of whether NEON supported.

Fixes: a3d4f4d291d7 ("net/hns3: support NEON Rx")
Fixes: e31f123db06b ("net/hns3: support NEON Tx")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix use of command status enumeration
Chengchang Tang [Tue, 13 Apr 2021 11:50:04 +0000 (19:50 +0800)]
net/hns3: fix use of command status enumeration

The type of return value of hns3_cmd_send is int, some function declare
the return value as hns3_cmd_status.

This patch fix the incorrect use of the enum hns3_cmd_status.

Fixes: 737f30e1c3ab ("net/hns3: support command interface with firmware")
Fixes: 02a7b55657b2 ("net/hns3: support Rx interrupt")
Cc: stable@dpdk.org
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix timing in mailbox
Chengchang Tang [Tue, 13 Apr 2021 11:50:03 +0000 (19:50 +0800)]
net/hns3: fix timing in mailbox

Currently, when processing MBX messages, the system timestamp is obtained
to determine whether timeout occurs. However, the gettimeofday function
is not monotonically increasing. Therefore, this may lead to incorrect
judgment or difficulty exiting the loop. And actually, in this scenario,
it is not necessary to obtain the timestamp.

This patch deletes the call to the gettimeofday function during MBX
message processing.

Fixes: 463e748964f5 ("net/hns3: support mailbox")
Cc: stable@dpdk.org
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix VF handling LSC event in secondary process
Chengwen Feng [Tue, 13 Apr 2021 11:50:02 +0000 (19:50 +0800)]
net/hns3: fix VF handling LSC event in secondary process

VF will build two queues (csq: command send queue, crq: command receive
queue) with firmware, the crq may contain the following messages:
1) mailbox response message which was the ack of mailbox sync request.
2) PF's link status change message which may send by PF at anytime;

Currently, any threads in the primary and secondary processes could
send mailbox sync request, so it will need to process the crq messages
in there own thread context.

If the crq hold two messages: a) PF's link status change message, b)
mailbox response message when secondary process deals with the crq
messages, it will lead to report lsc event in secondary process
because it uses the policy of processing all pending messages at once.

We use the following scheme to solve it:
1) threads in secondary process could only process specifics messages
   (eg. mailbox response message) in crq, if the message processed, its
   opcode will rewrite with zero, then the intr thread in primary
   process will not process again.
2) threads other than intr thread in the primary process use the same
   processing logic as the threads in secondary process.
3) intr thread in the primary process could process all messages.

Fixes: 76a3836b98c4 ("net/hns3: fix setting default MAC address in bonding of VF")
Fixes: 463e748964f5 ("net/hns3: support mailbox")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: fix possible mismatched response of mailbox
Chengwen Feng [Tue, 13 Apr 2021 11:50:01 +0000 (19:50 +0800)]
net/hns3: fix possible mismatched response of mailbox

Currently, the mailbox synchronous communication between VF and PF use
the following fields to maintain communication:
1. Req_msg_data which was combined by message code and subcode, used to
   match request and response.
2. Head which means the number of requests successfully sent by VF.
3. Tail which means the number of responses successfully received by VF.
4. Lost which means the number of requests which are timeout.

There may possible mismatches of the following situation:
1. VF sends message A with code=1 subcode=1.
Then head=1, tail=0, lost=0.
2. PF was blocked about 500ms when processing the message A.
3. VF will detect message A timeout because it can't get the response
within 500ms.
Then head=1, tail=0, lost=1.
4. VF sends message B with code=1 subcode=1 which equal message A.
Then head=2, tail=0, lost=1.
5. PF processes the first message A and send the response message to VF.
6. VF will update tail field to 1, but the lost field will remain
   unchanged because the code/subcode equal message B's, so driver will
   return success because now the head(2) equals tail(1) plus lost(1).
   This will lead to mismatch of request and response.

To fix the above bug, we use the following scheme:
1. The message sent from VF was labelled with match_id which was a
   unique 16-bit non-zero value.
2. The response sent from PF will label with match_id which got from the
   request.
3. The VF uses the match_id to match request and response message.

This scheme depends on the PF driver, if the PF driver don't support
then VF will uses the original scheme.

Fixes: 463e748964f5 ("net/hns3: support mailbox")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: delete mailbox arq ring
Chengwen Feng [Tue, 13 Apr 2021 11:50:00 +0000 (19:50 +0800)]
net/hns3: delete mailbox arq ring

Currently, driver will copy mailbox messages body into arq ring when
process HNS3_MBX_LINK_STAT_CHANGE and HNS3_MBX_LINK_STAT_CHANGE
message, and then call hns3_mbx_handler API which will direct process
pre-copy messages. In the whole process, the arq ring don't have a
substantial effect.

Note: The arq ring is designed for kernel environment which could not
do much job in interrupt context, but for DPDK it's not required.

Also we rename hns3_handle_link_change_event to
hns3pf_handle_link_change_event which add 'pf' suffix to make it
better to distinguish.

Fixes: 463e748964f5 ("net/hns3: support mailbox")
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/iavf: add offload path for Rx AVX512 flex descriptor
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:09 +0000 (15:34 +0800)]
net/iavf: add offload path for Rx AVX512 flex descriptor

Add a specific path for RX AVX512 (flexible descriptor).
In this path, support the HW offload features, like,
checksum, VLAN stripping, RSS hash.
This path is chosen automatically according to the
configuration.

'inline' is used, then the duplicate code is generated
by the compiler.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: add offload path for Rx AVX512
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:08 +0000 (15:34 +0800)]
net/iavf: add offload path for Rx AVX512

Add a specific path for RX AVX512 (traditional).
In this path, support the HW offload features, like,
checksum, VLAN stripping, RSS hash.
This path is chosen automatically according to the
configuration.

'inline' is used, then the duplicate code is generated
by the compiler.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: add offload path for Tx AVX512
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:07 +0000 (15:34 +0800)]
net/iavf: add offload path for Tx AVX512

Add a specific path for TX AVX512.
In this path, support the HW offload features, like,
checksum insertion, VLAN insertion.
This path is chosen automatically according to the
configuration.

'inline' is used, then the duplicate code is generated
by the compiler.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/iavf: store offload flag of Rx queue
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:06 +0000 (15:34 +0800)]
net/iavf: store offload flag of Rx queue

Add the offload flag for RX queues to know which offload
features are set.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/i40e: fix crash in AVX512
Wenzhuo Lu [Wed, 14 Apr 2021 07:25:26 +0000 (15:25 +0800)]
net/i40e: fix crash in AVX512

Fix segment fault when failing to get the memory from the pool.
If there's no memory in the default cache, fall back to the
previous process.

The previous AVX2 rearm function is changed to add some AVX512
instructions and changed to a callee of the AVX2 and AVX512
rearm functions.

Fixes: e6a6a138919f ("net/i40e: add AVX512 vector path")
Cc: stable@dpdk.org
Reported-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: David Coyle <david.coyle@intel.com>
3 years agonet/ice: fix crash in AVX512
Wenzhuo Lu [Wed, 14 Apr 2021 07:25:25 +0000 (15:25 +0800)]
net/ice: fix crash in AVX512

Fix segment fault when failing to get the memory from the pool.
If there's no memory in the default cache, fall back to the
previous process.

The previous AVX2 rearm function is changed to add some AVX512
instructions and changed to a callee of the AVX2 and AVX512
rearm functions.

Fixes: 7f85d5ebcfe1 ("net/ice: add AVX512 vector path")
Cc: stable@dpdk.org
Reported-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: David Coyle <david.coyle@intel.com>
3 years agonet/iavf: fix crash in AVX512
Wenzhuo Lu [Wed, 14 Apr 2021 07:25:24 +0000 (15:25 +0800)]
net/iavf: fix crash in AVX512

Fix segment fault when failing to get the memory from the pool.
If there's no memory in the default cache, fall back to the
previous process.

The previous AVX2 rearm function is changed to add some AVX512
instructions and changed to a callee of the AVX2 and AVX512
rearm functions.

Fixes: 31737f2b66fb ("net/iavf: enable AVX512 for legacy Rx")
Cc: stable@dpdk.org
Reported-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Tested-by: David Coyle <david.coyle@intel.com>
3 years agoethdev: update flow item GTP QFI definition
Raslan Darawsheh [Tue, 23 Mar 2021 12:11:34 +0000 (14:11 +0200)]
ethdev: update flow item GTP QFI definition

'qfi' field is 8 bits which represent single bit for
PPP (paging Policy Presence) single bit for RQI
(Reflective QoS Indicator) and 6 bits for QFI
(QoS Flow Identifier)
This is based on RFC 38415-g30
https://www.3gpp.org/ftp/Specs/archive/38_series/38.415/38415-g30.zip

Updated the doxygen comment and the mask for 'qfi'
to properly identify the full 8 bits of the field.

note: changing the default mask would cause different
patterns generated by testpmd.

Fixes: 346553db5bd1 ("ethdev: add GTP extension header to flow API")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@nvidia.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
3 years agoapp/testpmd: fix bitmap of link speeds when force speed
Huisong Li [Wed, 14 Apr 2021 03:02:05 +0000 (11:02 +0800)]
app/testpmd: fix bitmap of link speeds when force speed

Currently, when the user sets force link speed through 'link_speeds',
bit(0) of 'link_speeds' is not set to 1(ETH_LINK_SPEED_FIXED),
which conflicts with the definition.

Fixes: 88fbedcd5e5a ("app/testpmd: move speed and duplex parsing in a function")
Cc: stable@dpdk.org
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agoapp/testpmd: add command for single flow dump
Haifei Luo [Wed, 14 Apr 2021 10:20:00 +0000 (13:20 +0300)]
app/testpmd: add command for single flow dump

Add support for single flow dump.
The CLIs to dump one rule: flow dump PORT rule ID
to dump all: flow dump PORT all
Examples:
testpmd> flow dump 0 all
testpmd> flow dump 0 rule 0

Signed-off-by: Haifei Luo <haifeil@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agoethdev: dump single flow rule
Haifei Luo [Wed, 14 Apr 2021 10:19:59 +0000 (13:19 +0300)]
ethdev: dump single flow rule

Previous implementations support dump all the flows. Add new arg
rte_flow in rte_flow_dev_dump to dump one flow.

Signed-off-by: Haifei Luo <haifeil@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Ori Kam <orika@nvidia.com>
3 years agodrivers: add missing includes
Ferruh Yigit [Fri, 26 Mar 2021 16:46:15 +0000 (16:46 +0000)]
drivers: add missing includes

These headers are used but not included explicitly, including them.

"arpa/inet.h" is included for 'htons' and friends.
"netinet/in.h" is included for 'IPPROTO_IP'.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Rasesh Mody <rmody@marvell.com>
3 years agonet/mvpp2: check meter packet mode
Li Zhang [Tue, 13 Apr 2021 15:59:57 +0000 (18:59 +0300)]
net/mvpp2: check meter packet mode

Currently meter algorithms only supports bytes per second(BPS).
Check packet_mode set to TRUE are rejected.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Liron Himi <lironh@marvell.com>
3 years agonet/softnic: check meter packet mode
Li Zhang [Tue, 13 Apr 2021 15:59:56 +0000 (18:59 +0300)]
net/softnic: check meter packet mode

Currently meter algorithms only supports bytes per second(BPS).
Check packet_mode set to TRUE are rejected.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agoapp/testpmd: add meter profile packet mode option
Li Zhang [Tue, 13 Apr 2021 15:59:55 +0000 (18:59 +0300)]
app/testpmd: add meter profile packet mode option

add meter profile packet_mode to the ethernet device.
One example:
add port meter profile rfc2697 (port_id) (profile_id)
(cir) (cbs) (ebs) (packet_mode)

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agoethdev: add packet mode in meter profile structure
Li Zhang [Tue, 13 Apr 2021 15:59:54 +0000 (18:59 +0300)]
ethdev: add packet mode in meter profile structure

Currently meter algorithms only supports rate is bytes per second (BPS).
Add packet_mode flag in meter profile parameters data structure.
So that it can meter traffic by packet per second.

When packet_mode is 0, the profile rates and bucket sizes are
specified in bytes per second and bytes
when packet_mode is not 0, the profile rates and bucket sizes are
specified in packets and packets per second.

The below structure will be extended:
rte_mtr_meter_profile
rte_mtr_capabilities

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agonet/ice: update QinQ switch filter handling
Haiyue Wang [Tue, 13 Apr 2021 05:14:59 +0000 (13:14 +0800)]
net/ice: update QinQ switch filter handling

The hardware outer/inner VLAN protocol types are now updated to map to
new interface VLAN protocol types, so update the application to use new
VLAN protocol types when the rte_flow is QinQ filter type.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice/base: allow GTP-U filter using only inner protocols
Qi Zhang [Tue, 13 Apr 2021 05:06:40 +0000 (13:06 +0800)]
net/ice/base: allow GTP-U filter using only inner protocols

Adds a support for switch filter: GTP-U using just inner fields.
If user doesn't specify outer protocol and its fields but wants to
add switch filter for GTP-U using inner protocols and related fields
such as inner L3 and/or inner L4, this patch enables such filtering.

Signed-off-by: Kiran Patil <kiran.patil@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add packet type for PPPoL2TPv2oUDP
Qi Zhang [Tue, 13 Apr 2021 05:06:39 +0000 (13:06 +0800)]
net/ice/base: add packet type for PPPoL2TPv2oUDP

Add some new macros of PTYPE values to support PPPoL2TPv2oUDP.

Signed-off-by: Ting Xu <ting.xu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: fix QinQ PPPoE dummy packet selection
Qi Zhang [Tue, 13 Apr 2021 05:06:38 +0000 (13:06 +0800)]
net/ice/base: fix QinQ PPPoE dummy packet selection

The dummy packet should be QinQ PPPoE ipv6 when ppp protocol is ipv6.

Fixes: bb3386f348dd ("net/ice: enable QinQ filter for switch")
Cc: stable@dpdk.org
Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add inner VLAN protocol type for QinQ filter
Qi Zhang [Tue, 13 Apr 2021 05:06:37 +0000 (13:06 +0800)]
net/ice/base: add inner VLAN protocol type for QinQ filter

Since VLAN protocol type 'ICE_VLAN_OFOS' has been changed to map
the hardware VLAN protocol ID to 'ICE_VLAN_OF_HW (16)' when in Double
VLAN mode, and to 'ICE_VLAN_OL_HW (17)' when in Single VLAN mode.

So 'ICE_VLAN_OFOS' can't be used with 'ICE_VLAN_EX' which is outer VLAN
hardware protocol ID 'ICE_VLAN_OF_HW (16)' to do the QinQ VLAN pattern.

Introduce the new inner VLAN protocol type 'ICE_VLAN_IN', which is inner
VLAN hardware protocol ID 'ICE_VLAN_OL_HW (17)'.

Now for QinQ VLAN pattern, the protocol 'ICE_VLAN_EX' and 'ICE_VLAN_IN'
should be used to set the related protocol header fields like VLAN ID.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add set/get GPIO helper functions
Qi Zhang [Tue, 13 Apr 2021 05:06:35 +0000 (13:06 +0800)]
net/ice/base: add set/get GPIO helper functions

Add helper functions to set the GPIO pin state or get the value of a
GPIO signal that's the part of the topology based on AQ commands.
This change is needed to setup GPIO pins state for PTP, SyncE etc.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: enable I2C read/write commands
Qi Zhang [Tue, 13 Apr 2021 05:06:33 +0000 (13:06 +0800)]
net/ice/base: enable I2C read/write commands

Enable I2C read/write AQ commands. They are now required for
controlling the external physical connectors via external I2C
port expander on E810-T adapters.

Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: add priority check of matching recipe
Qi Zhang [Tue, 13 Apr 2021 05:06:36 +0000 (13:06 +0800)]
net/ice/base: add priority check of matching recipe

Check priority when look for a recipe which matches our request
to enable flow priority for switch filter.

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: change protocol ID for VLAN in DVM
Qi Zhang [Tue, 13 Apr 2021 05:06:32 +0000 (13:06 +0800)]
net/ice/base: change protocol ID for VLAN in DVM

Protocol id for first vlan in Double VLAN Mode (DVM) should be
ICE_VLAN_OF_HW = 16, but for Single VLAN Mode (SVM) this should be
ICE_VLAN_OL_HW = 17.

Change protocol id in type to id translation array for outer vlan
to 17 when DVM is enabled, which means the driver, package,
and firmware support DVM.

Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: support PPPoL2TPv2oUDP RSS hash
Qi Zhang [Tue, 13 Apr 2021 05:06:34 +0000 (13:06 +0800)]
net/ice/base: support PPPoL2TPv2oUDP RSS hash

Add support for PPPoL2TPv2oUDP RSS hash. L2TPv2 and PPP ptypes
and flow headers are added. Protocol id for PPP is added.

Signed-off-by: Ting Xu <ting.xu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: set MAC type for E823C device
Qi Zhang [Tue, 13 Apr 2021 05:06:31 +0000 (13:06 +0800)]
net/ice/base: set MAC type for E823C device

Set E823C device's MAC type as generic.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: remove unused ptype field in PTT definition
Qi Zhang [Tue, 13 Apr 2021 05:06:30 +0000 (13:06 +0800)]
net/ice/base: remove unused ptype field in PTT definition

Remove the unused ptype entry, and use the gcc extension for
ranged initializers in arrays for Linux, and explicitly target
each table entry by index when initializing under Linux.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: print link configure error
Qi Zhang [Tue, 13 Apr 2021 05:06:29 +0000 (13:06 +0800)]
net/ice/base: print link configure error

Newer NVMs return link_cfg_err for get_link_status AQ. Print it
for debug use.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: support removing VSI from flow profile
Qi Zhang [Tue, 13 Apr 2021 05:06:28 +0000 (13:06 +0800)]
net/ice/base: support removing VSI from flow profile

Adding a function ice_flow_rem_vsi_prof() to remove flow entries
associated to the SW VSI handle. Once complete, clear the vsi index from
the flow profile bitmap. This will ensure that a VSI once removed
can be re-added and the package block rules will be added again.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice/base: cleanup code
Qi Zhang [Tue, 13 Apr 2021 05:06:27 +0000 (13:06 +0800)]
net/ice/base: cleanup code

1. There are a lots of function header mismatch its function name.
2. remove unnecessary header file include.
3. remove unnecessary macro.
4. remove unnecessary comment.

Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
3 years agonet/ice: use write combining store for tail on AVX512
Radu Nicolau [Fri, 9 Apr 2021 10:09:03 +0000 (10:09 +0000)]
net/ice: use write combining store for tail on AVX512

Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ixgbe: fix Rx errors statistics for UDP checksum
Haiyue Wang [Thu, 8 Apr 2021 06:30:00 +0000 (14:30 +0800)]
net/ixgbe: fix Rx errors statistics for UDP checksum

Restrict the "remove l3_l4_xsum_errors from rx_errors" to 82599 only for
hardware errata.

Fixes: 256ff05a9cae ("ixgbe: fix Rx errors statistics for UDP checksum")
Cc: stable@dpdk.org
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/mlx5: fix resource release for mirror flow
Jiawei Wang [Fri, 9 Apr 2021 12:33:28 +0000 (15:33 +0300)]
net/mlx5: fix resource release for mirror flow

The mlx5 PMD allocated the resources of the sample actions, and then
moved these ones to the destination actions array. The original indices
were not cleared and the resources were referenced twice in the
flow object - as the fate actions and in the destination actions array.

This causes the failure on flow destroy because PMD tried to release the
same objects twice.

The patch clears the original indices, add the missed checking for zero
and eliminates multiple object releasing.

Fixes: 00c10c22118a ("net/mlx5: update translate function for mirroring")
Cc: stable@dpdk.org
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Reviewed-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx4: fix RSS action with null hash key
Viacheslav Ovsiienko [Wed, 7 Apr 2021 15:30:15 +0000 (15:30 +0000)]
net/mlx4: fix RSS action with null hash key

If RSS action contains non zero hash key length and NULL
key buffer pointer the default hash key should be used.
The check for the NULL pointer this was missing in the mlx4
PMD causing crash, for example, in testpmd with command:

flow validate 0 ingress group 0
  pattern eth / ipv4 / end
  actions rss queues 0 end key_len 40 / end

Fixes: ac8d22de2394 ("ethdev: flatten RSS configuration in flow API")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agodoc: update push/pop VLAN support in mlx5 guide
Dong Zhou [Thu, 1 Apr 2021 13:22:47 +0000 (16:22 +0300)]
doc: update push/pop VLAN support in mlx5 guide

Updates the documentation for push/pop VLAN support. In E-Switch
mode, push VLAN on ingress traffic and pop VLAN in egress traffic
are both support.

Signed-off-by: Dong Zhou <dongzhou@nvidia.com>
Reviewed-by: Asaf Penso <asafp@nvidia.com>
3 years agonet/mlx5: fix redundant flow after RSS expansion
Xiaoyu Min [Tue, 30 Mar 2021 13:40:32 +0000 (21:40 +0800)]
net/mlx5: fix redundant flow after RSS expansion

When RSS expand, if there is no expansion happened but completion
happened because user only input next protocol field instead of item
i.e, ether type == 0x8100 instead of VLAN, an extra flow is created with
missing item in order to filter traffic strictly.

However, after [1] and [2] the rte_flow_item_eth itself is enough to
filter out VLAN traffic, the VLAN item is not needed.

[1]: commit 09315fc83861 ("ethdev: add VLAN attributes to ethernet and VLAN items")
[2]: commit 86b59a1af671 ("net/mlx5: support VLAN matching fields")

This redundant flow will cause failure in some scenarios on group 0 due
to they are the same FTE.

Fixes: fc2dd8dd492f ("ethdev: fix expand RSS flows")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: support 64-bit for modify field action
Alexander Kozyrev [Wed, 7 Apr 2021 15:18:29 +0000 (15:18 +0000)]
net/mlx5: support 64-bit for modify field action

Extend the range of immediate value used in the MODIFY_FIELD action
from 32 to 64 bits to conform to the rte_flow_action_modify_data spec.
Apply appropriate big endian conversion to the immediate value
according to a destination field bit width.

Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: fix modify field action endianness
Alexander Kozyrev [Fri, 2 Apr 2021 02:07:41 +0000 (02:07 +0000)]
net/mlx5: fix modify field action endianness

Converting modify_field action masks to the big endian format is wrong
for small (less than 4 bytes) fields. Use the BE conversions appropriate
for a field size, not rte_cpu_to_be_32 for everything.

Fixes: 144127ba5660 ("net/mlx5: adjust modify field action endianness")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: fix modify field action order for IPv6
Alexander Kozyrev [Wed, 7 Apr 2021 01:14:33 +0000 (01:14 +0000)]
net/mlx5: fix modify field action order for IPv6

Mellanox hardware can only modify any packet field in 32-bit chunks,
which means 4 such chunks are needed to modify an IPv6 address.
The modification order of these chunks starts from the most significant
bits for the IPv6 address. That leads to confusing results when trying
to modify either source or destination address via the MODIFY_FIELD
action. Fix the order of 32-bit chunks for IPv6 addresses modification
by starting from the least significant bits.

Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: fix link speed calculation on Windows
Tal Shnaiderman [Tue, 6 Apr 2021 07:31:59 +0000 (10:31 +0300)]
net/mlx5: fix link speed calculation on Windows

In Windows DevX returns the rate of the current link speed
in bit/s, this rate was converted to Mibit/s instead of the Mbit/s
rate expected by DPDK resulting in wrong link speed reporting.

Fixes: 6fbd73709ee4 ("net/mlx5: support link update on Windows")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: check extended metadata for meta modification
Alexander Kozyrev [Wed, 7 Apr 2021 01:13:57 +0000 (01:13 +0000)]
net/mlx5: check extended metadata for meta modification

The MODIFY_FIELD action requires the extended metadata support
in order to manipulate on METADATA register as well as on MARK register.
Check if it is supported and reject the MODIFY_FIELD action if it is not
just like it was done before for the MARK register modifications.

Fixes: 0588d64ffde3 ("net/mlx5: check extended metadata for mark modification")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>