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net/mlx5: support scheduling on send routine template
2020-07-21 Viacheslav Ovsiienkonet/mlx5: support scheduling on send routine template
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: prepare Tx to support scheduling
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: convert timestamp to completion index
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: prepare Tx queue structures to support timestamp
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: introduce clock queue service routine
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: allocate packet pacing context
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: create Tx queues with DevX
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: create rearm queue for packet pacing
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: create clock queue for packet pacing
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: introduce shared UAR resource
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: fix UAR lock sharing for multiport devices
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkonet/mlx5: introduce send scheduling devargs
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-21 Viacheslav Ovsiienkocommon/mlx5: prepare support of packet pacing
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-17 Viacheslav Ovsiienkoapp/testpmd: fix typos
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-11 Viacheslav Ovsiienkoapp/testpmd: add Tx scheduling command
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-11 Viacheslav Ovsiienkombuf: introduce accurate packet Tx scheduling
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-07-11 Viacheslav Ovsiienkocommon/mlx5: fix physical port name pattern recognition
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-06-30 Viacheslav Ovsiienkonet/mlx5: fix host physical function representor naming
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-05-18 Viacheslav Ovsiienkocommon/mlx5: fix netlink buffer allocation from stack
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-05-18 Viacheslav Ovsiienkocommon/mlx5: fix MAC addresses assert
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-04-21 Viacheslav Ovsiienkonet/mlx5: fix metadata for compressed Rx CQEs
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-25 Viacheslav Ovsiienkodoc: add Tx inline hint in mlx5 guide
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-25 Viacheslav Ovsiienkodoc: add external pinned memory mbuf to release notes
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-25 Viacheslav Ovsiienkodoc: add metadata limitation in mlx5 guide
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-21 Viacheslav Ovsiienkodoc: clarify memory write combining in mlx5 guide
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-21 Viacheslav Ovsiienkonet/mlx5: fix inline packet size for ConnectX-4 Lx
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-21 Viacheslav Ovsiienkonet/mlx5: fix last completed built descriptor
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-14 Viacheslav Ovsiienkoapp/testpmd: fix txonly flow generation entropy
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-14 Viacheslav Ovsiienkonet/mlx5: fix legacy multi-packet write session
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-06 Viacheslav Ovsiienkotest/mbuf: check pinned external buffer
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-06 Viacheslav Ovsiienkombuf: fix pinned memory function style
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-02-05 Viacheslav Ovsiienkonet/mlx5: add no-inline Tx flag
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: engage free on completion queue
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: add free on completion queue
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: update Tx error handling routine
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: move Tx complete request routine
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkonet/mlx5: allow allocated mbuf with external buffer
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkoapp/testpmd: add mempool with external data buffers
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkombuf: create pool with external memory buffers
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkombuf: detach mbuf with pinned external buffer
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-20 Viacheslav Ovsiienkombuf: introduce routine to get private mbuf pool flags
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix metadata item endianness conversion
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix matcher field usage for metadata entities
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix shared metadata matcher field setup
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkoethdev: fix switching domain allocation
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix doorbell register offset type
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2020-01-17 Viacheslav Ovsiienkonet/mlx5: fix Tx burst routines set
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-27 Viacheslav Ovsiienkonet/mlx5: fix legacy inline multi-packet performance
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-27 Viacheslav Ovsiienkonet/mlx5: fix legacy non-inline multi-packet performance
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-27 Viacheslav Ovsiienkonet/mlx5: fix default mark copy flow
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-26 Viacheslav Ovsiienkonet/mlx5: fix legacy multi-packet Tx descriptors
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-26 Viacheslav Ovsiienkodoc: update metadata feature in mlx5 guide
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-26 Viacheslav Ovsiienkonet/mlx5: fix getting metadata register for E-Switch...
...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix assert in Tx inline settings
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix port action for LAG
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix Tx doorbell write memory barrier
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix vport index in port action
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix vport id in port id action
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix environment variable recovery
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix suffix flow creation in metadata split
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-20 Viacheslav Ovsiienkonet/mlx5: fix query host adapter attributes
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: control transmit doorbell register mapping
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: fix asserts for multi-segment Tx offload...
...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add metadata register copy table
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: split Rx flows to provide metadata copy
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: introduce flow splitters chain
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add metadata support to Rx datapath
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: extend flow metadata support
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: extend flow mark support
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: support flow tag
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update metadata register ID query
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: check maximum modify actions number
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: adjust shared register according to mask
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add devarg for extensive metadata support
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: check metadata registers availability
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: rename structure and function
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update meta register matcher set
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update flow functions
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: refactor flow structure
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: add metadata register copy
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: update modify header action translator
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-11 Viacheslav Ovsiienkonet/mlx5: convert internal tag endianness
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-08 Viacheslav Ovsiienkoethdev: move egress metadata to dynamic field
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-08 Viacheslav Ovsiienkoethdev: extend flow metadata
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-11-08 Viacheslav Ovsiienkoethdev: add flow tag
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-23 Viacheslav Ovsiienkonet/mlx5: fix Tx packets statistics
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: fix direct call to rdma-core library
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: fix device scan within switch domain
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: adjust inline setting for large Tx queue...
...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: check sibling device configurations mismatch
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: update switch port id in bonding configuration
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: extend switch domain searching range
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: update source and destination vport translations
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-08 Viacheslav Ovsiienkonet/mlx5: elaborate E-Switch port parameters query
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: query vport index match mode and parameters
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: check kernel support for VF LAG bonding
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: generate bonding device name
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: add VF LAG mode bonding device recognition
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: allocate device list explicitly
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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2019-10-07 Viacheslav Ovsiienkonet/mlx5: update PCI address retrieving routine
 ...off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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