4 * Copyright (C) Cavium, Inc 2017.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium, Inc nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include "test_order_common.h"
38 /* See http://dpdk.org/doc/guides/tools/testeventdev.html for test details */
40 static inline __attribute__((always_inline)) void
41 order_queue_process_stage_0(struct rte_event *const ev)
43 ev->queue_id = 1; /* q1 atomic queue */
44 ev->op = RTE_EVENT_OP_FORWARD;
45 ev->sched_type = RTE_SCHED_TYPE_ATOMIC;
46 ev->event_type = RTE_EVENT_TYPE_CPU;
50 order_queue_worker(void *arg)
55 while (t->err == false) {
56 uint16_t event = rte_event_dequeue_burst(dev_id, port,
59 if (rte_atomic64_read(outstand_pkts) <= 0)
65 if (ev.queue_id == 0) { /* from ordered queue */
66 order_queue_process_stage_0(&ev);
67 while (rte_event_enqueue_burst(dev_id, port, &ev, 1)
70 } else if (ev.queue_id == 1) { /* from atomic queue */
71 order_process_stage_1(t, &ev, nb_flows,
72 expected_flow_seq, outstand_pkts);
74 order_process_stage_invalid(t, &ev);
81 order_queue_worker_burst(void *arg)
84 struct rte_event ev[BURST_SIZE];
87 while (t->err == false) {
88 uint16_t const nb_rx = rte_event_dequeue_burst(dev_id, port, ev,
92 if (rte_atomic64_read(outstand_pkts) <= 0)
98 for (i = 0; i < nb_rx; i++) {
99 if (ev[i].queue_id == 0) { /* from ordered queue */
100 order_queue_process_stage_0(&ev[i]);
101 } else if (ev[i].queue_id == 1) {/* from atomic queue */
102 order_process_stage_1(t, &ev[i], nb_flows,
103 expected_flow_seq, outstand_pkts);
104 ev[i].op = RTE_EVENT_OP_RELEASE;
106 order_process_stage_invalid(t, &ev[i]);
112 enq = rte_event_enqueue_burst(dev_id, port, ev, nb_rx);
113 while (enq < nb_rx) {
114 enq += rte_event_enqueue_burst(dev_id, port,
115 ev + enq, nb_rx - enq);
122 worker_wrapper(void *arg)
124 struct worker_data *w = arg;
125 const bool burst = evt_has_burst_mode(w->dev_id);
128 return order_queue_worker_burst(arg);
130 return order_queue_worker(arg);
134 order_queue_launch_lcores(struct evt_test *test, struct evt_options *opt)
136 return order_launch_lcores(test, opt, worker_wrapper);
141 order_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)
145 const uint8_t nb_workers = evt_nr_active_lcores(opt->wlcores);
146 /* number of active worker cores + 1 producer */
147 const uint8_t nb_ports = nb_workers + 1;
149 const struct rte_event_dev_config config = {
150 .nb_event_queues = NB_QUEUES,/* q0 ordered, q1 atomic */
151 .nb_event_ports = nb_ports,
152 .nb_events_limit = 4096,
153 .nb_event_queue_flows = opt->nb_flows,
154 .nb_event_port_dequeue_depth = 128,
155 .nb_event_port_enqueue_depth = 128,
158 ret = rte_event_dev_configure(opt->dev_id, &config);
160 evt_err("failed to configure eventdev %d", opt->dev_id);
164 /* q0 (ordered queue) configuration */
165 struct rte_event_queue_conf q0_ordered_conf = {
166 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
167 .schedule_type = RTE_SCHED_TYPE_ORDERED,
168 .nb_atomic_flows = opt->nb_flows,
169 .nb_atomic_order_sequences = opt->nb_flows,
171 ret = rte_event_queue_setup(opt->dev_id, 0, &q0_ordered_conf);
173 evt_err("failed to setup queue0 eventdev %d", opt->dev_id);
177 /* q1 (atomic queue) configuration */
178 struct rte_event_queue_conf q1_atomic_conf = {
179 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
180 .schedule_type = RTE_SCHED_TYPE_ATOMIC,
181 .nb_atomic_flows = opt->nb_flows,
182 .nb_atomic_order_sequences = opt->nb_flows,
184 ret = rte_event_queue_setup(opt->dev_id, 1, &q1_atomic_conf);
186 evt_err("failed to setup queue1 eventdev %d", opt->dev_id);
190 /* setup one port per worker, linking to all queues */
191 ret = order_event_dev_port_setup(test, opt, nb_workers, NB_QUEUES);
195 ret = rte_event_dev_start(opt->dev_id);
197 evt_err("failed to start eventdev %d", opt->dev_id);
205 order_queue_opt_dump(struct evt_options *opt)
208 evt_dump("nb_evdev_queues", "%d", NB_QUEUES);
212 order_queue_capability_check(struct evt_options *opt)
214 struct rte_event_dev_info dev_info;
216 rte_event_dev_info_get(opt->dev_id, &dev_info);
217 if (dev_info.max_event_queues < NB_QUEUES || dev_info.max_event_ports <
218 order_nb_event_ports(opt)) {
219 evt_err("not enough eventdev queues=%d/%d or ports=%d/%d",
220 NB_QUEUES, dev_info.max_event_queues,
221 order_nb_event_ports(opt), dev_info.max_event_ports);
228 static const struct evt_test_ops order_queue = {
229 .cap_check = order_queue_capability_check,
230 .opt_check = order_opt_check,
231 .opt_dump = order_queue_opt_dump,
232 .test_setup = order_test_setup,
233 .mempool_setup = order_mempool_setup,
234 .eventdev_setup = order_queue_eventdev_setup,
235 .launch_lcores = order_queue_launch_lcores,
236 .eventdev_destroy = order_eventdev_destroy,
237 .mempool_destroy = order_mempool_destroy,
238 .test_result = order_test_result,
239 .test_destroy = order_test_destroy,
242 EVT_TEST_REGISTER(order_queue);