2 * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2017 Cavium, Inc.
6 #include "test_pipeline_common.h"
8 /* See http://doc.dpdk.org/guides/tools/testeventdev.html for test details */
10 static __rte_always_inline int
11 pipeline_queue_nb_event_queues(struct evt_options *opt)
13 uint16_t eth_count = rte_eth_dev_count_avail();
15 return (eth_count * opt->nb_stages) + eth_count;
18 typedef int (*pipeline_queue_worker_t)(void *arg);
20 static __rte_noinline int
21 pipeline_queue_worker_single_stage_tx(void *arg)
23 PIPELINE_WORKER_SINGLE_STAGE_INIT;
25 while (t->done == false) {
26 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
33 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
34 pipeline_event_tx(dev, port, &ev);
38 pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
39 pipeline_event_enqueue(dev, port, &ev);
46 static __rte_noinline int
47 pipeline_queue_worker_single_stage_fwd(void *arg)
49 PIPELINE_WORKER_SINGLE_STAGE_INIT;
50 const uint8_t *tx_queue = t->tx_evqueue_id;
52 while (t->done == false) {
53 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
60 ev.queue_id = tx_queue[ev.mbuf->port];
61 rte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);
62 pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
63 pipeline_event_enqueue(dev, port, &ev);
70 static __rte_noinline int
71 pipeline_queue_worker_single_stage_burst_tx(void *arg)
73 PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;
75 while (t->done == false) {
76 uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,
84 for (i = 0; i < nb_rx; i++) {
85 rte_prefetch0(ev[i + 1].mbuf);
86 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
87 pipeline_event_tx(dev, port, &ev[i]);
91 pipeline_fwd_event(&ev[i],
92 RTE_SCHED_TYPE_ATOMIC);
93 pipeline_event_enqueue_burst(dev, port, ev,
102 static __rte_noinline int
103 pipeline_queue_worker_single_stage_burst_fwd(void *arg)
105 PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;
106 const uint8_t *tx_queue = t->tx_evqueue_id;
108 while (t->done == false) {
109 uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,
117 for (i = 0; i < nb_rx; i++) {
118 rte_prefetch0(ev[i + 1].mbuf);
119 ev[i].queue_id = tx_queue[ev[i].mbuf->port];
120 rte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);
121 pipeline_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);
124 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
125 w->processed_pkts += nb_rx;
131 static __rte_noinline int
132 pipeline_queue_worker_single_stage_tx_vector(void *arg)
134 PIPELINE_WORKER_SINGLE_STAGE_INIT;
138 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
145 if (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
146 vector_sz = ev.vec->nb_elem;
147 pipeline_event_tx_vector(dev, port, &ev);
148 w->processed_pkts += vector_sz;
151 pipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);
152 pipeline_event_enqueue(dev, port, &ev);
159 static __rte_noinline int
160 pipeline_queue_worker_single_stage_fwd_vector(void *arg)
162 PIPELINE_WORKER_SINGLE_STAGE_INIT;
163 const uint8_t *tx_queue = t->tx_evqueue_id;
167 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
174 ev.queue_id = tx_queue[ev.vec->port];
176 vector_sz = ev.vec->nb_elem;
177 pipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);
178 pipeline_event_enqueue(dev, port, &ev);
179 w->processed_pkts += vector_sz;
185 static __rte_noinline int
186 pipeline_queue_worker_single_stage_burst_tx_vector(void *arg)
188 PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;
193 rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);
200 for (i = 0; i < nb_rx; i++) {
201 if (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {
202 vector_sz = ev[i].vec->nb_elem;
203 pipeline_event_tx_vector(dev, port, &ev[i]);
204 ev[i].op = RTE_EVENT_OP_RELEASE;
205 w->processed_pkts += vector_sz;
208 pipeline_fwd_event_vector(
209 &ev[i], RTE_SCHED_TYPE_ATOMIC);
213 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
219 static __rte_noinline int
220 pipeline_queue_worker_single_stage_burst_fwd_vector(void *arg)
222 PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;
223 const uint8_t *tx_queue = t->tx_evqueue_id;
228 rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);
236 for (i = 0; i < nb_rx; i++) {
237 ev[i].queue_id = tx_queue[ev[i].vec->port];
238 ev[i].vec->queue = 0;
239 vector_sz += ev[i].vec->nb_elem;
240 pipeline_fwd_event_vector(&ev[i],
241 RTE_SCHED_TYPE_ATOMIC);
244 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
245 w->processed_pkts += vector_sz;
251 static __rte_noinline int
252 pipeline_queue_worker_multi_stage_tx(void *arg)
254 PIPELINE_WORKER_MULTI_STAGE_INIT;
255 const uint8_t *tx_queue = t->tx_evqueue_id;
257 while (t->done == false) {
258 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
265 cq_id = ev.queue_id % nb_stages;
267 if (ev.queue_id == tx_queue[ev.mbuf->port]) {
268 pipeline_event_tx(dev, port, &ev);
274 pipeline_fwd_event(&ev, cq_id != last_queue ?
275 sched_type_list[cq_id] :
276 RTE_SCHED_TYPE_ATOMIC);
277 pipeline_event_enqueue(dev, port, &ev);
283 static __rte_noinline int
284 pipeline_queue_worker_multi_stage_fwd(void *arg)
286 PIPELINE_WORKER_MULTI_STAGE_INIT;
287 const uint8_t *tx_queue = t->tx_evqueue_id;
289 while (t->done == false) {
290 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
297 cq_id = ev.queue_id % nb_stages;
299 if (cq_id == last_queue) {
300 ev.queue_id = tx_queue[ev.mbuf->port];
301 rte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);
302 pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);
303 pipeline_event_enqueue(dev, port, &ev);
307 pipeline_fwd_event(&ev, sched_type_list[cq_id]);
308 pipeline_event_enqueue(dev, port, &ev);
315 static __rte_noinline int
316 pipeline_queue_worker_multi_stage_burst_tx(void *arg)
318 PIPELINE_WORKER_MULTI_STAGE_BURST_INIT;
319 const uint8_t *tx_queue = t->tx_evqueue_id;
321 while (t->done == false) {
322 uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,
330 for (i = 0; i < nb_rx; i++) {
331 rte_prefetch0(ev[i + 1].mbuf);
332 cq_id = ev[i].queue_id % nb_stages;
334 if (ev[i].queue_id == tx_queue[ev[i].mbuf->port]) {
335 pipeline_event_tx(dev, port, &ev[i]);
341 pipeline_fwd_event(&ev[i], cq_id != last_queue ?
342 sched_type_list[cq_id] :
343 RTE_SCHED_TYPE_ATOMIC);
344 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
351 static __rte_noinline int
352 pipeline_queue_worker_multi_stage_burst_fwd(void *arg)
354 PIPELINE_WORKER_MULTI_STAGE_BURST_INIT;
355 const uint8_t *tx_queue = t->tx_evqueue_id;
357 while (t->done == false) {
358 uint16_t processed_pkts = 0;
359 uint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,
367 for (i = 0; i < nb_rx; i++) {
368 rte_prefetch0(ev[i + 1].mbuf);
369 cq_id = ev[i].queue_id % nb_stages;
371 if (cq_id == last_queue) {
372 ev[i].queue_id = tx_queue[ev[i].mbuf->port];
373 rte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);
374 pipeline_fwd_event(&ev[i],
375 RTE_SCHED_TYPE_ATOMIC);
379 pipeline_fwd_event(&ev[i],
380 sched_type_list[cq_id]);
384 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
385 w->processed_pkts += processed_pkts;
391 static __rte_noinline int
392 pipeline_queue_worker_multi_stage_tx_vector(void *arg)
394 PIPELINE_WORKER_MULTI_STAGE_INIT;
395 const uint8_t *tx_queue = t->tx_evqueue_id;
399 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
406 cq_id = ev.queue_id % nb_stages;
408 if (ev.queue_id == tx_queue[ev.vec->port]) {
409 vector_sz = ev.vec->nb_elem;
410 pipeline_event_tx_vector(dev, port, &ev);
411 w->processed_pkts += vector_sz;
416 pipeline_fwd_event_vector(&ev, cq_id != last_queue
417 ? sched_type_list[cq_id]
418 : RTE_SCHED_TYPE_ATOMIC);
419 pipeline_event_enqueue(dev, port, &ev);
425 static __rte_noinline int
426 pipeline_queue_worker_multi_stage_fwd_vector(void *arg)
428 PIPELINE_WORKER_MULTI_STAGE_INIT;
429 const uint8_t *tx_queue = t->tx_evqueue_id;
433 uint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);
440 cq_id = ev.queue_id % nb_stages;
442 if (cq_id == last_queue) {
443 vector_sz = ev.vec->nb_elem;
444 ev.queue_id = tx_queue[ev.vec->port];
445 pipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);
446 w->processed_pkts += vector_sz;
449 pipeline_fwd_event_vector(&ev, sched_type_list[cq_id]);
452 pipeline_event_enqueue(dev, port, &ev);
458 static __rte_noinline int
459 pipeline_queue_worker_multi_stage_burst_tx_vector(void *arg)
461 PIPELINE_WORKER_MULTI_STAGE_BURST_INIT;
462 const uint8_t *tx_queue = t->tx_evqueue_id;
467 rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);
474 for (i = 0; i < nb_rx; i++) {
475 cq_id = ev[i].queue_id % nb_stages;
477 if (ev[i].queue_id == tx_queue[ev[i].vec->port]) {
478 vector_sz = ev[i].vec->nb_elem;
479 pipeline_event_tx_vector(dev, port, &ev[i]);
480 ev[i].op = RTE_EVENT_OP_RELEASE;
481 w->processed_pkts += vector_sz;
486 pipeline_fwd_event_vector(
487 &ev[i], cq_id != last_queue
488 ? sched_type_list[cq_id]
489 : RTE_SCHED_TYPE_ATOMIC);
492 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
498 static __rte_noinline int
499 pipeline_queue_worker_multi_stage_burst_fwd_vector(void *arg)
501 PIPELINE_WORKER_MULTI_STAGE_BURST_INIT;
502 const uint8_t *tx_queue = t->tx_evqueue_id;
507 rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);
514 for (i = 0; i < nb_rx; i++) {
515 cq_id = ev[i].queue_id % nb_stages;
517 if (cq_id == last_queue) {
518 ev[i].queue_id = tx_queue[ev[i].vec->port];
519 vector_sz = ev[i].vec->nb_elem;
520 pipeline_fwd_event_vector(
521 &ev[i], RTE_SCHED_TYPE_ATOMIC);
522 w->processed_pkts += vector_sz;
525 pipeline_fwd_event_vector(
526 &ev[i], sched_type_list[cq_id]);
530 pipeline_event_enqueue_burst(dev, port, ev, nb_rx);
537 worker_wrapper(void *arg)
539 struct worker_data *w = arg;
540 struct evt_options *opt = w->t->opt;
541 const bool burst = evt_has_burst_mode(w->dev_id);
542 const bool internal_port = w->t->internal_port;
543 const uint8_t nb_stages = opt->nb_stages;
544 /*vector/burst/internal_port*/
545 const pipeline_queue_worker_t
546 pipeline_queue_worker_single_stage[2][2][2] = {
547 [0][0][0] = pipeline_queue_worker_single_stage_fwd,
548 [0][0][1] = pipeline_queue_worker_single_stage_tx,
549 [0][1][0] = pipeline_queue_worker_single_stage_burst_fwd,
550 [0][1][1] = pipeline_queue_worker_single_stage_burst_tx,
551 [1][0][0] = pipeline_queue_worker_single_stage_fwd_vector,
552 [1][0][1] = pipeline_queue_worker_single_stage_tx_vector,
553 [1][1][0] = pipeline_queue_worker_single_stage_burst_fwd_vector,
554 [1][1][1] = pipeline_queue_worker_single_stage_burst_tx_vector,
556 const pipeline_queue_worker_t
557 pipeline_queue_worker_multi_stage[2][2][2] = {
558 [0][0][0] = pipeline_queue_worker_multi_stage_fwd,
559 [0][0][1] = pipeline_queue_worker_multi_stage_tx,
560 [0][1][0] = pipeline_queue_worker_multi_stage_burst_fwd,
561 [0][1][1] = pipeline_queue_worker_multi_stage_burst_tx,
562 [1][0][0] = pipeline_queue_worker_multi_stage_fwd_vector,
563 [1][0][1] = pipeline_queue_worker_multi_stage_tx_vector,
564 [1][1][0] = pipeline_queue_worker_multi_stage_burst_fwd_vector,
565 [1][1][1] = pipeline_queue_worker_multi_stage_burst_tx_vector,
569 return (pipeline_queue_worker_single_stage[opt->ena_vector]
571 [internal_port])(arg);
573 return (pipeline_queue_worker_multi_stage[opt->ena_vector]
575 [internal_port])(arg);
577 rte_panic("invalid worker\n");
581 pipeline_queue_launch_lcores(struct evt_test *test, struct evt_options *opt)
583 return pipeline_launch_lcores(test, opt, worker_wrapper);
587 pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)
592 int nb_stages = opt->nb_stages;
594 uint8_t tx_evport_id = 0;
595 uint8_t tx_evqueue_id[RTE_MAX_ETHPORTS];
596 uint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV];
597 uint8_t nb_worker_queues = 0;
599 struct rte_event_dev_info info;
600 struct test_pipeline *t = evt_test_priv(test);
602 nb_ports = evt_nr_active_lcores(opt->wlcores);
603 nb_queues = rte_eth_dev_count_avail() * (nb_stages);
605 /* One queue for Tx adapter per port */
606 nb_queues += rte_eth_dev_count_avail();
608 memset(tx_evqueue_id, 0, sizeof(uint8_t) * RTE_MAX_ETHPORTS);
609 memset(queue_arr, 0, sizeof(uint8_t) * RTE_EVENT_MAX_QUEUES_PER_DEV);
611 rte_event_dev_info_get(opt->dev_id, &info);
612 ret = evt_configure_eventdev(opt, nb_queues, nb_ports);
614 evt_err("failed to configure eventdev %d", opt->dev_id);
618 struct rte_event_queue_conf q_conf = {
619 .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
620 .nb_atomic_flows = opt->nb_flows,
621 .nb_atomic_order_sequences = opt->nb_flows,
623 /* queue configurations */
624 for (queue = 0; queue < nb_queues; queue++) {
627 q_conf.event_queue_cfg = 0;
628 slot = queue % (nb_stages + 1);
629 if (slot == nb_stages) {
630 q_conf.schedule_type = RTE_SCHED_TYPE_ATOMIC;
631 if (!t->internal_port) {
632 q_conf.event_queue_cfg =
633 RTE_EVENT_QUEUE_CFG_SINGLE_LINK;
635 tx_evqueue_id[prod++] = queue;
637 q_conf.schedule_type = opt->sched_type_list[slot];
638 queue_arr[nb_worker_queues] = queue;
642 ret = rte_event_queue_setup(opt->dev_id, queue, &q_conf);
644 evt_err("failed to setup queue=%d", queue);
649 if (opt->wkr_deq_dep > info.max_event_port_dequeue_depth)
650 opt->wkr_deq_dep = info.max_event_port_dequeue_depth;
652 /* port configuration */
653 const struct rte_event_port_conf p_conf = {
654 .dequeue_depth = opt->wkr_deq_dep,
655 .enqueue_depth = info.max_event_port_dequeue_depth,
656 .new_event_threshold = info.max_num_events,
659 if (!t->internal_port) {
660 ret = pipeline_event_port_setup(test, opt, queue_arr,
661 nb_worker_queues, p_conf);
665 ret = pipeline_event_port_setup(test, opt, NULL, nb_queues,
671 * The pipelines are setup in the following manner:
673 * eth_dev_count = 2, nb_stages = 2.
678 * event queue pipelines:
679 * eth0 -> q0 -> q1 -> (q2->tx)
680 * eth1 -> q3 -> q4 -> (q5->tx)
682 * q2, q5 configured as ATOMIC | SINGLE_LINK
685 ret = pipeline_event_rx_adapter_setup(opt, nb_stages + 1, p_conf);
689 ret = pipeline_event_tx_adapter_setup(opt, p_conf);
693 if (!evt_has_distributed_sched(opt->dev_id)) {
695 rte_event_dev_service_id_get(opt->dev_id, &service_id);
696 ret = evt_service_setup(service_id);
698 evt_err("No service lcore found to run event dev.");
703 /* Connect the tx_evqueue_id to the Tx adapter port */
704 if (!t->internal_port) {
705 RTE_ETH_FOREACH_DEV(prod) {
706 ret = rte_event_eth_tx_adapter_event_port_get(prod,
709 evt_err("Unable to get Tx adptr[%d] evprt[%d]",
714 if (rte_event_port_link(opt->dev_id, tx_evport_id,
715 &tx_evqueue_id[prod],
717 evt_err("Unable to link Tx adptr[%d] evprt[%d]",
724 ret = rte_event_dev_start(opt->dev_id);
726 evt_err("failed to start eventdev %d", opt->dev_id);
731 RTE_ETH_FOREACH_DEV(prod) {
732 ret = rte_eth_dev_start(prod);
734 evt_err("Ethernet dev [%d] failed to start."
735 " Using synthetic producer", prod);
741 RTE_ETH_FOREACH_DEV(prod) {
742 ret = rte_event_eth_rx_adapter_start(prod);
744 evt_err("Rx adapter[%d] start failed", prod);
748 ret = rte_event_eth_tx_adapter_start(prod);
750 evt_err("Tx adapter[%d] start failed", prod);
755 memcpy(t->tx_evqueue_id, tx_evqueue_id, sizeof(uint8_t) *
762 pipeline_queue_opt_dump(struct evt_options *opt)
764 pipeline_opt_dump(opt, pipeline_queue_nb_event_queues(opt));
768 pipeline_queue_opt_check(struct evt_options *opt)
770 return pipeline_opt_check(opt, pipeline_queue_nb_event_queues(opt));
774 pipeline_queue_capability_check(struct evt_options *opt)
776 struct rte_event_dev_info dev_info;
778 rte_event_dev_info_get(opt->dev_id, &dev_info);
779 if (dev_info.max_event_queues < pipeline_queue_nb_event_queues(opt) ||
780 dev_info.max_event_ports <
781 evt_nr_active_lcores(opt->wlcores)) {
782 evt_err("not enough eventdev queues=%d/%d or ports=%d/%d",
783 pipeline_queue_nb_event_queues(opt),
784 dev_info.max_event_queues,
785 evt_nr_active_lcores(opt->wlcores),
786 dev_info.max_event_ports);
792 static const struct evt_test_ops pipeline_queue = {
793 .cap_check = pipeline_queue_capability_check,
794 .opt_check = pipeline_queue_opt_check,
795 .opt_dump = pipeline_queue_opt_dump,
796 .test_setup = pipeline_test_setup,
797 .mempool_setup = pipeline_mempool_setup,
798 .ethdev_setup = pipeline_ethdev_setup,
799 .eventdev_setup = pipeline_queue_eventdev_setup,
800 .launch_lcores = pipeline_queue_launch_lcores,
801 .eventdev_destroy = pipeline_eventdev_destroy,
802 .mempool_destroy = pipeline_mempool_destroy,
803 .ethdev_destroy = pipeline_ethdev_destroy,
804 .test_result = pipeline_test_result,
805 .test_destroy = pipeline_test_destroy,
808 EVT_TEST_REGISTER(pipeline_queue);