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39 #include <rte_ethdev.h>
40 #include <rte_ether.h>
42 #include <rte_byteorder.h>
44 #include <rte_port_ring.h>
45 #include <rte_table_lpm.h>
46 #include <rte_pipeline.h>
50 #ifndef PIPELINE_LPM_TABLE_NUMBER_TABLE8s
51 #define PIPELINE_LPM_TABLE_NUMBER_TABLE8s 256
55 app_main_loop_worker_pipeline_lpm(void) {
56 struct rte_pipeline_params pipeline_params = {
58 .socket_id = rte_socket_id(),
61 struct rte_pipeline *p;
62 uint32_t port_in_id[APP_MAX_PORTS];
63 uint32_t port_out_id[APP_MAX_PORTS];
67 RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with "
68 "LPM table)\n", rte_lcore_id());
70 /* Pipeline configuration */
71 p = rte_pipeline_create(&pipeline_params);
73 rte_panic("Unable to configure the pipeline\n");
75 /* Input port configuration */
76 for (i = 0; i < app.n_ports; i++) {
77 struct rte_port_ring_reader_params port_ring_params = {
78 .ring = app.rings_rx[i],
81 struct rte_pipeline_port_in_params port_params = {
82 .ops = &rte_port_ring_reader_ops,
83 .arg_create = (void *) &port_ring_params,
86 .burst_size = app.burst_size_worker_read,
89 if (rte_pipeline_port_in_create(p, &port_params,
91 rte_panic("Unable to configure input port for "
95 /* Output port configuration */
96 for (i = 0; i < app.n_ports; i++) {
97 struct rte_port_ring_writer_params port_ring_params = {
98 .ring = app.rings_tx[i],
99 .tx_burst_sz = app.burst_size_worker_write,
102 struct rte_pipeline_port_out_params port_params = {
103 .ops = &rte_port_ring_writer_ops,
104 .arg_create = (void *) &port_ring_params,
109 if (rte_pipeline_port_out_create(p, &port_params,
111 rte_panic("Unable to configure output port for "
115 /* Table configuration */
117 struct rte_table_lpm_params table_lpm_params = {
120 .number_tbl8s = PIPELINE_LPM_TABLE_NUMBER_TABLE8s,
123 sizeof(struct rte_pipeline_table_entry),
124 .offset = APP_METADATA_OFFSET(32),
127 struct rte_pipeline_table_params table_params = {
128 .ops = &rte_table_lpm_ops,
129 .arg_create = &table_lpm_params,
130 .f_action_hit = NULL,
131 .f_action_miss = NULL,
133 .action_data_size = 0,
136 if (rte_pipeline_table_create(p, &table_params, &table_id))
137 rte_panic("Unable to configure the LPM table\n");
140 /* Interconnecting ports and tables */
141 for (i = 0; i < app.n_ports; i++)
142 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
144 rte_panic("Unable to connect input port %u to "
145 "table %u\n", port_in_id[i], table_id);
147 /* Add entries to tables */
148 for (i = 0; i < app.n_ports; i++) {
149 struct rte_pipeline_table_entry entry = {
150 .action = RTE_PIPELINE_ACTION_PORT,
151 {.port_id = port_out_id[i & (app.n_ports - 1)]},
154 struct rte_table_lpm_key key = {
155 .ip = i << (24 - __builtin_popcount(app.n_ports - 1)),
156 .depth = 8 + __builtin_popcount(app.n_ports - 1),
159 struct rte_pipeline_table_entry *entry_ptr;
161 int key_found, status;
163 printf("Adding rule to LPM table (IPv4 destination = %"
164 PRIu32 ".%" PRIu32 ".%" PRIu32 ".%" PRIu32 "/%" PRIu8
165 " => port out = %" PRIu32 ")\n",
166 (key.ip & 0xFF000000) >> 24,
167 (key.ip & 0x00FF0000) >> 16,
168 (key.ip & 0x0000FF00) >> 8,
173 status = rte_pipeline_table_entry_add(p, table_id, &key, &entry,
174 &key_found, &entry_ptr);
176 rte_panic("Unable to add entry to table %u (%d)\n",
180 /* Enable input ports */
181 for (i = 0; i < app.n_ports; i++)
182 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
183 rte_panic("Unable to enable input port %u\n",
186 /* Check pipeline consistency */
187 if (rte_pipeline_check(p) < 0)
188 rte_panic("Pipeline consistency check failed\n");
198 if ((i & APP_FLUSH) == 0)
199 rte_pipeline_flush(p);