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39 #include <rte_ethdev.h>
40 #include <rte_ether.h>
42 #include <rte_byteorder.h>
44 #include <rte_port_ring.h>
45 #include <rte_table_lpm.h>
46 #include <rte_pipeline.h>
51 app_main_loop_worker_pipeline_lpm(void) {
52 struct rte_pipeline_params pipeline_params = {
54 .socket_id = rte_socket_id(),
57 struct rte_pipeline *p;
58 uint32_t port_in_id[APP_MAX_PORTS];
59 uint32_t port_out_id[APP_MAX_PORTS];
63 RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with "
64 "LPM table)\n", rte_lcore_id());
66 /* Pipeline configuration */
67 p = rte_pipeline_create(&pipeline_params);
69 rte_panic("Unable to configure the pipeline\n");
71 /* Input port configuration */
72 for (i = 0; i < app.n_ports; i++) {
73 struct rte_port_ring_reader_params port_ring_params = {
74 .ring = app.rings_rx[i],
77 struct rte_pipeline_port_in_params port_params = {
78 .ops = &rte_port_ring_reader_ops,
79 .arg_create = (void *) &port_ring_params,
82 .burst_size = app.burst_size_worker_read,
85 if (rte_pipeline_port_in_create(p, &port_params,
87 rte_panic("Unable to configure input port for "
91 /* Output port configuration */
92 for (i = 0; i < app.n_ports; i++) {
93 struct rte_port_ring_writer_params port_ring_params = {
94 .ring = app.rings_tx[i],
95 .tx_burst_sz = app.burst_size_worker_write,
98 struct rte_pipeline_port_out_params port_params = {
99 .ops = &rte_port_ring_writer_ops,
100 .arg_create = (void *) &port_ring_params,
105 if (rte_pipeline_port_out_create(p, &port_params,
107 rte_panic("Unable to configure output port for "
111 /* Table configuration */
113 struct rte_table_lpm_params table_lpm_params = {
117 sizeof(struct rte_pipeline_table_entry),
118 .offset = APP_METADATA_OFFSET(32),
121 struct rte_pipeline_table_params table_params = {
122 .ops = &rte_table_lpm_ops,
123 .arg_create = &table_lpm_params,
124 .f_action_hit = NULL,
125 .f_action_miss = NULL,
127 .action_data_size = 0,
130 if (rte_pipeline_table_create(p, &table_params, &table_id))
131 rte_panic("Unable to configure the LPM table\n");
134 /* Interconnecting ports and tables */
135 for (i = 0; i < app.n_ports; i++)
136 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
138 rte_panic("Unable to connect input port %u to "
139 "table %u\n", port_in_id[i], table_id);
141 /* Add entries to tables */
142 for (i = 0; i < app.n_ports; i++) {
143 struct rte_pipeline_table_entry entry = {
144 .action = RTE_PIPELINE_ACTION_PORT,
145 {.port_id = port_out_id[i & (app.n_ports - 1)]},
148 struct rte_table_lpm_key key = {
149 .ip = i << (24 - __builtin_popcount(app.n_ports - 1)),
150 .depth = 8 + __builtin_popcount(app.n_ports - 1),
153 struct rte_pipeline_table_entry *entry_ptr;
155 int key_found, status;
157 printf("Adding rule to LPM table (IPv4 destination = %"
158 PRIu32 ".%" PRIu32 ".%" PRIu32 ".%" PRIu32 "/%" PRIu8
159 " => port out = %" PRIu32 ")\n",
160 (key.ip & 0xFF000000) >> 24,
161 (key.ip & 0x00FF0000) >> 16,
162 (key.ip & 0x0000FF00) >> 8,
167 status = rte_pipeline_table_entry_add(p, table_id, &key, &entry,
168 &key_found, &entry_ptr);
170 rte_panic("Unable to add entry to table %u (%d)\n",
174 /* Enable input ports */
175 for (i = 0; i < app.n_ports; i++)
176 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
177 rte_panic("Unable to enable input port %u\n",
180 /* Check pipeline consistency */
181 if (rte_pipeline_check(p) < 0)
182 rte_panic("Pipeline consistency check failed\n");
192 if ((i & APP_FLUSH) == 0)
193 rte_pipeline_flush(p);