app/test-pipeline/pipeline_stub.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <stdint.h>
   8
   9 #include <rte_log.h>
  10 #include <rte_port_ring.h>
  11 #include <rte_table_stub.h>
  12 #include <rte_pipeline.h>
  13
  14 #include "main.h"
  15
  16 void
  17 app_main_loop_worker_pipeline_stub(void) {
  18         struct rte_pipeline_params pipeline_params = {
  19                 .name = "pipeline",
  20                 .socket_id = rte_socket_id(),
  21         };
  22
  23         struct rte_pipeline *p;
  24         uint32_t port_in_id[APP_MAX_PORTS];
  25         uint32_t port_out_id[APP_MAX_PORTS];
  26         uint32_t table_id[APP_MAX_PORTS];
  27         uint32_t i;
  28
  29         RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with stub "
  30                 "tables)\n", rte_lcore_id());
  31
  32         /* Pipeline configuration */
  33         p = rte_pipeline_create(&pipeline_params);
  34         if (p == NULL)
  35                 rte_panic("Unable to configure the pipeline\n");
  36
  37         /* Input port configuration */
  38         for (i = 0; i < app.n_ports; i++) {
  39                 struct rte_port_ring_reader_params port_ring_params = {
  40                         .ring = app.rings_rx[i],
  41                 };
  42
  43                 struct rte_pipeline_port_in_params port_params = {
  44                         .ops = &rte_port_ring_reader_ops,
  45                         .arg_create = (void *) &port_ring_params,
  46                         .f_action = NULL,
  47                         .arg_ah = NULL,
  48                         .burst_size = app.burst_size_worker_read,
  49                 };
  50
  51                 if (rte_pipeline_port_in_create(p, &port_params,
  52                         &port_in_id[i]))
  53                         rte_panic("Unable to configure input port for "
  54                                 "ring %d\n", i);
  55         }
  56
  57         /* Output port configuration */
  58         for (i = 0; i < app.n_ports; i++) {
  59                 struct rte_port_ring_writer_params port_ring_params = {
  60                         .ring = app.rings_tx[i],
  61                         .tx_burst_sz = app.burst_size_worker_write,
  62                 };
  63
  64                 struct rte_pipeline_port_out_params port_params = {
  65                         .ops = &rte_port_ring_writer_ops,
  66                         .arg_create = (void *) &port_ring_params,
  67                         .f_action = NULL,
  68                         .arg_ah = NULL,
  69                 };
  70
  71                 if (rte_pipeline_port_out_create(p, &port_params,
  72                         &port_out_id[i]))
  73                         rte_panic("Unable to configure output port for "
  74                                 "ring %d\n", i);
  75         }
  76
  77         /* Table configuration */
  78         for (i = 0; i < app.n_ports; i++) {
  79                 struct rte_pipeline_table_params table_params = {
  80                         .ops = &rte_table_stub_ops,
  81                         .arg_create = NULL,
  82                         .f_action_hit = NULL,
  83                         .f_action_miss = NULL,
  84                         .arg_ah = NULL,
  85                         .action_data_size = 0,
  86                 };
  87
  88                 if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
  89                         rte_panic("Unable to configure table %u\n", i);
  90         }
  91
  92         /* Interconnecting ports and tables */
  93         for (i = 0; i < app.n_ports; i++)
  94                 if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
  95                                 table_id[i]))
  96                         rte_panic("Unable to connect input port %u to "
  97                                 "table %u\n", port_in_id[i],  table_id[i]);
  98
  99         /* Add entries to tables */
 100         for (i = 0; i < app.n_ports; i++) {
 101                 struct rte_pipeline_table_entry entry = {
 102                         .action = RTE_PIPELINE_ACTION_PORT,
 103                         {.port_id = port_out_id[i ^ 1]},
 104                 };
 105                 struct rte_pipeline_table_entry *default_entry_ptr;
 106
 107                 if (rte_pipeline_table_default_entry_add(p, table_id[i], &entry,
 108                         &default_entry_ptr))
 109                         rte_panic("Unable to add default entry to table %u\n",
 110                                 table_id[i]);
 111         }
 112
 113         /* Enable input ports */
 114         for (i = 0; i < app.n_ports; i++)
 115                 if (rte_pipeline_port_in_enable(p, port_in_id[i]))
 116                         rte_panic("Unable to enable input port %u\n",
 117                                 port_in_id[i]);
 118
 119         /* Check pipeline consistency */
 120         if (rte_pipeline_check(p) < 0)
 121                 rte_panic("Pipeline consistency check failed\n");
 122
 123         /* Run-time */
 124 #if APP_FLUSH == 0
 125         for ( ; ; )
 126                 rte_pipeline_run(p);
 127 #else
 128         for (i = 0; ; i++) {
 129                 rte_pipeline_run(p);
 130
 131                 if ((i & APP_FLUSH) == 0)
 132                         rte_pipeline_flush(p);
 133         }
 134 #endif
 135 }