4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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42 #include <sys/queue.h>
45 #include <rte_common.h>
46 #include <rte_byteorder.h>
48 #include <rte_debug.h>
49 #include <rte_cycles.h>
50 #include <rte_memory.h>
51 #include <rte_memzone.h>
52 #include <rte_launch.h>
54 #include <rte_per_lcore.h>
55 #include <rte_lcore.h>
56 #include <rte_atomic.h>
57 #include <rte_branch_prediction.h>
59 #include <rte_memory.h>
60 #include <rte_mempool.h>
62 #include <rte_interrupts.h>
64 #include <rte_ether.h>
65 #include <rte_ethdev.h>
66 #include <rte_string_fns.h>
71 * The structure of a PTP V2 packet.
73 * Only the minimum fields used by the ieee1588 test are represented.
77 uint8_t version; /**< must be 0x02 */
80 #define PTP_SYNC_MESSAGE 0x0
81 #define PTP_DELAY_REQ_MESSAGE 0x1
82 #define PTP_PATH_DELAY_REQ_MESSAGE 0x2
83 #define PTP_PATH_DELAY_RESP_MESSAGE 0x3
84 #define PTP_FOLLOWUP_MESSAGE 0x8
85 #define PTP_DELAY_RESP_MESSAGE 0x9
86 #define PTP_PATH_DELAY_FOLLOWUP_MESSAGE 0xA
87 #define PTP_ANNOUNCE_MESSAGE 0xB
88 #define PTP_SIGNALLING_MESSAGE 0xC
89 #define PTP_MANAGEMENT_MESSAGE 0xD
92 * Forwarding of IEEE1588 Precise Time Protocol (PTP) packets.
94 * In this mode, packets are received one by one and are expected to be
95 * PTP V2 L2 Ethernet frames (with the specific Ethernet type "0x88F7")
96 * containing PTP "sync" messages (version 2 at offset 1, and message ID
99 * Check that each received packet is a IEEE1588 PTP V2 packet of type
100 * PTP_SYNC_MESSAGE, and that it has been identified and timestamped
102 * Check that the value of the last RX timestamp recorded by the controller
103 * is greater than the previous one.
105 * If everything is OK, send the received packet back on the same port,
106 * requesting for it to be timestamped by the hardware.
107 * Check that the value of the last TX timestamp recorded by the controller
108 * is greater than the previous one.
112 * 1GbE 82576 Kawela registers used for IEEE1588 hardware support
114 #define IGBE_82576_ETQF(n) (0x05CB0 + (4 * (n)))
115 #define IGBE_82576_ETQF_FILTER_ENABLE (1 << 26)
116 #define IGBE_82576_ETQF_1588_TIMESTAMP (1 << 30)
118 #define IGBE_82576_TSYNCRXCTL 0x0B620
119 #define IGBE_82576_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
121 #define IGBE_82576_RXSTMPL 0x0B624
122 #define IGBE_82576_RXSTMPH 0x0B628
123 #define IGBE_82576_RXSATRL 0x0B62C
124 #define IGBE_82576_RXSATRH 0x0B630
125 #define IGBE_82576_TSYNCTXCTL 0x0B614
126 #define IGBE_82576_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
128 #define IGBE_82576_TXSTMPL 0x0B618
129 #define IGBE_82576_TXSTMPH 0x0B61C
130 #define IGBE_82576_SYSTIML 0x0B600
131 #define IGBE_82576_SYSTIMH 0x0B604
132 #define IGBE_82576_TIMINCA 0x0B608
133 #define IGBE_82576_TIMADJL 0x0B60C
134 #define IGBE_82576_TIMADJH 0x0B610
135 #define IGBE_82576_TSAUXC 0x0B640
136 #define IGBE_82576_TRGTTIML0 0x0B644
137 #define IGBE_82576_TRGTTIMH0 0x0B648
138 #define IGBE_82576_TRGTTIML1 0x0B64C
139 #define IGBE_82576_TRGTTIMH1 0x0B650
140 #define IGBE_82576_AUXSTMPL0 0x0B65C
141 #define IGBE_82576_AUXSTMPH0 0x0B660
142 #define IGBE_82576_AUXSTMPL1 0x0B664
143 #define IGBE_82576_AUXSTMPH1 0x0B668
144 #define IGBE_82576_TSYNCRXCFG 0x05F50
145 #define IGBE_82576_TSSDP 0x0003C
148 * 10GbE 82599 Niantic registers used for IEEE1588 hardware support
150 #define IXGBE_82599_ETQF(n) (0x05128 + (4 * (n)))
151 #define IXGBE_82599_ETQF_FILTER_ENABLE (1 << 31)
152 #define IXGBE_82599_ETQF_1588_TIMESTAMP (1 << 30)
154 #define IXGBE_82599_TSYNCRXCTL 0x05188
155 #define IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
157 #define IXGBE_82599_RXSTMPL 0x051E8
158 #define IXGBE_82599_RXSTMPH 0x051A4
159 #define IXGBE_82599_RXSATRL 0x051A0
160 #define IXGBE_82599_RXSATRH 0x051A8
161 #define IXGBE_82599_RXMTRL 0x05120
162 #define IXGBE_82599_TSYNCTXCTL 0x08C00
163 #define IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
165 #define IXGBE_82599_TXSTMPL 0x08C04
166 #define IXGBE_82599_TXSTMPH 0x08C08
167 #define IXGBE_82599_SYSTIML 0x08C0C
168 #define IXGBE_82599_SYSTIMH 0x08C10
169 #define IXGBE_82599_TIMINCA 0x08C14
170 #define IXGBE_82599_TIMADJL 0x08C18
171 #define IXGBE_82599_TIMADJH 0x08C1C
172 #define IXGBE_82599_TSAUXC 0x08C20
173 #define IXGBE_82599_TRGTTIML0 0x08C24
174 #define IXGBE_82599_TRGTTIMH0 0x08C28
175 #define IXGBE_82599_TRGTTIML1 0x08C2C
176 #define IXGBE_82599_TRGTTIMH1 0x08C30
177 #define IXGBE_82599_AUXSTMPL0 0x08C3C
178 #define IXGBE_82599_AUXSTMPH0 0x08C40
179 #define IXGBE_82599_AUXSTMPL1 0x08C44
180 #define IXGBE_82599_AUXSTMPH1 0x08C48
183 * Mandatory ETQF register for IEEE1588 packets filter.
185 #define ETQF_FILTER_1588_REG 3
188 * Recommended value for increment and period of
189 * the Increment Attribute Register.
191 #define IEEE1588_TIMINCA_INIT ((0x02 << 24) | 0x00F42400)
194 * Data structure with pointers to port-specific functions.
196 typedef void (*ieee1588_start_t)(portid_t pi); /**< Start IEEE1588 feature. */
197 typedef void (*ieee1588_stop_t)(portid_t pi); /**< Stop IEEE1588 feature. */
198 typedef int (*tmst_read_t)(portid_t pi, uint64_t *tmst); /**< Read TMST regs */
200 struct port_ieee1588_ops {
201 ieee1588_start_t ieee1588_start;
202 ieee1588_stop_t ieee1588_stop;
203 tmst_read_t rx_tmst_read;
204 tmst_read_t tx_tmst_read;
208 * 1GbE 82576 IEEE1588 operations.
211 igbe_82576_ieee1588_start(portid_t pi)
216 * Start incrementation of the System Time registers used to
217 * timestamp PTP packets.
219 port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, IEEE1588_TIMINCA_INIT);
220 port_id_pci_reg_write(pi, IGBE_82576_TSAUXC, 0);
223 * Enable L2 filtering of IEEE1588 Ethernet frame types.
225 port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG),
227 IGBE_82576_ETQF_FILTER_ENABLE |
228 IGBE_82576_ETQF_1588_TIMESTAMP));
231 * Enable timestamping of received PTP packets.
233 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
234 tsync_ctl |= IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
235 port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
238 * Enable Timestamping of transmitted PTP packets.
240 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
241 tsync_ctl |= IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
242 port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
246 igbe_82576_ieee1588_stop(portid_t pi)
251 * Disable Timestamping of transmitted PTP packets.
253 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
254 tsync_ctl &= ~IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
255 port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
258 * Disable timestamping of received PTP packets.
260 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
261 tsync_ctl &= ~IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
262 port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
265 * Disable L2 filtering of IEEE1588 Ethernet types.
267 port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG), 0);
270 * Stop incrementation of the System Time registers.
272 port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, 0);
276 * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
277 * of a 1GbE 82576 port.
280 * The port identifier.
283 * The address of a 64-bit variable to return the value of the RX timestamp.
286 * -1: the RXSTMPL and RXSTMPH registers of the port are not valid.
287 * 0: the variable pointed to by the "tmst" parameter contains the value
288 * of the RXSTMPL and RXSTMPH registers of the port.
291 igbe_82576_rx_timestamp_read(portid_t pi, uint64_t *tmst)
293 uint32_t tsync_rxctl;
297 tsync_rxctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
298 if ((tsync_rxctl & 0x01) == 0)
301 rx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPL);
302 rx_stmph = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPH);
303 *tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
308 * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
309 * of a 1GbE 82576 port.
312 * The port identifier.
315 * The address of a 64-bit variable to return the value of the TX timestamp.
318 * -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
319 * 0: the variable pointed to by the "tmst" parameter contains the value
320 * of the TXSTMPL and TXSTMPH registers of the port.
323 igbe_82576_tx_timestamp_read(portid_t pi, uint64_t *tmst)
325 uint32_t tsync_txctl;
329 tsync_txctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
330 if ((tsync_txctl & 0x01) == 0)
333 tx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPL);
334 tx_stmph = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPH);
335 *tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
339 static struct port_ieee1588_ops igbe_82576_ieee1588_ops = {
340 .ieee1588_start = igbe_82576_ieee1588_start,
341 .ieee1588_stop = igbe_82576_ieee1588_stop,
342 .rx_tmst_read = igbe_82576_rx_timestamp_read,
343 .tx_tmst_read = igbe_82576_tx_timestamp_read,
347 * 10GbE 82599 IEEE1588 operations.
350 ixgbe_82599_ieee1588_start(portid_t pi)
355 * Start incrementation of the System Time registers used to
356 * timestamp PTP packets.
358 port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, IEEE1588_TIMINCA_INIT);
361 * Enable L2 filtering of IEEE1588 Ethernet frame types.
363 port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG),
365 IXGBE_82599_ETQF_FILTER_ENABLE |
366 IXGBE_82599_ETQF_1588_TIMESTAMP));
369 * Enable timestamping of received PTP packets.
371 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
372 tsync_ctl |= IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
373 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
376 * Enable Timestamping of transmitted PTP packets.
378 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
379 tsync_ctl |= IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
380 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
384 ixgbe_82599_ieee1588_stop(portid_t pi)
389 * Disable Timestamping of transmitted PTP packets.
391 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
392 tsync_ctl &= ~IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
393 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
396 * Disable timestamping of received PTP packets.
398 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
399 tsync_ctl &= ~IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
400 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
403 * Disable L2 filtering of IEEE1588 Ethernet frame types.
405 port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG), 0);
408 * Stop incrementation of the System Time registers.
410 port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, 0);
414 * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
415 * of a 10GbE 82599 port.
418 * The port identifier.
421 * The address of a 64-bit variable to return the value of the TX timestamp.
424 * -1: the RX timestamp registers of the port are not valid.
425 * 0: the variable pointed to by the "tmst" parameter contains the value
426 * of the RXSTMPL and RXSTMPH registers of the port.
429 ixgbe_82599_rx_timestamp_read(portid_t pi, uint64_t *tmst)
431 uint32_t tsync_rxctl;
435 tsync_rxctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
436 if ((tsync_rxctl & 0x01) == 0)
439 rx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPL);
440 rx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPH);
441 *tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
446 * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
447 * of a 10GbE 82599 port.
450 * The port identifier.
453 * The address of a 64-bit variable to return the value of the TX timestamp.
456 * -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
457 * 0: the variable pointed to by the "tmst" parameter contains the value
458 * of the TXSTMPL and TXSTMPH registers of the port.
461 ixgbe_82599_tx_timestamp_read(portid_t pi, uint64_t *tmst)
463 uint32_t tsync_txctl;
467 tsync_txctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
468 if ((tsync_txctl & 0x01) == 0)
471 tx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPL);
472 tx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPH);
473 *tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
477 static struct port_ieee1588_ops ixgbe_82599_ieee1588_ops = {
478 .ieee1588_start = ixgbe_82599_ieee1588_start,
479 .ieee1588_stop = ixgbe_82599_ieee1588_stop,
480 .rx_tmst_read = ixgbe_82599_rx_timestamp_read,
481 .tx_tmst_read = ixgbe_82599_tx_timestamp_read,
485 port_ieee1588_rx_timestamp_check(portid_t pi)
487 struct port_ieee1588_ops *ieee_ops;
490 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
491 if (ieee_ops->rx_tmst_read(pi, &rx_tmst) < 0) {
492 printf("Port %u: RX timestamp registers not valid\n",
496 printf("Port %u RX timestamp value 0x%"PRIu64"\n",
497 (unsigned) pi, rx_tmst);
500 #define MAX_TX_TMST_WAIT_MICROSECS 1000 /**< 1 milli-second */
503 port_ieee1588_tx_timestamp_check(portid_t pi)
505 struct port_ieee1588_ops *ieee_ops;
509 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
511 while ((ieee_ops->tx_tmst_read(pi, &tx_tmst) < 0) &&
512 (wait_us < MAX_TX_TMST_WAIT_MICROSECS)) {
516 if (wait_us >= MAX_TX_TMST_WAIT_MICROSECS) {
517 printf("Port %u: TX timestamp registers not valid after"
518 "%u micro-seconds\n",
519 (unsigned) pi, (unsigned) MAX_TX_TMST_WAIT_MICROSECS);
522 printf("Port %u TX timestamp value 0x%"PRIu64" validated after "
523 "%u micro-second%s\n",
524 (unsigned) pi, tx_tmst, wait_us,
525 (wait_us == 1) ? "" : "s");
529 ieee1588_packet_fwd(struct fwd_stream *fs)
532 struct ether_hdr *eth_hdr;
533 struct ptpv2_msg *ptp_hdr;
537 * Receive 1 packet at a time.
539 if (rte_eth_rx_burst(fs->rx_port, fs->rx_queue, &mb, 1) == 0)
545 * Check that the received packet is a PTP packet that was detected
548 eth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);
549 eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
550 if (! (mb->ol_flags & PKT_RX_IEEE1588_PTP)) {
551 if (eth_type == ETHER_TYPE_1588) {
552 printf("Port %u Received PTP packet not filtered"
554 (unsigned) fs->rx_port);
556 printf("Port %u Received non PTP packet type=0x%4x "
558 (unsigned) fs->rx_port, eth_type,
559 (unsigned) mb->pkt_len);
561 rte_pktmbuf_free(mb);
564 if (eth_type != ETHER_TYPE_1588) {
565 printf("Port %u Received NON PTP packet wrongly"
566 " detected by hardware\n",
567 (unsigned) fs->rx_port);
568 rte_pktmbuf_free(mb);
573 * Check that the received PTP packet is a PTP V2 packet of type
576 ptp_hdr = rte_pktmbuf_mtod_offset(mb, struct ptpv2_msg *,
577 sizeof(struct ether_hdr));
578 if (ptp_hdr->version != 0x02) {
579 printf("Port %u Received PTP V2 Ethernet frame with wrong PTP"
580 " protocol version 0x%x (should be 0x02)\n",
581 (unsigned) fs->rx_port, ptp_hdr->version);
582 rte_pktmbuf_free(mb);
585 if (ptp_hdr->msg_id != PTP_SYNC_MESSAGE) {
586 printf("Port %u Received PTP V2 Ethernet frame with unexpected"
587 " messageID 0x%x (expected 0x0 - PTP_SYNC_MESSAGE)\n",
588 (unsigned) fs->rx_port, ptp_hdr->msg_id);
589 rte_pktmbuf_free(mb);
592 printf("Port %u IEEE1588 PTP V2 SYNC Message filtered by hardware\n",
593 (unsigned) fs->rx_port);
596 * Check that the received PTP packet has been timestamped by the
599 if (! (mb->ol_flags & PKT_RX_IEEE1588_TMST)) {
600 printf("Port %u Received PTP packet not timestamped"
602 (unsigned) fs->rx_port);
603 rte_pktmbuf_free(mb);
607 /* Check the RX timestamp */
608 port_ieee1588_rx_timestamp_check(fs->rx_port);
610 /* Forward PTP packet with hardware TX timestamp */
611 mb->ol_flags |= PKT_TX_IEEE1588_TMST;
613 if (rte_eth_tx_burst(fs->rx_port, fs->tx_queue, &mb, 1) == 0) {
614 printf("Port %u sent PTP packet dropped\n",
615 (unsigned) fs->rx_port);
616 fs->fwd_dropped += 1;
617 rte_pktmbuf_free(mb);
622 * Check the TX timestamp.
624 port_ieee1588_tx_timestamp_check(fs->rx_port);
628 port_ieee1588_fwd_begin(portid_t pi)
630 struct port_ieee1588_ops *ieee_ops;
632 if (strcmp(ports[pi].dev_info.driver_name, "rte_igb_pmd") == 0)
633 ieee_ops = &igbe_82576_ieee1588_ops;
635 ieee_ops = &ixgbe_82599_ieee1588_ops;
636 ports[pi].fwd_ctx = ieee_ops;
637 (ieee_ops->ieee1588_start)(pi);
641 port_ieee1588_fwd_end(portid_t pi)
643 struct port_ieee1588_ops *ieee_ops;
645 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
646 (ieee_ops->ieee1588_stop)(pi);
649 struct fwd_engine ieee1588_fwd_engine = {
650 .fwd_mode_name = "ieee1588",
651 .port_fwd_begin = port_ieee1588_fwd_begin,
652 .port_fwd_end = port_ieee1588_fwd_end,
653 .packet_fwd = ieee1588_packet_fwd,