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43 #include <sys/queue.h>
46 #include <rte_common.h>
47 #include <rte_byteorder.h>
49 #include <rte_debug.h>
50 #include <rte_cycles.h>
51 #include <rte_memory.h>
52 #include <rte_memzone.h>
53 #include <rte_launch.h>
54 #include <rte_tailq.h>
56 #include <rte_per_lcore.h>
57 #include <rte_lcore.h>
58 #include <rte_atomic.h>
59 #include <rte_branch_prediction.h>
61 #include <rte_memory.h>
62 #include <rte_mempool.h>
64 #include <rte_interrupts.h>
66 #include <rte_ether.h>
67 #include <rte_ethdev.h>
68 #include <rte_string_fns.h>
73 * The structure of a PTP V2 packet.
75 * Only the minimum fields used by the ieee1588 test are represented.
79 uint8_t version; /**< must be 0x02 */
82 #define PTP_SYNC_MESSAGE 0x0
83 #define PTP_DELAY_REQ_MESSAGE 0x1
84 #define PTP_PATH_DELAY_REQ_MESSAGE 0x2
85 #define PTP_PATH_DELAY_RESP_MESSAGE 0x3
86 #define PTP_FOLLOWUP_MESSAGE 0x8
87 #define PTP_DELAY_RESP_MESSAGE 0x9
88 #define PTP_PATH_DELAY_FOLLOWUP_MESSAGE 0xA
89 #define PTP_ANNOUNCE_MESSAGE 0xB
90 #define PTP_SIGNALLING_MESSAGE 0xC
91 #define PTP_MANAGEMENT_MESSAGE 0xD
94 * Forwarding of IEEE1588 Precise Time Protocol (PTP) packets.
96 * In this mode, packets are received one by one and are expected to be
97 * PTP V2 L2 Ethernet frames (with the specific Ethernet type "0x88F7")
98 * containing PTP "sync" messages (version 2 at offset 1, and message ID
101 * Check that each received packet is a IEEE1588 PTP V2 packet of type
102 * PTP_SYNC_MESSAGE, and that it has been identified and timestamped
104 * Check that the value of the last RX timestamp recorded by the controller
105 * is greater than the previous one.
107 * If everything is OK, send the received packet back on the same port,
108 * requesting for it to be timestamped by the hardware.
109 * Check that the value of the last TX timestamp recorded by the controller
110 * is greater than the previous one.
114 * 1GbE 82576 Kawela registers used for IEEE1588 hardware support
116 #define IGBE_82576_ETQF(n) (0x05CB0 + (4 * (n)))
117 #define IGBE_82576_ETQF_FILTER_ENABLE (1 << 26)
118 #define IGBE_82576_ETQF_1588_TIMESTAMP (1 << 30)
120 #define IGBE_82576_TSYNCRXCTL 0x0B620
121 #define IGBE_82576_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
123 #define IGBE_82576_RXSTMPL 0x0B624
124 #define IGBE_82576_RXSTMPH 0x0B628
125 #define IGBE_82576_RXSATRL 0x0B62C
126 #define IGBE_82576_RXSATRH 0x0B630
127 #define IGBE_82576_TSYNCTXCTL 0x0B614
128 #define IGBE_82576_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
130 #define IGBE_82576_TXSTMPL 0x0B618
131 #define IGBE_82576_TXSTMPH 0x0B61C
132 #define IGBE_82576_SYSTIML 0x0B600
133 #define IGBE_82576_SYSTIMH 0x0B604
134 #define IGBE_82576_TIMINCA 0x0B608
135 #define IGBE_82576_TIMADJL 0x0B60C
136 #define IGBE_82576_TIMADJH 0x0B610
137 #define IGBE_82576_TSAUXC 0x0B640
138 #define IGBE_82576_TRGTTIML0 0x0B644
139 #define IGBE_82576_TRGTTIMH0 0x0B648
140 #define IGBE_82576_TRGTTIML1 0x0B64C
141 #define IGBE_82576_TRGTTIMH1 0x0B650
142 #define IGBE_82576_AUXSTMPL0 0x0B65C
143 #define IGBE_82576_AUXSTMPH0 0x0B660
144 #define IGBE_82576_AUXSTMPL1 0x0B664
145 #define IGBE_82576_AUXSTMPH1 0x0B668
146 #define IGBE_82576_TSYNCRXCFG 0x05F50
147 #define IGBE_82576_TSSDP 0x0003C
150 * 10GbE 82599 Niantic registers used for IEEE1588 hardware support
152 #define IXGBE_82599_ETQF(n) (0x05128 + (4 * (n)))
153 #define IXGBE_82599_ETQF_FILTER_ENABLE (1 << 31)
154 #define IXGBE_82599_ETQF_1588_TIMESTAMP (1 << 30)
156 #define IXGBE_82599_TSYNCRXCTL 0x05188
157 #define IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
159 #define IXGBE_82599_RXSTMPL 0x051E8
160 #define IXGBE_82599_RXSTMPH 0x051A4
161 #define IXGBE_82599_RXSATRL 0x051A0
162 #define IXGBE_82599_RXSATRH 0x051A8
163 #define IXGBE_82599_RXMTRL 0x05120
164 #define IXGBE_82599_TSYNCTXCTL 0x08C00
165 #define IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
167 #define IXGBE_82599_TXSTMPL 0x08C04
168 #define IXGBE_82599_TXSTMPH 0x08C08
169 #define IXGBE_82599_SYSTIML 0x08C0C
170 #define IXGBE_82599_SYSTIMH 0x08C10
171 #define IXGBE_82599_TIMINCA 0x08C14
172 #define IXGBE_82599_TIMADJL 0x08C18
173 #define IXGBE_82599_TIMADJH 0x08C1C
174 #define IXGBE_82599_TSAUXC 0x08C20
175 #define IXGBE_82599_TRGTTIML0 0x08C24
176 #define IXGBE_82599_TRGTTIMH0 0x08C28
177 #define IXGBE_82599_TRGTTIML1 0x08C2C
178 #define IXGBE_82599_TRGTTIMH1 0x08C30
179 #define IXGBE_82599_AUXSTMPL0 0x08C3C
180 #define IXGBE_82599_AUXSTMPH0 0x08C40
181 #define IXGBE_82599_AUXSTMPL1 0x08C44
182 #define IXGBE_82599_AUXSTMPH1 0x08C48
185 * Mandatory ETQF register for IEEE1588 packets filter.
187 #define ETQF_FILTER_1588_REG 3
190 * Recommended value for increment and period of
191 * the Increment Attribute Register.
193 #define IEEE1588_TIMINCA_INIT ((0x02 << 24) | 0x00F42400)
196 * Data structure with pointers to port-specific functions.
198 typedef void (*ieee1588_start_t)(portid_t pi); /**< Start IEEE1588 feature. */
199 typedef void (*ieee1588_stop_t)(portid_t pi); /**< Stop IEEE1588 feature. */
200 typedef int (*tmst_read_t)(portid_t pi, uint64_t *tmst); /**< Read TMST regs */
202 struct port_ieee1588_ops {
203 ieee1588_start_t ieee1588_start;
204 ieee1588_stop_t ieee1588_stop;
205 tmst_read_t rx_tmst_read;
206 tmst_read_t tx_tmst_read;
210 * 1GbE 82576 IEEE1588 operations.
213 igbe_82576_ieee1588_start(portid_t pi)
218 * Start incrementation of the System Time registers used to
219 * timestamp PTP packets.
221 port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, IEEE1588_TIMINCA_INIT);
222 port_id_pci_reg_write(pi, IGBE_82576_TSAUXC, 0);
225 * Enable L2 filtering of IEEE1588 Ethernet frame types.
227 port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG),
229 IGBE_82576_ETQF_FILTER_ENABLE |
230 IGBE_82576_ETQF_1588_TIMESTAMP));
233 * Enable timestamping of received PTP packets.
235 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
236 tsync_ctl |= IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
237 port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
240 * Enable Timestamping of transmitted PTP packets.
242 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
243 tsync_ctl |= IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
244 port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
248 igbe_82576_ieee1588_stop(portid_t pi)
253 * Disable Timestamping of transmitted PTP packets.
255 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
256 tsync_ctl &= ~IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
257 port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
260 * Disable timestamping of received PTP packets.
262 tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
263 tsync_ctl &= ~IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
264 port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
267 * Disable L2 filtering of IEEE1588 Ethernet types.
269 port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG), 0);
272 * Stop incrementation of the System Time registers.
274 port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, 0);
278 * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
279 * of a 1GbE 82576 port.
282 * The port identifier.
285 * The address of a 64-bit variable to return the value of the RX timestamp.
288 * -1: the RXSTMPL and RXSTMPH registers of the port are not valid.
289 * 0: the variable pointed to by the "tmst" parameter contains the value
290 * of the RXSTMPL and RXSTMPH registers of the port.
293 igbe_82576_rx_timestamp_read(portid_t pi, uint64_t *tmst)
295 uint32_t tsync_rxctl;
299 tsync_rxctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
300 if ((tsync_rxctl & 0x01) == 0)
303 rx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPL);
304 rx_stmph = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPH);
305 *tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
310 * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
311 * of a 1GbE 82576 port.
314 * The port identifier.
317 * The address of a 64-bit variable to return the value of the TX timestamp.
320 * -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
321 * 0: the variable pointed to by the "tmst" parameter contains the value
322 * of the TXSTMPL and TXSTMPH registers of the port.
325 igbe_82576_tx_timestamp_read(portid_t pi, uint64_t *tmst)
327 uint32_t tsync_txctl;
331 tsync_txctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
332 if ((tsync_txctl & 0x01) == 0)
335 tx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPL);
336 tx_stmph = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPH);
337 *tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
341 static struct port_ieee1588_ops igbe_82576_ieee1588_ops = {
342 .ieee1588_start = igbe_82576_ieee1588_start,
343 .ieee1588_stop = igbe_82576_ieee1588_stop,
344 .rx_tmst_read = igbe_82576_rx_timestamp_read,
345 .tx_tmst_read = igbe_82576_tx_timestamp_read,
349 * 10GbE 82599 IEEE1588 operations.
352 ixgbe_82599_ieee1588_start(portid_t pi)
357 * Start incrementation of the System Time registers used to
358 * timestamp PTP packets.
360 port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, IEEE1588_TIMINCA_INIT);
363 * Enable L2 filtering of IEEE1588 Ethernet frame types.
365 port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG),
367 IXGBE_82599_ETQF_FILTER_ENABLE |
368 IXGBE_82599_ETQF_1588_TIMESTAMP));
371 * Enable timestamping of received PTP packets.
373 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
374 tsync_ctl |= IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
375 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
378 * Enable Timestamping of transmitted PTP packets.
380 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
381 tsync_ctl |= IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
382 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
386 ixgbe_82599_ieee1588_stop(portid_t pi)
391 * Disable Timestamping of transmitted PTP packets.
393 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
394 tsync_ctl &= ~IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
395 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
398 * Disable timestamping of received PTP packets.
400 tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
401 tsync_ctl &= ~IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
402 port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
405 * Disable L2 filtering of IEEE1588 Ethernet frame types.
407 port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG), 0);
410 * Stop incrementation of the System Time registers.
412 port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, 0);
416 * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
417 * of a 10GbE 82599 port.
420 * The port identifier.
423 * The address of a 64-bit variable to return the value of the TX timestamp.
426 * -1: the RX timestamp registers of the port are not valid.
427 * 0: the variable pointed to by the "tmst" parameter contains the value
428 * of the RXSTMPL and RXSTMPH registers of the port.
431 ixgbe_82599_rx_timestamp_read(portid_t pi, uint64_t *tmst)
433 uint32_t tsync_rxctl;
437 tsync_rxctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
438 if ((tsync_rxctl & 0x01) == 0)
441 rx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPL);
442 rx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPH);
443 *tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
448 * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
449 * of a 10GbE 82599 port.
452 * The port identifier.
455 * The address of a 64-bit variable to return the value of the TX timestamp.
458 * -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
459 * 0: the variable pointed to by the "tmst" parameter contains the value
460 * of the TXSTMPL and TXSTMPH registers of the port.
463 ixgbe_82599_tx_timestamp_read(portid_t pi, uint64_t *tmst)
465 uint32_t tsync_txctl;
469 tsync_txctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
470 if ((tsync_txctl & 0x01) == 0)
473 tx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPL);
474 tx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPH);
475 *tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
479 static struct port_ieee1588_ops ixgbe_82599_ieee1588_ops = {
480 .ieee1588_start = ixgbe_82599_ieee1588_start,
481 .ieee1588_stop = ixgbe_82599_ieee1588_stop,
482 .rx_tmst_read = ixgbe_82599_rx_timestamp_read,
483 .tx_tmst_read = ixgbe_82599_tx_timestamp_read,
487 port_ieee1588_rx_timestamp_check(portid_t pi)
489 struct port_ieee1588_ops *ieee_ops;
492 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
493 if (ieee_ops->rx_tmst_read(pi, &rx_tmst) < 0) {
494 printf("Port %u: RX timestamp registers not valid\n",
498 printf("Port %u RX timestamp value 0x%"PRIu64"\n",
499 (unsigned) pi, rx_tmst);
502 #define MAX_TX_TMST_WAIT_MICROSECS 1000 /**< 1 milli-second */
505 port_ieee1588_tx_timestamp_check(portid_t pi)
507 struct port_ieee1588_ops *ieee_ops;
511 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
513 while ((ieee_ops->tx_tmst_read(pi, &tx_tmst) < 0) &&
514 (wait_us < MAX_TX_TMST_WAIT_MICROSECS)) {
518 if (wait_us >= MAX_TX_TMST_WAIT_MICROSECS) {
519 printf("Port %u: TX timestamp registers not valid after"
520 "%u micro-seconds\n",
521 (unsigned) pi, (unsigned) MAX_TX_TMST_WAIT_MICROSECS);
524 printf("Port %u TX timestamp value 0x%"PRIu64" validated after "
525 "%u micro-second%s\n",
526 (unsigned) pi, tx_tmst, wait_us,
527 (wait_us == 1) ? "" : "s");
531 ieee1588_packet_fwd(struct fwd_stream *fs)
534 struct ether_hdr *eth_hdr;
535 struct ptpv2_msg *ptp_hdr;
539 * Receive 1 packet at a time.
541 if (rte_eth_rx_burst(fs->rx_port, fs->rx_queue, &mb, 1) == 0)
547 * Check that the received packet is a PTP packet that was detected
550 eth_hdr = (struct ether_hdr *)mb->pkt.data;
551 eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
552 if (! (mb->ol_flags & PKT_RX_IEEE1588_PTP)) {
553 if (eth_type == ETHER_TYPE_1588) {
554 printf("Port %u Received PTP packet not filtered"
556 (unsigned) fs->rx_port);
558 printf("Port %u Received non PTP packet type=0x%4x "
560 (unsigned) fs->rx_port, eth_type,
561 (unsigned) mb->pkt.pkt_len);
563 rte_pktmbuf_free(mb);
566 if (eth_type != ETHER_TYPE_1588) {
567 printf("Port %u Received NON PTP packet wrongly"
568 " detected by hardware\n",
569 (unsigned) fs->rx_port);
570 rte_pktmbuf_free(mb);
575 * Check that the received PTP packet is a PTP V2 packet of type
578 ptp_hdr = (struct ptpv2_msg *) ((char *) mb->pkt.data +
579 sizeof(struct ether_hdr));
580 if (ptp_hdr->version != 0x02) {
581 printf("Port %u Received PTP V2 Ethernet frame with wrong PTP"
582 " protocol version 0x%x (should be 0x02)\n",
583 (unsigned) fs->rx_port, ptp_hdr->version);
584 rte_pktmbuf_free(mb);
587 if (ptp_hdr->msg_id != PTP_SYNC_MESSAGE) {
588 printf("Port %u Received PTP V2 Ethernet frame with unexpected"
589 " messageID 0x%x (expected 0x0 - PTP_SYNC_MESSAGE)\n",
590 (unsigned) fs->rx_port, ptp_hdr->msg_id);
591 rte_pktmbuf_free(mb);
594 printf("Port %u IEEE1588 PTP V2 SYNC Message filtered by hardware\n",
595 (unsigned) fs->rx_port);
598 * Check that the received PTP packet has been timestamped by the
601 if (! (mb->ol_flags & PKT_RX_IEEE1588_TMST)) {
602 printf("Port %u Received PTP packet not timestamped"
604 (unsigned) fs->rx_port);
605 rte_pktmbuf_free(mb);
609 /* Check the RX timestamp */
610 port_ieee1588_rx_timestamp_check(fs->rx_port);
612 /* Forward PTP packet with hardware TX timestamp */
613 mb->ol_flags |= PKT_TX_IEEE1588_TMST;
615 if (rte_eth_tx_burst(fs->rx_port, fs->tx_queue, &mb, 1) == 0) {
616 printf("Port %u sent PTP packet dropped\n",
617 (unsigned) fs->rx_port);
618 fs->fwd_dropped += 1;
619 rte_pktmbuf_free(mb);
624 * Check the TX timestamp.
626 port_ieee1588_tx_timestamp_check(fs->rx_port);
630 port_ieee1588_fwd_begin(portid_t pi)
632 struct port_ieee1588_ops *ieee_ops;
634 if (strcmp(ports[pi].dev_info.driver_name, "rte_igb_pmd") == 0)
635 ieee_ops = &igbe_82576_ieee1588_ops;
637 ieee_ops = &ixgbe_82599_ieee1588_ops;
638 ports[pi].fwd_ctx = ieee_ops;
639 (ieee_ops->ieee1588_start)(pi);
643 port_ieee1588_fwd_end(portid_t pi)
645 struct port_ieee1588_ops *ieee_ops;
647 ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
648 (ieee_ops->ieee1588_stop)(pi);
651 struct fwd_engine ieee1588_fwd_engine = {
652 .fwd_mode_name = "ieee1588",
653 .port_fwd_begin = port_ieee1588_fwd_begin,
654 .port_fwd_end = port_ieee1588_fwd_end,
655 .packet_fwd = ieee1588_packet_fwd,