1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_ethdev.h"
7 #include "axgbe_rxtx.h"
11 #include <rte_mempool.h>
16 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue)
19 struct rte_mbuf **sw_ring;
22 sw_ring = rx_queue->sw_ring;
24 for (i = 0; i < rx_queue->nb_desc; i++) {
26 rte_pktmbuf_free(sw_ring[i]);
34 void axgbe_dev_rx_queue_release(void *rxq)
36 axgbe_rx_queue_release(rxq);
39 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
40 uint16_t nb_desc, unsigned int socket_id,
41 const struct rte_eth_rxconf *rx_conf,
42 struct rte_mempool *mp)
44 PMD_INIT_FUNC_TRACE();
46 const struct rte_memzone *dma;
47 struct axgbe_rx_queue *rxq;
48 uint32_t rx_desc = nb_desc;
49 struct axgbe_port *pdata = dev->data->dev_private;
52 * validate Rx descriptors count
53 * should be power of 2 and less than h/w supported
55 if ((!rte_is_power_of_2(rx_desc)) ||
56 rx_desc > pdata->rx_desc_count)
58 /* First allocate the rx queue data structure */
59 rxq = rte_zmalloc_socket("ethdev RX queue",
60 sizeof(struct axgbe_rx_queue),
61 RTE_CACHE_LINE_SIZE, socket_id);
63 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!");
71 rxq->queue_id = queue_idx;
72 rxq->port_id = dev->data->port_id;
73 rxq->nb_desc = rx_desc;
74 rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
75 (DMA_CH_INC * rxq->queue_id));
76 rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs +
78 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
79 rxq->crc_len = RTE_ETHER_CRC_LEN;
83 /* CRC strip in AXGBE supports per port not per queue */
84 pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0;
85 rxq->free_thresh = rx_conf->rx_free_thresh ?
86 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH;
87 if (rxq->free_thresh > rxq->nb_desc)
88 rxq->free_thresh = rxq->nb_desc >> 3;
90 /* Allocate RX ring hardware descriptors */
91 size = rxq->nb_desc * sizeof(union axgbe_rx_desc);
92 dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128,
95 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n");
96 axgbe_rx_queue_release(rxq);
99 rxq->ring_phys_addr = (uint64_t)dma->iova;
100 rxq->desc = (volatile union axgbe_rx_desc *)dma->addr;
101 memset((void *)rxq->desc, 0, size);
102 /* Allocate software ring */
103 size = rxq->nb_desc * sizeof(struct rte_mbuf *);
104 rxq->sw_ring = rte_zmalloc_socket("sw_ring", size,
108 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n");
109 axgbe_rx_queue_release(rxq);
112 dev->data->rx_queues[queue_idx] = rxq;
113 if (!pdata->rx_queues)
114 pdata->rx_queues = dev->data->rx_queues;
119 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata,
122 unsigned int rx_status;
123 unsigned long rx_timeout;
125 /* The Rx engine cannot be stopped if it is actively processing
126 * packets. Wait for the Rx queue to empty the Rx fifo. Don't
127 * wait forever though...
129 rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
132 while (time_before(rte_get_timer_cycles(), rx_timeout)) {
133 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
134 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
135 (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
141 if (!time_before(rte_get_timer_cycles(), rx_timeout))
143 "timed out waiting for Rx queue %u to empty\n",
147 void axgbe_dev_disable_rx(struct rte_eth_dev *dev)
149 struct axgbe_rx_queue *rxq;
150 struct axgbe_port *pdata = dev->data->dev_private;
154 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
155 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
156 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
157 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
159 /* Prepare for Rx DMA channel stop */
160 for (i = 0; i < dev->data->nb_rx_queues; i++) {
161 rxq = dev->data->rx_queues[i];
162 axgbe_prepare_rx_stop(pdata, i);
164 /* Disable each Rx queue */
165 AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
166 for (i = 0; i < dev->data->nb_rx_queues; i++) {
167 rxq = dev->data->rx_queues[i];
168 /* Disable Rx DMA channel */
169 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0);
173 void axgbe_dev_enable_rx(struct rte_eth_dev *dev)
175 struct axgbe_rx_queue *rxq;
176 struct axgbe_port *pdata = dev->data->dev_private;
178 unsigned int reg_val = 0;
180 for (i = 0; i < dev->data->nb_rx_queues; i++) {
181 rxq = dev->data->rx_queues[i];
182 /* Enable Rx DMA channel */
183 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1);
187 for (i = 0; i < pdata->rx_q_count; i++)
188 reg_val |= (0x02 << (i << 1));
189 AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
192 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
193 /* Frame is forwarded after stripping CRC to application*/
194 if (pdata->crc_strip_enable) {
195 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
196 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
198 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
201 /* Rx function one to one refresh */
203 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
206 PMD_INIT_FUNC_TRACE();
208 struct axgbe_rx_queue *rxq = rx_queue;
209 volatile union axgbe_rx_desc *desc;
210 uint64_t old_dirty = rxq->dirty;
211 struct rte_mbuf *mbuf, *tmbuf;
212 unsigned int err, etlt;
213 uint32_t error_status;
214 uint16_t idx, pidx, pkt_len;
217 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
218 while (nb_rx < nb_pkts) {
219 if (unlikely(idx == rxq->nb_desc))
222 desc = &rxq->desc[idx];
224 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
226 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
227 if (unlikely(!tmbuf)) {
228 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
230 (unsigned int)rxq->port_id,
231 (unsigned int)rxq->queue_id);
233 rxq->port_id].data->rx_mbuf_alloc_failed++;
234 rxq->rx_mbuf_alloc_failed++;
238 if (unlikely(pidx == rxq->nb_desc))
241 rte_prefetch0(rxq->sw_ring[pidx]);
242 if ((pidx & 0x3) == 0) {
243 rte_prefetch0(&rxq->desc[pidx]);
244 rte_prefetch0(&rxq->sw_ring[pidx]);
247 mbuf = rxq->sw_ring[idx];
248 /* Check for any errors and free mbuf*/
249 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
250 RX_NORMAL_DESC3, ES);
253 error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
254 if ((error_status != AXGBE_L3_CSUM_ERR) &&
255 (error_status != AXGBE_L4_CSUM_ERR)) {
257 rte_pktmbuf_free(mbuf);
261 if (rxq->pdata->rx_csum_enable) {
263 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
264 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
265 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
266 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD;
267 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
268 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
269 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
271 unlikely(error_status == AXGBE_L4_CSUM_ERR)) {
272 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
273 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
276 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
277 /* Get the RSS hash */
278 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
279 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
280 etlt = AXGMAC_GET_BITS_LE(desc->write.desc3,
281 RX_NORMAL_DESC3, ETLT);
282 offloads = rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads;
284 if (etlt == RX_CVLAN_TAG_PRESENT) {
285 mbuf->ol_flags |= PKT_RX_VLAN;
287 AXGMAC_GET_BITS_LE(desc->write.desc0,
288 RX_NORMAL_DESC0, OVT);
289 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
290 mbuf->ol_flags |= PKT_RX_VLAN_STRIPPED;
292 mbuf->ol_flags &= ~PKT_RX_VLAN_STRIPPED;
296 | PKT_RX_VLAN_STRIPPED);
300 /* Indicate if a Context Descriptor is next */
301 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA))
302 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP
303 | PKT_RX_IEEE1588_TMST;
304 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3,
308 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
310 mbuf->port = rxq->port_id;
311 mbuf->pkt_len = pkt_len;
312 mbuf->data_len = pkt_len;
313 rxq->bytes += pkt_len;
314 rx_pkts[nb_rx++] = mbuf;
317 rxq->sw_ring[idx++] = tmbuf;
319 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
320 memset((void *)(&desc->read.desc2), 0, 8);
321 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
325 if (rxq->dirty != old_dirty) {
327 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
328 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
329 low32_value(rxq->ring_phys_addr +
330 (idx * sizeof(union axgbe_rx_desc))));
337 uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
338 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
340 PMD_INIT_FUNC_TRACE();
342 struct axgbe_rx_queue *rxq = rx_queue;
343 volatile union axgbe_rx_desc *desc;
345 uint64_t old_dirty = rxq->dirty;
346 struct rte_mbuf *first_seg = NULL;
347 struct rte_mbuf *mbuf, *tmbuf;
348 unsigned int err, etlt;
349 uint32_t error_status;
350 uint16_t idx, pidx, data_len = 0, pkt_len = 0;
353 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
354 while (nb_rx < nb_pkts) {
357 if (unlikely(idx == rxq->nb_desc))
360 desc = &rxq->desc[idx];
362 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
365 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
366 if (unlikely(!tmbuf)) {
367 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
369 (unsigned int)rxq->port_id,
370 (unsigned int)rxq->queue_id);
371 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
376 if (unlikely(pidx == rxq->nb_desc))
379 rte_prefetch0(rxq->sw_ring[pidx]);
380 if ((pidx & 0x3) == 0) {
381 rte_prefetch0(&rxq->desc[pidx]);
382 rte_prefetch0(&rxq->sw_ring[pidx]);
385 mbuf = rxq->sw_ring[idx];
386 /* Check for any errors and free mbuf*/
387 err = AXGMAC_GET_BITS_LE(desc->write.desc3,
388 RX_NORMAL_DESC3, ES);
391 error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
392 if ((error_status != AXGBE_L3_CSUM_ERR)
393 && (error_status != AXGBE_L4_CSUM_ERR)) {
395 rte_pktmbuf_free(mbuf);
399 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
401 if (!AXGMAC_GET_BITS_LE(desc->write.desc3,
402 RX_NORMAL_DESC3, LD)) {
404 pkt_len = rxq->buf_size;
408 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3,
409 RX_NORMAL_DESC3, PL);
410 data_len = pkt_len - rxq->crc_len;
413 if (first_seg != NULL) {
414 if (rte_pktmbuf_chain(first_seg, mbuf) != 0)
415 rte_mempool_put(rxq->mb_pool,
421 /* Get the RSS hash */
422 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV))
423 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1);
424 etlt = AXGMAC_GET_BITS_LE(desc->write.desc3,
425 RX_NORMAL_DESC3, ETLT);
426 offloads = rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads;
428 if (etlt == RX_CVLAN_TAG_PRESENT) {
429 mbuf->ol_flags |= PKT_RX_VLAN;
431 AXGMAC_GET_BITS_LE(desc->write.desc0,
432 RX_NORMAL_DESC0, OVT);
433 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
434 mbuf->ol_flags |= PKT_RX_VLAN_STRIPPED;
436 mbuf->ol_flags &= ~PKT_RX_VLAN_STRIPPED;
439 ~(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
444 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
445 mbuf->data_len = data_len;
449 rxq->sw_ring[idx++] = tmbuf;
451 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
452 memset((void *)(&desc->read.desc2), 0, 8);
453 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
457 rte_pktmbuf_free(mbuf);
461 first_seg->pkt_len = pkt_len;
462 rxq->bytes += pkt_len;
465 first_seg->port = rxq->port_id;
466 if (rxq->pdata->rx_csum_enable) {
468 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
469 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
470 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) {
471 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD;
472 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
473 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
474 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
475 } else if (unlikely(error_status
476 == AXGBE_L4_CSUM_ERR)) {
477 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD;
478 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
482 rx_pkts[nb_rx++] = first_seg;
484 /* Setup receipt context for a new packet.*/
488 /* Save receive context.*/
491 if (rxq->dirty != old_dirty) {
493 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
494 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
495 low32_value(rxq->ring_phys_addr +
496 (idx * sizeof(union axgbe_rx_desc))));
502 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue)
505 struct rte_mbuf **sw_ring;
508 sw_ring = tx_queue->sw_ring;
510 for (i = 0; i < tx_queue->nb_desc; i++) {
512 rte_pktmbuf_free(sw_ring[i]);
520 void axgbe_dev_tx_queue_release(void *txq)
522 axgbe_tx_queue_release(txq);
525 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
526 uint16_t nb_desc, unsigned int socket_id,
527 const struct rte_eth_txconf *tx_conf)
529 PMD_INIT_FUNC_TRACE();
531 struct axgbe_port *pdata;
532 struct axgbe_tx_queue *txq;
534 const struct rte_memzone *tz;
538 pdata = dev->data->dev_private;
541 * validate tx descriptors count
542 * should be power of 2 and less than h/w supported
544 if ((!rte_is_power_of_2(tx_desc)) ||
545 tx_desc > pdata->tx_desc_count ||
546 tx_desc < AXGBE_MIN_RING_DESC)
549 /* First allocate the tx queue data structure */
550 txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue),
551 RTE_CACHE_LINE_SIZE);
555 offloads = tx_conf->offloads |
556 txq->pdata->eth_dev->data->dev_conf.txmode.offloads;
557 txq->nb_desc = tx_desc;
558 txq->free_thresh = tx_conf->tx_free_thresh ?
559 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH;
560 if (txq->free_thresh > txq->nb_desc)
561 txq->free_thresh = (txq->nb_desc >> 1);
562 txq->free_batch_cnt = txq->free_thresh;
564 /* In vector_tx path threshold should be multiple of queue_size*/
565 if (txq->nb_desc % txq->free_thresh != 0)
566 txq->vector_disable = 1;
569 txq->vector_disable = 1;
571 /* Allocate TX ring hardware descriptors */
572 tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc);
573 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
574 tsize, AXGBE_DESC_ALIGN, socket_id);
576 axgbe_tx_queue_release(txq);
579 memset(tz->addr, 0, tsize);
580 txq->ring_phys_addr = (uint64_t)tz->iova;
581 txq->desc = tz->addr;
582 txq->queue_id = queue_idx;
583 txq->port_id = dev->data->port_id;
584 txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
585 (DMA_CH_INC * txq->queue_id));
586 txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs +
590 txq->nb_desc_free = txq->nb_desc;
591 /* Allocate software ring */
592 tsize = txq->nb_desc * sizeof(struct rte_mbuf *);
593 txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize,
594 RTE_CACHE_LINE_SIZE);
596 axgbe_tx_queue_release(txq);
599 dev->data->tx_queues[queue_idx] = txq;
600 if (!pdata->tx_queues)
601 pdata->tx_queues = dev->data->tx_queues;
603 if (txq->vector_disable ||
604 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
605 dev->tx_pkt_burst = &axgbe_xmit_pkts;
608 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec;
610 dev->tx_pkt_burst = &axgbe_xmit_pkts;
616 int axgbe_dev_fw_version_get(struct rte_eth_dev *eth_dev,
617 char *fw_version, size_t fw_size)
619 struct axgbe_port *pdata;
620 struct axgbe_hw_features *hw_feat;
623 pdata = (struct axgbe_port *)eth_dev->data->dev_private;
624 hw_feat = &pdata->hw_feat;
626 if (fw_version == NULL)
629 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
630 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER),
631 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID),
632 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER));
636 ret += 1; /* add the size of '\0' */
638 if (fw_size < (size_t)ret)
644 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata,
647 unsigned int tx_status;
648 unsigned long tx_timeout;
650 /* The Tx engine cannot be stopped if it is actively processing
651 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
652 * wait forever though...
654 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
656 while (time_before(rte_get_timer_cycles(), tx_timeout)) {
657 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
658 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
659 (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
665 if (!time_before(rte_get_timer_cycles(), tx_timeout))
667 "timed out waiting for Tx queue %u to empty\n",
671 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata,
674 unsigned int tx_dsr, tx_pos, tx_qidx;
675 unsigned int tx_status;
676 unsigned long tx_timeout;
678 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
679 return axgbe_txq_prepare_tx_stop(pdata, queue);
681 /* Calculate the status register to read and the position within */
682 if (queue < DMA_DSRX_FIRST_QUEUE) {
684 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
686 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
688 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
689 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
693 /* The Tx engine cannot be stopped if it is actively processing
694 * descriptors. Wait for the Tx engine to enter the stopped or
695 * suspended state. Don't wait forever though...
697 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT *
699 while (time_before(rte_get_timer_cycles(), tx_timeout)) {
700 tx_status = AXGMAC_IOREAD(pdata, tx_dsr);
701 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
702 if ((tx_status == DMA_TPS_STOPPED) ||
703 (tx_status == DMA_TPS_SUSPENDED))
709 if (!time_before(rte_get_timer_cycles(), tx_timeout))
711 "timed out waiting for Tx DMA channel %u to stop\n",
715 void axgbe_dev_disable_tx(struct rte_eth_dev *dev)
717 struct axgbe_tx_queue *txq;
718 struct axgbe_port *pdata = dev->data->dev_private;
721 /* Prepare for stopping DMA channel */
722 for (i = 0; i < pdata->tx_q_count; i++) {
723 txq = dev->data->tx_queues[i];
724 axgbe_prepare_tx_stop(pdata, i);
727 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
728 /* Disable each Tx queue*/
729 for (i = 0; i < pdata->tx_q_count; i++)
730 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
732 /* Disable each Tx DMA channel */
733 for (i = 0; i < dev->data->nb_tx_queues; i++) {
734 txq = dev->data->tx_queues[i];
735 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0);
739 void axgbe_dev_enable_tx(struct rte_eth_dev *dev)
741 struct axgbe_tx_queue *txq;
742 struct axgbe_port *pdata = dev->data->dev_private;
745 for (i = 0; i < dev->data->nb_tx_queues; i++) {
746 txq = dev->data->tx_queues[i];
747 /* Enable Tx DMA channel */
748 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1);
751 for (i = 0; i < pdata->tx_q_count; i++)
752 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
755 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
758 /* Free Tx conformed mbufs */
759 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq)
761 volatile struct axgbe_tx_desc *desc;
764 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty);
765 while (txq->cur != txq->dirty) {
766 if (unlikely(idx == txq->nb_desc))
768 desc = &txq->desc[idx];
769 /* Check for ownership */
770 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
772 memset((void *)&desc->desc2, 0, 8);
774 rte_pktmbuf_free(txq->sw_ring[idx]);
775 txq->sw_ring[idx++] = NULL;
780 /* Tx Descriptor formation
781 * Considering each mbuf requires one desc
784 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
785 struct rte_mbuf *mbuf)
787 volatile struct axgbe_tx_desc *desc;
791 idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
792 desc = &txq->desc[idx];
794 /* Update buffer address and length */
795 desc->baddr = rte_mbuf_data_iova(mbuf);
796 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,
798 /* Total msg length to transmit */
799 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
801 /* Timestamp enablement check */
802 if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST)
803 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);
805 /* Mark it as First and Last Descriptor */
806 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);
807 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);
808 /* Mark it as a NORMAL descriptor */
809 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);
810 /* configure h/w Offload */
811 mask = mbuf->ol_flags & PKT_TX_L4_MASK;
812 if ((mask == PKT_TX_TCP_CKSUM) || (mask == PKT_TX_UDP_CKSUM))
813 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);
814 else if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
815 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);
818 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
819 /* Mark it as a CONTEXT descriptor */
820 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,
822 /* Set the VLAN tag */
823 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,
825 /* Indicate this descriptor contains the VLAN tag */
826 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,
828 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR,
829 TX_NORMAL_DESC2_VLAN_INSERT);
831 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 0x0);
836 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);
841 txq->sw_ring[idx] = mbuf;
842 /* Update current index*/
845 txq->bytes += mbuf->pkt_len;
850 /* Eal supported tx wrapper*/
852 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
855 PMD_INIT_FUNC_TRACE();
857 if (unlikely(nb_pkts == 0))
860 struct axgbe_tx_queue *txq;
861 uint16_t nb_desc_free;
862 uint16_t nb_pkt_sent = 0;
865 struct rte_mbuf *mbuf;
867 txq = (struct axgbe_tx_queue *)tx_queue;
868 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
870 if (unlikely(nb_desc_free <= txq->free_thresh)) {
871 axgbe_xmit_cleanup(txq);
872 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
873 if (unlikely(nb_desc_free == 0))
876 nb_pkts = RTE_MIN(nb_desc_free, nb_pkts);
879 if (axgbe_xmit_hw(txq, mbuf))
884 /* Sync read and write */
886 idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
887 tail_addr = low32_value(txq->ring_phys_addr +
888 idx * sizeof(struct axgbe_tx_desc));
889 /* Update tail reg with next immediate address to kick Tx DMA channel*/
890 AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr);
891 txq->pkts += nb_pkt_sent;
895 void axgbe_dev_clear_queues(struct rte_eth_dev *dev)
897 PMD_INIT_FUNC_TRACE();
899 struct axgbe_rx_queue *rxq;
900 struct axgbe_tx_queue *txq;
902 for (i = 0; i < dev->data->nb_rx_queues; i++) {
903 rxq = dev->data->rx_queues[i];
906 axgbe_rx_queue_release(rxq);
907 dev->data->rx_queues[i] = NULL;
911 for (i = 0; i < dev->data->nb_tx_queues; i++) {
912 txq = dev->data->tx_queues[i];
915 axgbe_tx_queue_release(txq);
916 dev->data->tx_queues[i] = NULL;
922 axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
924 struct axgbe_rx_queue *rxq = rx_queue;
925 volatile union axgbe_rx_desc *desc;
929 if (unlikely(offset >= rxq->nb_desc))
932 if (offset >= rxq->nb_desc - rxq->dirty)
933 return RTE_ETH_RX_DESC_UNAVAIL;
935 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
936 desc = &rxq->desc[idx + offset];
938 if (!AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
939 return RTE_ETH_RX_DESC_DONE;
941 return RTE_ETH_RX_DESC_AVAIL;
945 axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
947 struct axgbe_tx_queue *txq = tx_queue;
948 volatile struct axgbe_tx_desc *desc;
952 if (unlikely(offset >= txq->nb_desc))
955 if (offset >= txq->nb_desc - txq->dirty)
956 return RTE_ETH_TX_DESC_UNAVAIL;
958 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty + txq->free_batch_cnt - 1);
959 desc = &txq->desc[idx + offset];
961 if (!AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
962 return RTE_ETH_TX_DESC_DONE;
964 return RTE_ETH_TX_DESC_FULL;