1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_check.h"
13 #include "efx_phy_ids.h"
19 #define EFX_STATIC_ASSERT(_cond) \
20 ((void)sizeof (char[(_cond) ? 1 : -1]))
22 #define EFX_ARRAY_SIZE(_array) \
23 (sizeof (_array) / sizeof ((_array)[0]))
25 #define EFX_FIELD_OFFSET(_type, _field) \
26 ((size_t)&(((_type *)0)->_field))
28 /* The macro expands divider twice */
29 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
33 typedef __success(return == 0) int efx_rc_t;
38 typedef enum efx_family_e {
40 EFX_FAMILY_FALCON, /* Obsolete and not supported */
42 EFX_FAMILY_HUNTINGTON,
48 extern __checkReturn efx_rc_t
52 __out efx_family_t *efp,
53 __out unsigned int *membarp);
56 #define EFX_PCI_VENID_SFC 0x1924
58 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
60 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
61 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
62 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
64 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
65 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
66 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
68 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
69 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
71 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
72 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
73 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
75 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
76 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
77 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
80 #define EFX_MEM_BAR_SIENA 2
82 #define EFX_MEM_BAR_HUNTINGTON_PF 2
83 #define EFX_MEM_BAR_HUNTINGTON_VF 0
85 #define EFX_MEM_BAR_MEDFORD_PF 2
86 #define EFX_MEM_BAR_MEDFORD_VF 0
88 #define EFX_MEM_BAR_MEDFORD2 0
109 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
110 extern __checkReturn uint32_t
112 __in uint32_t crc_init,
113 __in_ecount(length) uint8_t const *input,
117 /* Type prototypes */
119 typedef struct efx_rxq_s efx_rxq_t;
123 typedef struct efx_nic_s efx_nic_t;
125 extern __checkReturn efx_rc_t
127 __in efx_family_t family,
128 __in efsys_identifier_t *esip,
129 __in efsys_bar_t *esbp,
130 __in efsys_lock_t *eslp,
131 __deref_out efx_nic_t **enpp);
133 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
134 typedef enum efx_fw_variant_e {
135 EFX_FW_VARIANT_FULL_FEATURED,
136 EFX_FW_VARIANT_LOW_LATENCY,
137 EFX_FW_VARIANT_PACKED_STREAM,
138 EFX_FW_VARIANT_HIGH_TX_RATE,
139 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
140 EFX_FW_VARIANT_RULES_ENGINE,
142 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
145 extern __checkReturn efx_rc_t
148 __in efx_fw_variant_t efv);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
156 __in efx_nic_t *enp);
158 extern __checkReturn boolean_t
159 efx_nic_hw_unavailable(
160 __in efx_nic_t *enp);
163 efx_nic_set_hw_unavailable(
164 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
169 efx_nic_register_test(
170 __in efx_nic_t *enp);
172 #endif /* EFSYS_OPT_DIAG */
176 __in efx_nic_t *enp);
180 __in efx_nic_t *enp);
184 __in efx_nic_t *enp);
186 #define EFX_PCIE_LINK_SPEED_GEN1 1
187 #define EFX_PCIE_LINK_SPEED_GEN2 2
188 #define EFX_PCIE_LINK_SPEED_GEN3 3
190 typedef enum efx_pcie_link_performance_e {
191 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
192 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
193 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
194 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
195 } efx_pcie_link_performance_t;
197 extern __checkReturn efx_rc_t
198 efx_nic_calculate_pcie_link_bandwidth(
199 __in uint32_t pcie_link_width,
200 __in uint32_t pcie_link_gen,
201 __out uint32_t *bandwidth_mbpsp);
203 extern __checkReturn efx_rc_t
204 efx_nic_check_pcie_link_speed(
206 __in uint32_t pcie_link_width,
207 __in uint32_t pcie_link_gen,
208 __out efx_pcie_link_performance_t *resultp);
212 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
213 /* Huntington and Medford require MCDIv2 commands */
214 #define WITH_MCDI_V2 1
217 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
219 typedef enum efx_mcdi_exception_e {
220 EFX_MCDI_EXCEPTION_MC_REBOOT,
221 EFX_MCDI_EXCEPTION_MC_BADASSERT,
222 } efx_mcdi_exception_t;
224 #if EFSYS_OPT_MCDI_LOGGING
225 typedef enum efx_log_msg_e {
227 EFX_LOG_MCDI_REQUEST,
228 EFX_LOG_MCDI_RESPONSE,
230 #endif /* EFSYS_OPT_MCDI_LOGGING */
232 typedef struct efx_mcdi_transport_s {
234 efsys_mem_t *emt_dma_mem;
235 void (*emt_execute)(void *, efx_mcdi_req_t *);
236 void (*emt_ev_cpl)(void *);
237 void (*emt_exception)(void *, efx_mcdi_exception_t);
238 #if EFSYS_OPT_MCDI_LOGGING
239 void (*emt_logger)(void *, efx_log_msg_t,
240 void *, size_t, void *, size_t);
241 #endif /* EFSYS_OPT_MCDI_LOGGING */
242 #if EFSYS_OPT_MCDI_PROXY_AUTH
243 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
244 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
245 } efx_mcdi_transport_t;
247 extern __checkReturn efx_rc_t
250 __in const efx_mcdi_transport_t *mtp);
252 extern __checkReturn efx_rc_t
254 __in efx_nic_t *enp);
258 __in efx_nic_t *enp);
261 efx_mcdi_get_timeout(
263 __in efx_mcdi_req_t *emrp,
264 __out uint32_t *usec_timeoutp);
267 efx_mcdi_request_start(
269 __in efx_mcdi_req_t *emrp,
270 __in boolean_t ev_cpl);
272 extern __checkReturn boolean_t
273 efx_mcdi_request_poll(
274 __in efx_nic_t *enp);
276 extern __checkReturn boolean_t
277 efx_mcdi_request_abort(
278 __in efx_nic_t *enp);
282 __in efx_nic_t *enp);
284 #endif /* EFSYS_OPT_MCDI */
288 #define EFX_NINTR_SIENA 1024
290 typedef enum efx_intr_type_e {
291 EFX_INTR_INVALID = 0,
297 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
299 extern __checkReturn efx_rc_t
302 __in efx_intr_type_t type,
303 __in efsys_mem_t *esmp);
307 __in efx_nic_t *enp);
311 __in efx_nic_t *enp);
314 efx_intr_disable_unlocked(
315 __in efx_nic_t *enp);
317 #define EFX_INTR_NEVQS 32
319 extern __checkReturn efx_rc_t
322 __in unsigned int level);
325 efx_intr_status_line(
327 __out boolean_t *fatalp,
328 __out uint32_t *maskp);
331 efx_intr_status_message(
333 __in unsigned int message,
334 __out boolean_t *fatalp);
338 __in efx_nic_t *enp);
342 __in efx_nic_t *enp);
346 #if EFSYS_OPT_MAC_STATS
348 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
349 typedef enum efx_mac_stat_e {
352 EFX_MAC_RX_UNICST_PKTS,
353 EFX_MAC_RX_MULTICST_PKTS,
354 EFX_MAC_RX_BRDCST_PKTS,
355 EFX_MAC_RX_PAUSE_PKTS,
356 EFX_MAC_RX_LE_64_PKTS,
357 EFX_MAC_RX_65_TO_127_PKTS,
358 EFX_MAC_RX_128_TO_255_PKTS,
359 EFX_MAC_RX_256_TO_511_PKTS,
360 EFX_MAC_RX_512_TO_1023_PKTS,
361 EFX_MAC_RX_1024_TO_15XX_PKTS,
362 EFX_MAC_RX_GE_15XX_PKTS,
364 EFX_MAC_RX_FCS_ERRORS,
365 EFX_MAC_RX_DROP_EVENTS,
366 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
367 EFX_MAC_RX_SYMBOL_ERRORS,
368 EFX_MAC_RX_ALIGN_ERRORS,
369 EFX_MAC_RX_INTERNAL_ERRORS,
370 EFX_MAC_RX_JABBER_PKTS,
371 EFX_MAC_RX_LANE0_CHAR_ERR,
372 EFX_MAC_RX_LANE1_CHAR_ERR,
373 EFX_MAC_RX_LANE2_CHAR_ERR,
374 EFX_MAC_RX_LANE3_CHAR_ERR,
375 EFX_MAC_RX_LANE0_DISP_ERR,
376 EFX_MAC_RX_LANE1_DISP_ERR,
377 EFX_MAC_RX_LANE2_DISP_ERR,
378 EFX_MAC_RX_LANE3_DISP_ERR,
379 EFX_MAC_RX_MATCH_FAULT,
380 EFX_MAC_RX_NODESC_DROP_CNT,
383 EFX_MAC_TX_UNICST_PKTS,
384 EFX_MAC_TX_MULTICST_PKTS,
385 EFX_MAC_TX_BRDCST_PKTS,
386 EFX_MAC_TX_PAUSE_PKTS,
387 EFX_MAC_TX_LE_64_PKTS,
388 EFX_MAC_TX_65_TO_127_PKTS,
389 EFX_MAC_TX_128_TO_255_PKTS,
390 EFX_MAC_TX_256_TO_511_PKTS,
391 EFX_MAC_TX_512_TO_1023_PKTS,
392 EFX_MAC_TX_1024_TO_15XX_PKTS,
393 EFX_MAC_TX_GE_15XX_PKTS,
395 EFX_MAC_TX_SGL_COL_PKTS,
396 EFX_MAC_TX_MULT_COL_PKTS,
397 EFX_MAC_TX_EX_COL_PKTS,
398 EFX_MAC_TX_LATE_COL_PKTS,
400 EFX_MAC_TX_EX_DEF_PKTS,
401 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
402 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
403 EFX_MAC_PM_TRUNC_VFIFO_FULL,
404 EFX_MAC_PM_DISCARD_VFIFO_FULL,
405 EFX_MAC_PM_TRUNC_QBB,
406 EFX_MAC_PM_DISCARD_QBB,
407 EFX_MAC_PM_DISCARD_MAPPING,
408 EFX_MAC_RXDP_Q_DISABLED_PKTS,
409 EFX_MAC_RXDP_DI_DROPPED_PKTS,
410 EFX_MAC_RXDP_STREAMING_PKTS,
411 EFX_MAC_RXDP_HLB_FETCH,
412 EFX_MAC_RXDP_HLB_WAIT,
413 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
414 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
415 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
416 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
417 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
418 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
419 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
420 EFX_MAC_VADAPTER_RX_BAD_BYTES,
421 EFX_MAC_VADAPTER_RX_OVERFLOW,
422 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
423 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
424 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
425 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
426 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
427 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
428 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
429 EFX_MAC_VADAPTER_TX_BAD_BYTES,
430 EFX_MAC_VADAPTER_TX_OVERFLOW,
431 EFX_MAC_FEC_UNCORRECTED_ERRORS,
432 EFX_MAC_FEC_CORRECTED_ERRORS,
433 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
434 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
435 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
436 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
437 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
438 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
439 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
440 EFX_MAC_CTPIO_OVERFLOW_FAIL,
441 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
442 EFX_MAC_CTPIO_TIMEOUT_FAIL,
443 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
444 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
445 EFX_MAC_CTPIO_INVALID_WR_FAIL,
446 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
447 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
448 EFX_MAC_CTPIO_RUNT_FALLBACK,
449 EFX_MAC_CTPIO_SUCCESS,
450 EFX_MAC_CTPIO_FALLBACK,
451 EFX_MAC_CTPIO_POISON,
453 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
454 EFX_MAC_RXDP_HLB_IDLE,
455 EFX_MAC_RXDP_HLB_TIMEOUT,
459 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
461 #endif /* EFSYS_OPT_MAC_STATS */
463 typedef enum efx_link_mode_e {
464 EFX_LINK_UNKNOWN = 0,
480 #define EFX_MAC_ADDR_LEN 6
482 #define EFX_VNI_OR_VSID_LEN 3
484 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
486 #define EFX_MAC_MULTICAST_LIST_MAX 256
488 #define EFX_MAC_SDU_MAX 9202
490 #define EFX_MAC_PDU_ADJUSTMENT \
494 + /* bug16011 */ 16) \
496 #define EFX_MAC_PDU(_sdu) \
497 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
500 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
501 * the SDU rounded up slightly.
503 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
505 #define EFX_MAC_PDU_MIN 60
506 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
508 extern __checkReturn efx_rc_t
513 extern __checkReturn efx_rc_t
518 extern __checkReturn efx_rc_t
523 extern __checkReturn efx_rc_t
526 __in boolean_t all_unicst,
527 __in boolean_t mulcst,
528 __in boolean_t all_mulcst,
529 __in boolean_t brdcst);
531 extern __checkReturn efx_rc_t
532 efx_mac_multicast_list_set(
534 __in_ecount(6*count) uint8_t const *addrs,
537 extern __checkReturn efx_rc_t
538 efx_mac_filter_default_rxq_set(
541 __in boolean_t using_rss);
544 efx_mac_filter_default_rxq_clear(
545 __in efx_nic_t *enp);
547 extern __checkReturn efx_rc_t
550 __in boolean_t enabled);
552 extern __checkReturn efx_rc_t
555 __out boolean_t *mac_upp);
557 #define EFX_FCNTL_RESPOND 0x00000001
558 #define EFX_FCNTL_GENERATE 0x00000002
560 extern __checkReturn efx_rc_t
563 __in unsigned int fcntl,
564 __in boolean_t autoneg);
569 __out unsigned int *fcntl_wantedp,
570 __out unsigned int *fcntl_linkp);
573 #if EFSYS_OPT_MAC_STATS
577 extern __checkReturn const char *
580 __in unsigned int id);
582 #endif /* EFSYS_OPT_NAMES */
584 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
586 #define EFX_MAC_STATS_MASK_NPAGES \
587 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
588 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
591 * Get mask of MAC statistics supported by the hardware.
593 * If mask_size is insufficient to return the mask, EINVAL error is
594 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
595 * (which is sizeof (uint32_t)) is sufficient.
597 extern __checkReturn efx_rc_t
598 efx_mac_stats_get_mask(
600 __out_bcount(mask_size) uint32_t *maskp,
601 __in size_t mask_size);
603 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
604 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
605 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
608 extern __checkReturn efx_rc_t
610 __in efx_nic_t *enp);
613 * Upload mac statistics supported by the hardware into the given buffer.
615 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
616 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
618 * The hardware will only DMA statistics that it understands (of course).
619 * Drivers should not make any assumptions about which statistics are
620 * supported, especially when the statistics are generated by firmware.
622 * Thus, drivers should zero this buffer before use, so that not-understood
623 * statistics read back as zero.
625 extern __checkReturn efx_rc_t
626 efx_mac_stats_upload(
628 __in efsys_mem_t *esmp);
630 extern __checkReturn efx_rc_t
631 efx_mac_stats_periodic(
633 __in efsys_mem_t *esmp,
634 __in uint16_t period_ms,
635 __in boolean_t events);
637 extern __checkReturn efx_rc_t
638 efx_mac_stats_update(
640 __in efsys_mem_t *esmp,
641 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
642 __inout_opt uint32_t *generationp);
644 #endif /* EFSYS_OPT_MAC_STATS */
648 typedef enum efx_mon_type_e {
660 __in efx_nic_t *enp);
662 #endif /* EFSYS_OPT_NAMES */
664 extern __checkReturn efx_rc_t
666 __in efx_nic_t *enp);
668 #if EFSYS_OPT_MON_STATS
670 #define EFX_MON_STATS_PAGE_SIZE 0x100
671 #define EFX_MON_MASK_ELEMENT_SIZE 32
673 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
674 typedef enum efx_mon_stat_e {
675 EFX_MON_STAT_CONTROLLER_TEMP,
676 EFX_MON_STAT_PHY_COMMON_TEMP,
677 EFX_MON_STAT_CONTROLLER_COOLING,
678 EFX_MON_STAT_PHY0_TEMP,
679 EFX_MON_STAT_PHY0_COOLING,
680 EFX_MON_STAT_PHY1_TEMP,
681 EFX_MON_STAT_PHY1_COOLING,
687 EFX_MON_STAT_IN_12V0,
688 EFX_MON_STAT_IN_1V2A,
689 EFX_MON_STAT_IN_VREF,
690 EFX_MON_STAT_OUT_VAOE,
691 EFX_MON_STAT_AOE_TEMP,
692 EFX_MON_STAT_PSU_AOE_TEMP,
693 EFX_MON_STAT_PSU_TEMP,
699 EFX_MON_STAT_IN_VAOE,
700 EFX_MON_STAT_OUT_IAOE,
701 EFX_MON_STAT_IN_IAOE,
702 EFX_MON_STAT_NIC_POWER,
704 EFX_MON_STAT_IN_I0V9,
705 EFX_MON_STAT_IN_I1V2,
706 EFX_MON_STAT_IN_0V9_ADC,
707 EFX_MON_STAT_CONTROLLER_2_TEMP,
708 EFX_MON_STAT_VREG_INTERNAL_TEMP,
709 EFX_MON_STAT_VREG_0V9_TEMP,
710 EFX_MON_STAT_VREG_1V2_TEMP,
711 EFX_MON_STAT_CONTROLLER_VPTAT,
712 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
713 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
714 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
715 EFX_MON_STAT_AMBIENT_TEMP,
716 EFX_MON_STAT_AIRFLOW,
717 EFX_MON_STAT_VDD08D_VSS08D_CSR,
718 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
719 EFX_MON_STAT_HOTPOINT_TEMP,
720 EFX_MON_STAT_PHY_POWER_PORT0,
721 EFX_MON_STAT_PHY_POWER_PORT1,
722 EFX_MON_STAT_MUM_VCC,
723 EFX_MON_STAT_IN_0V9_A,
724 EFX_MON_STAT_IN_I0V9_A,
725 EFX_MON_STAT_VREG_0V9_A_TEMP,
726 EFX_MON_STAT_IN_0V9_B,
727 EFX_MON_STAT_IN_I0V9_B,
728 EFX_MON_STAT_VREG_0V9_B_TEMP,
729 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
730 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
731 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
732 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
733 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
734 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
735 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
736 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
737 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
738 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
739 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
740 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
741 EFX_MON_STAT_SODIMM_VOUT,
742 EFX_MON_STAT_SODIMM_0_TEMP,
743 EFX_MON_STAT_SODIMM_1_TEMP,
744 EFX_MON_STAT_PHY0_VCC,
745 EFX_MON_STAT_PHY1_VCC,
746 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
747 EFX_MON_STAT_BOARD_FRONT_TEMP,
748 EFX_MON_STAT_BOARD_BACK_TEMP,
749 EFX_MON_STAT_IN_I1V8,
750 EFX_MON_STAT_IN_I2V5,
751 EFX_MON_STAT_IN_I3V3,
752 EFX_MON_STAT_IN_I12V0,
754 EFX_MON_STAT_IN_I1V3,
758 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
760 typedef enum efx_mon_stat_state_e {
761 EFX_MON_STAT_STATE_OK = 0,
762 EFX_MON_STAT_STATE_WARNING = 1,
763 EFX_MON_STAT_STATE_FATAL = 2,
764 EFX_MON_STAT_STATE_BROKEN = 3,
765 EFX_MON_STAT_STATE_NO_READING = 4,
766 } efx_mon_stat_state_t;
768 typedef enum efx_mon_stat_unit_e {
769 EFX_MON_STAT_UNIT_UNKNOWN = 0,
770 EFX_MON_STAT_UNIT_BOOL,
771 EFX_MON_STAT_UNIT_TEMP_C,
772 EFX_MON_STAT_UNIT_VOLTAGE_MV,
773 EFX_MON_STAT_UNIT_CURRENT_MA,
774 EFX_MON_STAT_UNIT_POWER_W,
775 EFX_MON_STAT_UNIT_RPM,
777 } efx_mon_stat_unit_t;
779 typedef struct efx_mon_stat_value_s {
781 efx_mon_stat_state_t emsv_state;
782 efx_mon_stat_unit_t emsv_unit;
783 } efx_mon_stat_value_t;
785 typedef struct efx_mon_limit_value_s {
786 uint16_t emlv_warning_min;
787 uint16_t emlv_warning_max;
788 uint16_t emlv_fatal_min;
789 uint16_t emlv_fatal_max;
790 } efx_mon_stat_limits_t;
792 typedef enum efx_mon_stat_portmask_e {
793 EFX_MON_STAT_PORTMAP_NONE = 0,
794 EFX_MON_STAT_PORTMAP_PORT0 = 1,
795 EFX_MON_STAT_PORTMAP_PORT1 = 2,
796 EFX_MON_STAT_PORTMAP_PORT2 = 3,
797 EFX_MON_STAT_PORTMAP_PORT3 = 4,
798 EFX_MON_STAT_PORTMAP_ALL = (-1),
799 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
800 } efx_mon_stat_portmask_t;
807 __in efx_mon_stat_t id);
810 efx_mon_stat_description(
812 __in efx_mon_stat_t id);
814 #endif /* EFSYS_OPT_NAMES */
816 extern __checkReturn boolean_t
817 efx_mon_mcdi_to_efx_stat(
819 __out efx_mon_stat_t *statp);
821 extern __checkReturn boolean_t
822 efx_mon_get_stat_unit(
823 __in efx_mon_stat_t stat,
824 __out efx_mon_stat_unit_t *unitp);
826 extern __checkReturn boolean_t
827 efx_mon_get_stat_portmap(
828 __in efx_mon_stat_t stat,
829 __out efx_mon_stat_portmask_t *maskp);
831 extern __checkReturn efx_rc_t
832 efx_mon_stats_update(
834 __in efsys_mem_t *esmp,
835 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
837 extern __checkReturn efx_rc_t
838 efx_mon_limits_update(
840 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
842 #endif /* EFSYS_OPT_MON_STATS */
846 __in efx_nic_t *enp);
850 extern __checkReturn efx_rc_t
852 __in efx_nic_t *enp);
854 #if EFSYS_OPT_PHY_LED_CONTROL
856 typedef enum efx_phy_led_mode_e {
857 EFX_PHY_LED_DEFAULT = 0,
862 } efx_phy_led_mode_t;
864 extern __checkReturn efx_rc_t
867 __in efx_phy_led_mode_t mode);
869 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
871 extern __checkReturn efx_rc_t
873 __in efx_nic_t *enp);
875 #if EFSYS_OPT_LOOPBACK
877 typedef enum efx_loopback_type_e {
878 EFX_LOOPBACK_OFF = 0,
879 EFX_LOOPBACK_DATA = 1,
880 EFX_LOOPBACK_GMAC = 2,
881 EFX_LOOPBACK_XGMII = 3,
882 EFX_LOOPBACK_XGXS = 4,
883 EFX_LOOPBACK_XAUI = 5,
884 EFX_LOOPBACK_GMII = 6,
885 EFX_LOOPBACK_SGMII = 7,
886 EFX_LOOPBACK_XGBR = 8,
887 EFX_LOOPBACK_XFI = 9,
888 EFX_LOOPBACK_XAUI_FAR = 10,
889 EFX_LOOPBACK_GMII_FAR = 11,
890 EFX_LOOPBACK_SGMII_FAR = 12,
891 EFX_LOOPBACK_XFI_FAR = 13,
892 EFX_LOOPBACK_GPHY = 14,
893 EFX_LOOPBACK_PHY_XS = 15,
894 EFX_LOOPBACK_PCS = 16,
895 EFX_LOOPBACK_PMA_PMD = 17,
896 EFX_LOOPBACK_XPORT = 18,
897 EFX_LOOPBACK_XGMII_WS = 19,
898 EFX_LOOPBACK_XAUI_WS = 20,
899 EFX_LOOPBACK_XAUI_WS_FAR = 21,
900 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
901 EFX_LOOPBACK_GMII_WS = 23,
902 EFX_LOOPBACK_XFI_WS = 24,
903 EFX_LOOPBACK_XFI_WS_FAR = 25,
904 EFX_LOOPBACK_PHYXS_WS = 26,
905 EFX_LOOPBACK_PMA_INT = 27,
906 EFX_LOOPBACK_SD_NEAR = 28,
907 EFX_LOOPBACK_SD_FAR = 29,
908 EFX_LOOPBACK_PMA_INT_WS = 30,
909 EFX_LOOPBACK_SD_FEP2_WS = 31,
910 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
911 EFX_LOOPBACK_SD_FEP_WS = 33,
912 EFX_LOOPBACK_SD_FES_WS = 34,
913 EFX_LOOPBACK_AOE_INT_NEAR = 35,
914 EFX_LOOPBACK_DATA_WS = 36,
915 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
917 } efx_loopback_type_t;
919 typedef enum efx_loopback_kind_e {
920 EFX_LOOPBACK_KIND_OFF = 0,
921 EFX_LOOPBACK_KIND_ALL,
922 EFX_LOOPBACK_KIND_MAC,
923 EFX_LOOPBACK_KIND_PHY,
925 } efx_loopback_kind_t;
929 __in efx_loopback_kind_t loopback_kind,
930 __out efx_qword_t *maskp);
932 extern __checkReturn efx_rc_t
933 efx_port_loopback_set(
935 __in efx_link_mode_t link_mode,
936 __in efx_loopback_type_t type);
940 extern __checkReturn const char *
941 efx_loopback_type_name(
943 __in efx_loopback_type_t type);
945 #endif /* EFSYS_OPT_NAMES */
947 #endif /* EFSYS_OPT_LOOPBACK */
949 extern __checkReturn efx_rc_t
952 __out_opt efx_link_mode_t *link_modep);
956 __in efx_nic_t *enp);
958 typedef enum efx_phy_cap_type_e {
959 EFX_PHY_CAP_INVALID = 0,
966 EFX_PHY_CAP_10000FDX,
970 EFX_PHY_CAP_40000FDX,
972 EFX_PHY_CAP_100000FDX,
973 EFX_PHY_CAP_25000FDX,
974 EFX_PHY_CAP_50000FDX,
975 EFX_PHY_CAP_BASER_FEC,
976 EFX_PHY_CAP_BASER_FEC_REQUESTED,
978 EFX_PHY_CAP_RS_FEC_REQUESTED,
979 EFX_PHY_CAP_25G_BASER_FEC,
980 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
982 } efx_phy_cap_type_t;
985 #define EFX_PHY_CAP_CURRENT 0x00000000
986 #define EFX_PHY_CAP_DEFAULT 0x00000001
987 #define EFX_PHY_CAP_PERM 0x00000002
993 __out uint32_t *maskp);
995 extern __checkReturn efx_rc_t
1002 __in efx_nic_t *enp,
1003 __out uint32_t *maskp);
1005 extern __checkReturn efx_rc_t
1007 __in efx_nic_t *enp,
1008 __out uint32_t *ouip);
1010 typedef enum efx_phy_media_type_e {
1011 EFX_PHY_MEDIA_INVALID = 0,
1016 EFX_PHY_MEDIA_SFP_PLUS,
1017 EFX_PHY_MEDIA_BASE_T,
1018 EFX_PHY_MEDIA_QSFP_PLUS,
1019 EFX_PHY_MEDIA_NTYPES
1020 } efx_phy_media_type_t;
1023 * Get the type of medium currently used. If the board has ports for
1024 * modules, a module is present, and we recognise the media type of
1025 * the module, then this will be the media type of the module.
1026 * Otherwise it will be the media type of the port.
1029 efx_phy_media_type_get(
1030 __in efx_nic_t *enp,
1031 __out efx_phy_media_type_t *typep);
1034 * 2-wire device address of the base information in accordance with SFF-8472
1035 * Diagnostic Monitoring Interface for Optical Transceivers section
1036 * 4 Memory Organization.
1038 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1041 * 2-wire device address of the digital diagnostics monitoring interface
1042 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1043 * Transceivers section 4 Memory Organization.
1045 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1048 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1049 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1052 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1055 * Maximum accessible data offset for PHY module information.
1057 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1060 extern __checkReturn efx_rc_t
1061 efx_phy_module_get_info(
1062 __in efx_nic_t *enp,
1063 __in uint8_t dev_addr,
1066 __out_bcount(len) uint8_t *data);
1068 #if EFSYS_OPT_PHY_STATS
1070 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1071 typedef enum efx_phy_stat_e {
1073 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1074 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1075 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1076 EFX_PHY_STAT_PMA_PMD_REV_A,
1077 EFX_PHY_STAT_PMA_PMD_REV_B,
1078 EFX_PHY_STAT_PMA_PMD_REV_C,
1079 EFX_PHY_STAT_PMA_PMD_REV_D,
1080 EFX_PHY_STAT_PCS_LINK_UP,
1081 EFX_PHY_STAT_PCS_RX_FAULT,
1082 EFX_PHY_STAT_PCS_TX_FAULT,
1083 EFX_PHY_STAT_PCS_BER,
1084 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1085 EFX_PHY_STAT_PHY_XS_LINK_UP,
1086 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1087 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1088 EFX_PHY_STAT_PHY_XS_ALIGN,
1089 EFX_PHY_STAT_PHY_XS_SYNC_A,
1090 EFX_PHY_STAT_PHY_XS_SYNC_B,
1091 EFX_PHY_STAT_PHY_XS_SYNC_C,
1092 EFX_PHY_STAT_PHY_XS_SYNC_D,
1093 EFX_PHY_STAT_AN_LINK_UP,
1094 EFX_PHY_STAT_AN_MASTER,
1095 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1096 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1097 EFX_PHY_STAT_CL22EXT_LINK_UP,
1102 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1103 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1104 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1105 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1106 EFX_PHY_STAT_AN_COMPLETE,
1107 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1108 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1109 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1110 EFX_PHY_STAT_PCS_FW_VERSION_0,
1111 EFX_PHY_STAT_PCS_FW_VERSION_1,
1112 EFX_PHY_STAT_PCS_FW_VERSION_2,
1113 EFX_PHY_STAT_PCS_FW_VERSION_3,
1114 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1115 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1116 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1117 EFX_PHY_STAT_PCS_OP_MODE,
1121 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1127 __in efx_nic_t *enp,
1128 __in efx_phy_stat_t stat);
1130 #endif /* EFSYS_OPT_NAMES */
1132 #define EFX_PHY_STATS_SIZE 0x100
1134 extern __checkReturn efx_rc_t
1135 efx_phy_stats_update(
1136 __in efx_nic_t *enp,
1137 __in efsys_mem_t *esmp,
1138 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1140 #endif /* EFSYS_OPT_PHY_STATS */
1145 typedef enum efx_bist_type_e {
1146 EFX_BIST_TYPE_UNKNOWN,
1147 EFX_BIST_TYPE_PHY_NORMAL,
1148 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1149 EFX_BIST_TYPE_PHY_CABLE_LONG,
1150 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1151 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1152 EFX_BIST_TYPE_REG, /* Test the register memories */
1153 EFX_BIST_TYPE_NTYPES,
1156 typedef enum efx_bist_result_e {
1157 EFX_BIST_RESULT_UNKNOWN,
1158 EFX_BIST_RESULT_RUNNING,
1159 EFX_BIST_RESULT_PASSED,
1160 EFX_BIST_RESULT_FAILED,
1161 } efx_bist_result_t;
1163 typedef enum efx_phy_cable_status_e {
1164 EFX_PHY_CABLE_STATUS_OK,
1165 EFX_PHY_CABLE_STATUS_INVALID,
1166 EFX_PHY_CABLE_STATUS_OPEN,
1167 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1168 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1169 EFX_PHY_CABLE_STATUS_BUSY,
1170 } efx_phy_cable_status_t;
1172 typedef enum efx_bist_value_e {
1173 EFX_BIST_PHY_CABLE_LENGTH_A,
1174 EFX_BIST_PHY_CABLE_LENGTH_B,
1175 EFX_BIST_PHY_CABLE_LENGTH_C,
1176 EFX_BIST_PHY_CABLE_LENGTH_D,
1177 EFX_BIST_PHY_CABLE_STATUS_A,
1178 EFX_BIST_PHY_CABLE_STATUS_B,
1179 EFX_BIST_PHY_CABLE_STATUS_C,
1180 EFX_BIST_PHY_CABLE_STATUS_D,
1181 EFX_BIST_FAULT_CODE,
1183 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1189 EFX_BIST_MEM_EXPECT,
1190 EFX_BIST_MEM_ACTUAL,
1192 EFX_BIST_MEM_ECC_PARITY,
1193 EFX_BIST_MEM_ECC_FATAL,
1197 extern __checkReturn efx_rc_t
1198 efx_bist_enable_offline(
1199 __in efx_nic_t *enp);
1201 extern __checkReturn efx_rc_t
1203 __in efx_nic_t *enp,
1204 __in efx_bist_type_t type);
1206 extern __checkReturn efx_rc_t
1208 __in efx_nic_t *enp,
1209 __in efx_bist_type_t type,
1210 __out efx_bist_result_t *resultp,
1211 __out_opt uint32_t *value_maskp,
1212 __out_ecount_opt(count) unsigned long *valuesp,
1217 __in efx_nic_t *enp,
1218 __in efx_bist_type_t type);
1220 #endif /* EFSYS_OPT_BIST */
1222 #define EFX_FEATURE_IPV6 0x00000001
1223 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1224 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1225 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1226 #define EFX_FEATURE_MCDI 0x00000020
1227 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1228 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1229 #define EFX_FEATURE_TURBO 0x00000100
1230 #define EFX_FEATURE_MCDI_DMA 0x00000200
1231 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1232 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1233 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1234 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1235 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1237 typedef enum efx_tunnel_protocol_e {
1238 EFX_TUNNEL_PROTOCOL_NONE = 0,
1239 EFX_TUNNEL_PROTOCOL_VXLAN,
1240 EFX_TUNNEL_PROTOCOL_GENEVE,
1241 EFX_TUNNEL_PROTOCOL_NVGRE,
1243 } efx_tunnel_protocol_t;
1245 typedef enum efx_vi_window_shift_e {
1246 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1247 EFX_VI_WINDOW_SHIFT_8K = 13,
1248 EFX_VI_WINDOW_SHIFT_16K = 14,
1249 EFX_VI_WINDOW_SHIFT_64K = 16,
1250 } efx_vi_window_shift_t;
1252 typedef struct efx_nic_cfg_s {
1253 uint32_t enc_board_type;
1254 uint32_t enc_phy_type;
1256 char enc_phy_name[21];
1258 char enc_phy_revision[21];
1259 efx_mon_type_t enc_mon_type;
1260 #if EFSYS_OPT_MON_STATS
1261 uint32_t enc_mon_stat_dma_buf_size;
1262 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1264 unsigned int enc_features;
1265 efx_vi_window_shift_t enc_vi_window_shift;
1266 uint8_t enc_mac_addr[6];
1267 uint8_t enc_port; /* PHY port number */
1268 uint32_t enc_intr_vec_base;
1269 uint32_t enc_intr_limit;
1270 uint32_t enc_evq_limit;
1271 uint32_t enc_txq_limit;
1272 uint32_t enc_rxq_limit;
1273 uint32_t enc_txq_max_ndescs;
1274 uint32_t enc_buftbl_limit;
1275 uint32_t enc_piobuf_limit;
1276 uint32_t enc_piobuf_size;
1277 uint32_t enc_piobuf_min_alloc_size;
1278 uint32_t enc_evq_timer_quantum_ns;
1279 uint32_t enc_evq_timer_max_us;
1280 uint32_t enc_clk_mult;
1281 uint32_t enc_rx_prefix_size;
1282 uint32_t enc_rx_buf_align_start;
1283 uint32_t enc_rx_buf_align_end;
1284 #if EFSYS_OPT_RX_SCALE
1285 uint32_t enc_rx_scale_max_exclusive_contexts;
1287 * Mask of supported hash algorithms.
1288 * Hash algorithm types are used as the bit indices.
1290 uint32_t enc_rx_scale_hash_alg_mask;
1292 * Indicates whether port numbers can be included to the
1293 * input data for hash computation.
1295 boolean_t enc_rx_scale_l4_hash_supported;
1296 boolean_t enc_rx_scale_additional_modes_supported;
1297 #endif /* EFSYS_OPT_RX_SCALE */
1298 #if EFSYS_OPT_LOOPBACK
1299 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1300 #endif /* EFSYS_OPT_LOOPBACK */
1301 #if EFSYS_OPT_PHY_FLAGS
1302 uint32_t enc_phy_flags_mask;
1303 #endif /* EFSYS_OPT_PHY_FLAGS */
1304 #if EFSYS_OPT_PHY_LED_CONTROL
1305 uint32_t enc_led_mask;
1306 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1307 #if EFSYS_OPT_PHY_STATS
1308 uint64_t enc_phy_stat_mask;
1309 #endif /* EFSYS_OPT_PHY_STATS */
1311 uint8_t enc_mcdi_mdio_channel;
1312 #if EFSYS_OPT_PHY_STATS
1313 uint32_t enc_mcdi_phy_stat_mask;
1314 #endif /* EFSYS_OPT_PHY_STATS */
1315 #if EFSYS_OPT_MON_STATS
1316 uint32_t *enc_mcdi_sensor_maskp;
1317 uint32_t enc_mcdi_sensor_mask_size;
1318 #endif /* EFSYS_OPT_MON_STATS */
1319 #endif /* EFSYS_OPT_MCDI */
1321 uint32_t enc_bist_mask;
1322 #endif /* EFSYS_OPT_BIST */
1323 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1326 uint32_t enc_privilege_mask;
1327 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1328 boolean_t enc_bug26807_workaround;
1329 boolean_t enc_bug35388_workaround;
1330 boolean_t enc_bug41750_workaround;
1331 boolean_t enc_bug61265_workaround;
1332 boolean_t enc_bug61297_workaround;
1333 boolean_t enc_rx_batching_enabled;
1334 /* Maximum number of descriptors completed in an rx event. */
1335 uint32_t enc_rx_batch_max;
1336 /* Number of rx descriptors the hardware requires for a push. */
1337 uint32_t enc_rx_push_align;
1338 /* Maximum amount of data in DMA descriptor */
1339 uint32_t enc_tx_dma_desc_size_max;
1341 * Boundary which DMA descriptor data must not cross or 0 if no
1344 uint32_t enc_tx_dma_desc_boundary;
1346 * Maximum number of bytes into the packet the TCP header can start for
1347 * the hardware to apply TSO packet edits.
1349 uint32_t enc_tx_tso_tcp_header_offset_limit;
1350 boolean_t enc_fw_assisted_tso_enabled;
1351 boolean_t enc_fw_assisted_tso_v2_enabled;
1352 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1353 /* Number of TSO contexts on the NIC (FATSOv2) */
1354 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1355 boolean_t enc_hw_tx_insert_vlan_enabled;
1356 /* Number of PFs on the NIC */
1357 uint32_t enc_hw_pf_count;
1358 /* Datapath firmware vadapter/vport/vswitch support */
1359 boolean_t enc_datapath_cap_evb;
1360 boolean_t enc_rx_disable_scatter_supported;
1361 boolean_t enc_allow_set_mac_with_installed_filters;
1362 boolean_t enc_enhanced_set_mac_supported;
1363 boolean_t enc_init_evq_v2_supported;
1364 boolean_t enc_rx_packed_stream_supported;
1365 boolean_t enc_rx_var_packed_stream_supported;
1366 boolean_t enc_rx_es_super_buffer_supported;
1367 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1368 boolean_t enc_pm_and_rxdp_counters;
1369 boolean_t enc_mac_stats_40g_tx_size_bins;
1370 uint32_t enc_tunnel_encapsulations_supported;
1372 * NIC global maximum for unique UDP tunnel ports shared by all
1375 uint32_t enc_tunnel_config_udp_entries_max;
1376 /* External port identifier */
1377 uint8_t enc_external_port;
1378 uint32_t enc_mcdi_max_payload_length;
1379 /* VPD may be per-PF or global */
1380 boolean_t enc_vpd_is_global;
1381 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1382 uint32_t enc_required_pcie_bandwidth_mbps;
1383 uint32_t enc_max_pcie_link_gen;
1384 /* Firmware verifies integrity of NVRAM updates */
1385 uint32_t enc_nvram_update_verify_result_supported;
1386 /* Firmware support for extended MAC_STATS buffer */
1387 uint32_t enc_mac_stats_nstats;
1388 boolean_t enc_fec_counters;
1389 boolean_t enc_hlb_counters;
1390 /* Firmware support for "FLAG" and "MARK" filter actions */
1391 boolean_t enc_filter_action_flag_supported;
1392 boolean_t enc_filter_action_mark_supported;
1393 uint32_t enc_filter_action_mark_max;
1396 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1397 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1399 #define EFX_PCI_FUNCTION(_encp) \
1400 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1402 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1404 extern const efx_nic_cfg_t *
1406 __in efx_nic_t *enp);
1408 /* RxDPCPU firmware id values by which FW variant can be identified */
1409 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1410 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1411 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1412 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1413 #define EFX_RXDP_DPDK_FW_ID 0x6
1415 typedef struct efx_nic_fw_info_s {
1416 /* Basic FW version information */
1417 uint16_t enfi_mc_fw_version[4];
1419 * If datapath capabilities can be detected,
1420 * additional FW information is to be shown
1422 boolean_t enfi_dpcpu_fw_ids_valid;
1423 /* Rx and Tx datapath CPU FW IDs */
1424 uint16_t enfi_rx_dpcpu_fw_id;
1425 uint16_t enfi_tx_dpcpu_fw_id;
1426 } efx_nic_fw_info_t;
1428 extern __checkReturn efx_rc_t
1429 efx_nic_get_fw_version(
1430 __in efx_nic_t *enp,
1431 __out efx_nic_fw_info_t *enfip);
1433 /* Driver resource limits (minimum required/maximum usable). */
1434 typedef struct efx_drv_limits_s {
1435 uint32_t edl_min_evq_count;
1436 uint32_t edl_max_evq_count;
1438 uint32_t edl_min_rxq_count;
1439 uint32_t edl_max_rxq_count;
1441 uint32_t edl_min_txq_count;
1442 uint32_t edl_max_txq_count;
1444 /* PIO blocks (sub-allocated from piobuf) */
1445 uint32_t edl_min_pio_alloc_size;
1446 uint32_t edl_max_pio_alloc_count;
1449 extern __checkReturn efx_rc_t
1450 efx_nic_set_drv_limits(
1451 __inout efx_nic_t *enp,
1452 __in efx_drv_limits_t *edlp);
1454 typedef enum efx_nic_region_e {
1455 EFX_REGION_VI, /* Memory BAR UC mapping */
1456 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1459 extern __checkReturn efx_rc_t
1460 efx_nic_get_bar_region(
1461 __in efx_nic_t *enp,
1462 __in efx_nic_region_t region,
1463 __out uint32_t *offsetp,
1464 __out size_t *sizep);
1466 extern __checkReturn efx_rc_t
1467 efx_nic_get_vi_pool(
1468 __in efx_nic_t *enp,
1469 __out uint32_t *evq_countp,
1470 __out uint32_t *rxq_countp,
1471 __out uint32_t *txq_countp);
1476 typedef enum efx_vpd_tag_e {
1483 typedef uint16_t efx_vpd_keyword_t;
1485 typedef struct efx_vpd_value_s {
1486 efx_vpd_tag_t evv_tag;
1487 efx_vpd_keyword_t evv_keyword;
1489 uint8_t evv_value[0x100];
1493 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1495 extern __checkReturn efx_rc_t
1497 __in efx_nic_t *enp);
1499 extern __checkReturn efx_rc_t
1501 __in efx_nic_t *enp,
1502 __out size_t *sizep);
1504 extern __checkReturn efx_rc_t
1506 __in efx_nic_t *enp,
1507 __out_bcount(size) caddr_t data,
1510 extern __checkReturn efx_rc_t
1512 __in efx_nic_t *enp,
1513 __in_bcount(size) caddr_t data,
1516 extern __checkReturn efx_rc_t
1518 __in efx_nic_t *enp,
1519 __in_bcount(size) caddr_t data,
1522 extern __checkReturn efx_rc_t
1524 __in efx_nic_t *enp,
1525 __in_bcount(size) caddr_t data,
1527 __inout efx_vpd_value_t *evvp);
1529 extern __checkReturn efx_rc_t
1531 __in efx_nic_t *enp,
1532 __inout_bcount(size) caddr_t data,
1534 __in efx_vpd_value_t *evvp);
1536 extern __checkReturn efx_rc_t
1538 __in efx_nic_t *enp,
1539 __inout_bcount(size) caddr_t data,
1541 __out efx_vpd_value_t *evvp,
1542 __inout unsigned int *contp);
1544 extern __checkReturn efx_rc_t
1546 __in efx_nic_t *enp,
1547 __in_bcount(size) caddr_t data,
1552 __in efx_nic_t *enp);
1554 #endif /* EFSYS_OPT_VPD */
1560 typedef enum efx_nvram_type_e {
1561 EFX_NVRAM_INVALID = 0,
1563 EFX_NVRAM_BOOTROM_CFG,
1564 EFX_NVRAM_MC_FIRMWARE,
1565 EFX_NVRAM_MC_GOLDEN,
1571 EFX_NVRAM_FPGA_BACKUP,
1572 EFX_NVRAM_DYNAMIC_CFG,
1575 EFX_NVRAM_MUM_FIRMWARE,
1576 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1577 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1581 extern __checkReturn efx_rc_t
1583 __in efx_nic_t *enp);
1587 extern __checkReturn efx_rc_t
1589 __in efx_nic_t *enp);
1591 #endif /* EFSYS_OPT_DIAG */
1593 extern __checkReturn efx_rc_t
1595 __in efx_nic_t *enp,
1596 __in efx_nvram_type_t type,
1597 __out size_t *sizep);
1599 extern __checkReturn efx_rc_t
1601 __in efx_nic_t *enp,
1602 __in efx_nvram_type_t type,
1603 __out_opt size_t *pref_chunkp);
1605 extern __checkReturn efx_rc_t
1606 efx_nvram_rw_finish(
1607 __in efx_nic_t *enp,
1608 __in efx_nvram_type_t type,
1609 __out_opt uint32_t *verify_resultp);
1611 extern __checkReturn efx_rc_t
1612 efx_nvram_get_version(
1613 __in efx_nic_t *enp,
1614 __in efx_nvram_type_t type,
1615 __out uint32_t *subtypep,
1616 __out_ecount(4) uint16_t version[4]);
1618 extern __checkReturn efx_rc_t
1619 efx_nvram_read_chunk(
1620 __in efx_nic_t *enp,
1621 __in efx_nvram_type_t type,
1622 __in unsigned int offset,
1623 __out_bcount(size) caddr_t data,
1626 extern __checkReturn efx_rc_t
1627 efx_nvram_read_backup(
1628 __in efx_nic_t *enp,
1629 __in efx_nvram_type_t type,
1630 __in unsigned int offset,
1631 __out_bcount(size) caddr_t data,
1634 extern __checkReturn efx_rc_t
1635 efx_nvram_set_version(
1636 __in efx_nic_t *enp,
1637 __in efx_nvram_type_t type,
1638 __in_ecount(4) uint16_t version[4]);
1640 extern __checkReturn efx_rc_t
1642 __in efx_nic_t *enp,
1643 __in efx_nvram_type_t type,
1644 __in_bcount(partn_size) caddr_t partn_data,
1645 __in size_t partn_size);
1647 extern __checkReturn efx_rc_t
1649 __in efx_nic_t *enp,
1650 __in efx_nvram_type_t type);
1652 extern __checkReturn efx_rc_t
1653 efx_nvram_write_chunk(
1654 __in efx_nic_t *enp,
1655 __in efx_nvram_type_t type,
1656 __in unsigned int offset,
1657 __in_bcount(size) caddr_t data,
1662 __in efx_nic_t *enp);
1664 #endif /* EFSYS_OPT_NVRAM */
1666 #if EFSYS_OPT_BOOTCFG
1668 /* Report size and offset of bootcfg sector in NVRAM partition. */
1669 extern __checkReturn efx_rc_t
1670 efx_bootcfg_sector_info(
1671 __in efx_nic_t *enp,
1673 __out_opt uint32_t *sector_countp,
1674 __out size_t *offsetp,
1675 __out size_t *max_sizep);
1678 * Copy bootcfg sector data to a target buffer which may differ in size.
1679 * Optionally corrects format errors in source buffer.
1682 efx_bootcfg_copy_sector(
1683 __in efx_nic_t *enp,
1684 __inout_bcount(sector_length)
1686 __in size_t sector_length,
1687 __out_bcount(data_size) uint8_t *data,
1688 __in size_t data_size,
1689 __in boolean_t handle_format_errors);
1693 __in efx_nic_t *enp,
1694 __out_bcount(size) uint8_t *data,
1699 __in efx_nic_t *enp,
1700 __in_bcount(size) uint8_t *data,
1705 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1706 * (see https://tools.ietf.org/html/rfc1533)
1708 * Summarising the format: the buffer is a sequence of options. All options
1709 * begin with a tag octet, which uniquely identifies the option. Fixed-
1710 * length options without data consist of only a tag octet. Only options PAD
1711 * (0) and END (255) are fixed length. All other options are variable-length
1712 * with a length octet following the tag octet. The value of the length
1713 * octet does not include the two octets specifying the tag and length. The
1714 * length octet is followed by "length" octets of data.
1716 * Option data may be a sequence of sub-options in the same format. The data
1717 * content of the encapsulating option is one or more encapsulated sub-options,
1718 * with no terminating END tag is required.
1720 * To be valid, the top-level sequence of options should be terminated by an
1721 * END tag. The buffer should be padded with the PAD byte.
1723 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1724 * checksum octet. The full buffer (including after the END tag) contributes
1725 * to the checksum, hence the need to fill the buffer to the end with PAD.
1728 #define EFX_DHCP_END ((uint8_t)0xff)
1729 #define EFX_DHCP_PAD ((uint8_t)0)
1731 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1732 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1734 extern __checkReturn uint8_t
1736 __in_bcount(size) uint8_t const *data,
1739 extern __checkReturn efx_rc_t
1741 __in_bcount(size) uint8_t const *data,
1743 __out_opt size_t *usedp);
1745 extern __checkReturn efx_rc_t
1747 __in_bcount(buffer_length) uint8_t *bufferp,
1748 __in size_t buffer_length,
1750 __deref_out uint8_t **valuepp,
1751 __out size_t *value_lengthp);
1753 extern __checkReturn efx_rc_t
1755 __in_bcount(buffer_length) uint8_t *bufferp,
1756 __in size_t buffer_length,
1757 __deref_out uint8_t **endpp);
1760 extern __checkReturn efx_rc_t
1761 efx_dhcp_delete_tag(
1762 __inout_bcount(buffer_length) uint8_t *bufferp,
1763 __in size_t buffer_length,
1766 extern __checkReturn efx_rc_t
1768 __inout_bcount(buffer_length) uint8_t *bufferp,
1769 __in size_t buffer_length,
1771 __in_bcount_opt(value_length) uint8_t *valuep,
1772 __in size_t value_length);
1774 extern __checkReturn efx_rc_t
1775 efx_dhcp_update_tag(
1776 __inout_bcount(buffer_length) uint8_t *bufferp,
1777 __in size_t buffer_length,
1779 __in uint8_t *value_locationp,
1780 __in_bcount_opt(value_length) uint8_t *valuep,
1781 __in size_t value_length);
1784 #endif /* EFSYS_OPT_BOOTCFG */
1786 #if EFSYS_OPT_IMAGE_LAYOUT
1788 #include "ef10_signed_image_layout.h"
1791 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1794 * The image header format is extensible. However, older drivers require an
1795 * exact match of image header version and header length when validating and
1796 * writing firmware images.
1798 * To avoid breaking backward compatibility, we use the upper bits of the
1799 * controller version fields to contain an extra version number used for
1800 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1801 * version). See bug39254 and SF-102785-PS for details.
1803 typedef struct efx_image_header_s {
1805 uint32_t eih_version;
1807 uint32_t eih_subtype;
1808 uint32_t eih_code_size;
1811 uint32_t eih_controller_version_min;
1813 uint16_t eih_controller_version_min_short;
1814 uint8_t eih_extra_version_a;
1815 uint8_t eih_extra_version_b;
1819 uint32_t eih_controller_version_max;
1821 uint16_t eih_controller_version_max_short;
1822 uint8_t eih_extra_version_c;
1823 uint8_t eih_extra_version_d;
1826 uint16_t eih_code_version_a;
1827 uint16_t eih_code_version_b;
1828 uint16_t eih_code_version_c;
1829 uint16_t eih_code_version_d;
1830 } efx_image_header_t;
1832 #define EFX_IMAGE_HEADER_SIZE (40)
1833 #define EFX_IMAGE_HEADER_VERSION (4)
1834 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1837 typedef struct efx_image_trailer_s {
1839 } efx_image_trailer_t;
1841 #define EFX_IMAGE_TRAILER_SIZE (4)
1843 typedef enum efx_image_format_e {
1844 EFX_IMAGE_FORMAT_NO_IMAGE,
1845 EFX_IMAGE_FORMAT_INVALID,
1846 EFX_IMAGE_FORMAT_UNSIGNED,
1847 EFX_IMAGE_FORMAT_SIGNED,
1848 } efx_image_format_t;
1850 typedef struct efx_image_info_s {
1851 efx_image_format_t eii_format;
1852 uint8_t * eii_imagep;
1853 size_t eii_image_size;
1854 efx_image_header_t * eii_headerp;
1857 extern __checkReturn efx_rc_t
1858 efx_check_reflash_image(
1860 __in uint32_t buffer_size,
1861 __out efx_image_info_t *infop);
1863 extern __checkReturn efx_rc_t
1864 efx_build_signed_image_write_buffer(
1865 __out_bcount(buffer_size)
1867 __in uint32_t buffer_size,
1868 __in efx_image_info_t *infop,
1869 __out efx_image_header_t **headerpp);
1871 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1875 typedef enum efx_pattern_type_t {
1876 EFX_PATTERN_BYTE_INCREMENT = 0,
1877 EFX_PATTERN_ALL_THE_SAME,
1878 EFX_PATTERN_BIT_ALTERNATE,
1879 EFX_PATTERN_BYTE_ALTERNATE,
1880 EFX_PATTERN_BYTE_CHANGING,
1881 EFX_PATTERN_BIT_SWEEP,
1883 } efx_pattern_type_t;
1886 (*efx_sram_pattern_fn_t)(
1888 __in boolean_t negate,
1889 __out efx_qword_t *eqp);
1891 extern __checkReturn efx_rc_t
1893 __in efx_nic_t *enp,
1894 __in efx_pattern_type_t type);
1896 #endif /* EFSYS_OPT_DIAG */
1898 extern __checkReturn efx_rc_t
1899 efx_sram_buf_tbl_set(
1900 __in efx_nic_t *enp,
1902 __in efsys_mem_t *esmp,
1906 efx_sram_buf_tbl_clear(
1907 __in efx_nic_t *enp,
1911 #define EFX_BUF_TBL_SIZE 0x20000
1913 #define EFX_BUF_SIZE 4096
1917 typedef struct efx_evq_s efx_evq_t;
1919 #if EFSYS_OPT_QSTATS
1921 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1922 typedef enum efx_ev_qstat_e {
1928 EV_RX_PAUSE_FRM_ERR,
1929 EV_RX_BUF_OWNER_ID_ERR,
1930 EV_RX_IPV4_HDR_CHKSUM_ERR,
1931 EV_RX_TCP_UDP_CHKSUM_ERR,
1935 EV_RX_MCAST_HASH_MATCH,
1952 EV_DRIVER_SRM_UPD_DONE,
1953 EV_DRIVER_TX_DESCQ_FLS_DONE,
1954 EV_DRIVER_RX_DESCQ_FLS_DONE,
1955 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1956 EV_DRIVER_RX_DSC_ERROR,
1957 EV_DRIVER_TX_DSC_ERROR,
1963 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1965 #endif /* EFSYS_OPT_QSTATS */
1967 extern __checkReturn efx_rc_t
1969 __in efx_nic_t *enp);
1973 __in efx_nic_t *enp);
1975 #define EFX_EVQ_MAXNEVS 32768
1976 #define EFX_EVQ_MINNEVS 512
1978 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1979 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1981 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1982 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1983 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1984 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1986 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1987 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1988 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1990 extern __checkReturn efx_rc_t
1992 __in efx_nic_t *enp,
1993 __in unsigned int index,
1994 __in efsys_mem_t *esmp,
1998 __in uint32_t flags,
1999 __deref_out efx_evq_t **eepp);
2003 __in efx_evq_t *eep,
2004 __in uint16_t data);
2006 typedef __checkReturn boolean_t
2007 (*efx_initialized_ev_t)(
2008 __in_opt void *arg);
2010 #define EFX_PKT_UNICAST 0x0004
2011 #define EFX_PKT_START 0x0008
2013 #define EFX_PKT_VLAN_TAGGED 0x0010
2014 #define EFX_CKSUM_TCPUDP 0x0020
2015 #define EFX_CKSUM_IPV4 0x0040
2016 #define EFX_PKT_CONT 0x0080
2018 #define EFX_CHECK_VLAN 0x0100
2019 #define EFX_PKT_TCP 0x0200
2020 #define EFX_PKT_UDP 0x0400
2021 #define EFX_PKT_IPV4 0x0800
2023 #define EFX_PKT_IPV6 0x1000
2024 #define EFX_PKT_PREFIX_LEN 0x2000
2025 #define EFX_ADDR_MISMATCH 0x4000
2026 #define EFX_DISCARD 0x8000
2029 * The following flags are used only for packed stream
2030 * mode. The values for the flags are reused to fit into 16 bit,
2031 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2032 * packed stream mode
2034 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2035 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2038 #define EFX_EV_RX_NLABELS 32
2039 #define EFX_EV_TX_NLABELS 32
2041 typedef __checkReturn boolean_t
2044 __in uint32_t label,
2047 __in uint16_t flags);
2049 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2052 * Packed stream mode is documented in SF-112241-TC.
2053 * The general idea is that, instead of putting each incoming
2054 * packet into a separate buffer which is specified in a RX
2055 * descriptor, a large buffer is provided to the hardware and
2056 * packets are put there in a continuous stream.
2057 * The main advantage of such an approach is that RX queue refilling
2058 * happens much less frequently.
2060 * Equal stride packed stream mode is documented in SF-119419-TC.
2061 * The general idea is to utilize advantages of the packed stream,
2062 * but avoid indirection in packets representation.
2063 * The main advantage of such an approach is that RX queue refilling
2064 * happens much less frequently and packets buffers are independent
2065 * from upper layers point of view.
2068 typedef __checkReturn boolean_t
2071 __in uint32_t label,
2073 __in uint32_t pkt_count,
2074 __in uint16_t flags);
2078 typedef __checkReturn boolean_t
2081 __in uint32_t label,
2084 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2085 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2086 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2087 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2088 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2089 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2090 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2091 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2092 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2094 typedef __checkReturn boolean_t
2095 (*efx_exception_ev_t)(
2097 __in uint32_t label,
2098 __in uint32_t data);
2100 typedef __checkReturn boolean_t
2101 (*efx_rxq_flush_done_ev_t)(
2103 __in uint32_t rxq_index);
2105 typedef __checkReturn boolean_t
2106 (*efx_rxq_flush_failed_ev_t)(
2108 __in uint32_t rxq_index);
2110 typedef __checkReturn boolean_t
2111 (*efx_txq_flush_done_ev_t)(
2113 __in uint32_t txq_index);
2115 typedef __checkReturn boolean_t
2116 (*efx_software_ev_t)(
2118 __in uint16_t magic);
2120 typedef __checkReturn boolean_t
2123 __in uint32_t code);
2125 #define EFX_SRAM_CLEAR 0
2126 #define EFX_SRAM_UPDATE 1
2127 #define EFX_SRAM_ILLEGAL_CLEAR 2
2129 typedef __checkReturn boolean_t
2130 (*efx_wake_up_ev_t)(
2132 __in uint32_t label);
2134 typedef __checkReturn boolean_t
2137 __in uint32_t label);
2139 typedef __checkReturn boolean_t
2140 (*efx_link_change_ev_t)(
2142 __in efx_link_mode_t link_mode);
2144 #if EFSYS_OPT_MON_STATS
2146 typedef __checkReturn boolean_t
2147 (*efx_monitor_ev_t)(
2149 __in efx_mon_stat_t id,
2150 __in efx_mon_stat_value_t value);
2152 #endif /* EFSYS_OPT_MON_STATS */
2154 #if EFSYS_OPT_MAC_STATS
2156 typedef __checkReturn boolean_t
2157 (*efx_mac_stats_ev_t)(
2159 __in uint32_t generation);
2161 #endif /* EFSYS_OPT_MAC_STATS */
2163 typedef struct efx_ev_callbacks_s {
2164 efx_initialized_ev_t eec_initialized;
2166 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2167 efx_rx_ps_ev_t eec_rx_ps;
2170 efx_exception_ev_t eec_exception;
2171 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2172 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2173 efx_txq_flush_done_ev_t eec_txq_flush_done;
2174 efx_software_ev_t eec_software;
2175 efx_sram_ev_t eec_sram;
2176 efx_wake_up_ev_t eec_wake_up;
2177 efx_timer_ev_t eec_timer;
2178 efx_link_change_ev_t eec_link_change;
2179 #if EFSYS_OPT_MON_STATS
2180 efx_monitor_ev_t eec_monitor;
2181 #endif /* EFSYS_OPT_MON_STATS */
2182 #if EFSYS_OPT_MAC_STATS
2183 efx_mac_stats_ev_t eec_mac_stats;
2184 #endif /* EFSYS_OPT_MAC_STATS */
2185 } efx_ev_callbacks_t;
2187 extern __checkReturn boolean_t
2189 __in efx_evq_t *eep,
2190 __in unsigned int count);
2192 #if EFSYS_OPT_EV_PREFETCH
2196 __in efx_evq_t *eep,
2197 __in unsigned int count);
2199 #endif /* EFSYS_OPT_EV_PREFETCH */
2203 __in efx_evq_t *eep,
2204 __inout unsigned int *countp,
2205 __in const efx_ev_callbacks_t *eecp,
2206 __in_opt void *arg);
2208 extern __checkReturn efx_rc_t
2209 efx_ev_usecs_to_ticks(
2210 __in efx_nic_t *enp,
2211 __in unsigned int usecs,
2212 __out unsigned int *ticksp);
2214 extern __checkReturn efx_rc_t
2216 __in efx_evq_t *eep,
2217 __in unsigned int us);
2219 extern __checkReturn efx_rc_t
2221 __in efx_evq_t *eep,
2222 __in unsigned int count);
2224 #if EFSYS_OPT_QSTATS
2230 __in efx_nic_t *enp,
2231 __in unsigned int id);
2233 #endif /* EFSYS_OPT_NAMES */
2236 efx_ev_qstats_update(
2237 __in efx_evq_t *eep,
2238 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2240 #endif /* EFSYS_OPT_QSTATS */
2244 __in efx_evq_t *eep);
2248 extern __checkReturn efx_rc_t
2250 __inout efx_nic_t *enp);
2254 __in efx_nic_t *enp);
2256 #if EFSYS_OPT_RX_SCATTER
2257 __checkReturn efx_rc_t
2258 efx_rx_scatter_enable(
2259 __in efx_nic_t *enp,
2260 __in unsigned int buf_size);
2261 #endif /* EFSYS_OPT_RX_SCATTER */
2263 /* Handle to represent use of the default RSS context. */
2264 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2266 #if EFSYS_OPT_RX_SCALE
2268 typedef enum efx_rx_hash_alg_e {
2269 EFX_RX_HASHALG_LFSR = 0,
2270 EFX_RX_HASHALG_TOEPLITZ,
2271 EFX_RX_HASHALG_PACKED_STREAM,
2273 } efx_rx_hash_alg_t;
2276 * Legacy hash type flags.
2278 * They represent standard tuples for distinct traffic classes.
2280 #define EFX_RX_HASH_IPV4 (1U << 0)
2281 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2282 #define EFX_RX_HASH_IPV6 (1U << 2)
2283 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2285 #define EFX_RX_HASH_LEGACY_MASK \
2286 (EFX_RX_HASH_IPV4 | \
2287 EFX_RX_HASH_TCPIPV4 | \
2288 EFX_RX_HASH_IPV6 | \
2289 EFX_RX_HASH_TCPIPV6)
2292 * The type of the argument used by efx_rx_scale_mode_set() to
2293 * provide a means for the client drivers to configure hashing.
2295 * A properly constructed value can either be:
2296 * - a combination of legacy flags
2297 * - a combination of EFX_RX_HASH() flags
2299 typedef uint32_t efx_rx_hash_type_t;
2301 typedef enum efx_rx_hash_support_e {
2302 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2303 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2304 } efx_rx_hash_support_t;
2306 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2307 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2308 #define EFX_MAXRSS 64 /* RX indirection entry range */
2309 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2311 typedef enum efx_rx_scale_context_type_e {
2312 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2313 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2314 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2315 } efx_rx_scale_context_type_t;
2318 * Traffic classes eligible for hash computation.
2320 * Select packet headers used in computing the receive hash.
2321 * This uses the same encoding as the RSS_MODES field of
2322 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2324 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2325 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2326 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2327 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2328 #define EFX_RX_CLASS_IPV4_LBN 16
2329 #define EFX_RX_CLASS_IPV4_WIDTH 4
2330 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2331 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2332 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2333 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2334 #define EFX_RX_CLASS_IPV6_LBN 28
2335 #define EFX_RX_CLASS_IPV6_WIDTH 4
2337 #define EFX_RX_NCLASSES 6
2340 * Ancillary flags used to construct generic hash tuples.
2341 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2343 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2344 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2345 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2346 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2349 * Generic hash tuples.
2351 * They express combinations of packet fields
2352 * which can contribute to the hash value for
2353 * a particular traffic class.
2355 #define EFX_RX_CLASS_HASH_DISABLE 0
2357 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2358 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2360 #define EFX_RX_CLASS_HASH_2TUPLE \
2361 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2362 EFX_RX_CLASS_HASH_DST_ADDR)
2364 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2365 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2366 EFX_RX_CLASS_HASH_SRC_PORT)
2368 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2369 (EFX_RX_CLASS_HASH_DST_ADDR | \
2370 EFX_RX_CLASS_HASH_DST_PORT)
2372 #define EFX_RX_CLASS_HASH_4TUPLE \
2373 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2374 EFX_RX_CLASS_HASH_DST_ADDR | \
2375 EFX_RX_CLASS_HASH_SRC_PORT | \
2376 EFX_RX_CLASS_HASH_DST_PORT)
2378 #define EFX_RX_CLASS_HASH_NTUPLES 7
2381 * Hash flag constructor.
2383 * Resulting flags encode hash tuples for specific traffic classes.
2384 * The client drivers are encouraged to use these flags to form
2385 * a hash type value.
2387 #define EFX_RX_HASH(_class, _tuple) \
2388 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2389 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2392 * The maximum number of EFX_RX_HASH() flags.
2394 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2396 extern __checkReturn efx_rc_t
2397 efx_rx_scale_hash_flags_get(
2398 __in efx_nic_t *enp,
2399 __in efx_rx_hash_alg_t hash_alg,
2400 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2401 __in unsigned int max_nflags,
2402 __out unsigned int *nflagsp);
2404 extern __checkReturn efx_rc_t
2405 efx_rx_hash_default_support_get(
2406 __in efx_nic_t *enp,
2407 __out efx_rx_hash_support_t *supportp);
2410 extern __checkReturn efx_rc_t
2411 efx_rx_scale_default_support_get(
2412 __in efx_nic_t *enp,
2413 __out efx_rx_scale_context_type_t *typep);
2415 extern __checkReturn efx_rc_t
2416 efx_rx_scale_context_alloc(
2417 __in efx_nic_t *enp,
2418 __in efx_rx_scale_context_type_t type,
2419 __in uint32_t num_queues,
2420 __out uint32_t *rss_contextp);
2422 extern __checkReturn efx_rc_t
2423 efx_rx_scale_context_free(
2424 __in efx_nic_t *enp,
2425 __in uint32_t rss_context);
2427 extern __checkReturn efx_rc_t
2428 efx_rx_scale_mode_set(
2429 __in efx_nic_t *enp,
2430 __in uint32_t rss_context,
2431 __in efx_rx_hash_alg_t alg,
2432 __in efx_rx_hash_type_t type,
2433 __in boolean_t insert);
2435 extern __checkReturn efx_rc_t
2436 efx_rx_scale_tbl_set(
2437 __in efx_nic_t *enp,
2438 __in uint32_t rss_context,
2439 __in_ecount(n) unsigned int *table,
2442 extern __checkReturn efx_rc_t
2443 efx_rx_scale_key_set(
2444 __in efx_nic_t *enp,
2445 __in uint32_t rss_context,
2446 __in_ecount(n) uint8_t *key,
2449 extern __checkReturn uint32_t
2450 efx_pseudo_hdr_hash_get(
2451 __in efx_rxq_t *erp,
2452 __in efx_rx_hash_alg_t func,
2453 __in uint8_t *buffer);
2455 #endif /* EFSYS_OPT_RX_SCALE */
2457 extern __checkReturn efx_rc_t
2458 efx_pseudo_hdr_pkt_length_get(
2459 __in efx_rxq_t *erp,
2460 __in uint8_t *buffer,
2461 __out uint16_t *pkt_lengthp);
2463 #define EFX_RXQ_MAXNDESCS 4096
2464 #define EFX_RXQ_MINNDESCS 512
2466 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2467 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2468 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2469 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2471 typedef enum efx_rxq_type_e {
2472 EFX_RXQ_TYPE_DEFAULT,
2473 EFX_RXQ_TYPE_PACKED_STREAM,
2474 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2479 * Dummy flag to be used instead of 0 to make it clear that the argument
2480 * is receive queue flags.
2482 #define EFX_RXQ_FLAG_NONE 0x0
2483 #define EFX_RXQ_FLAG_SCATTER 0x1
2485 * If tunnels are supported and Rx event can provide information about
2486 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2487 * full-feature firmware variant running), outer classes are requested by
2488 * default. However, if the driver supports tunnels, the flag allows to
2489 * request inner classes which are required to be able to interpret inner
2490 * Rx checksum offload results.
2492 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2494 extern __checkReturn efx_rc_t
2496 __in efx_nic_t *enp,
2497 __in unsigned int index,
2498 __in unsigned int label,
2499 __in efx_rxq_type_t type,
2500 __in efsys_mem_t *esmp,
2503 __in unsigned int flags,
2504 __in efx_evq_t *eep,
2505 __deref_out efx_rxq_t **erpp);
2507 #if EFSYS_OPT_RX_PACKED_STREAM
2509 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2510 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2511 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2512 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2513 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2515 extern __checkReturn efx_rc_t
2516 efx_rx_qcreate_packed_stream(
2517 __in efx_nic_t *enp,
2518 __in unsigned int index,
2519 __in unsigned int label,
2520 __in uint32_t ps_buf_size,
2521 __in efsys_mem_t *esmp,
2523 __in efx_evq_t *eep,
2524 __deref_out efx_rxq_t **erpp);
2528 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2530 /* Maximum head-of-line block timeout in nanoseconds */
2531 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2533 extern __checkReturn efx_rc_t
2534 efx_rx_qcreate_es_super_buffer(
2535 __in efx_nic_t *enp,
2536 __in unsigned int index,
2537 __in unsigned int label,
2538 __in uint32_t n_bufs_per_desc,
2539 __in uint32_t max_dma_len,
2540 __in uint32_t buf_stride,
2541 __in uint32_t hol_block_timeout,
2542 __in efsys_mem_t *esmp,
2544 __in unsigned int flags,
2545 __in efx_evq_t *eep,
2546 __deref_out efx_rxq_t **erpp);
2550 typedef struct efx_buffer_s {
2551 efsys_dma_addr_t eb_addr;
2556 typedef struct efx_desc_s {
2562 __in efx_rxq_t *erp,
2563 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2565 __in unsigned int ndescs,
2566 __in unsigned int completed,
2567 __in unsigned int added);
2571 __in efx_rxq_t *erp,
2572 __in unsigned int added,
2573 __inout unsigned int *pushedp);
2575 #if EFSYS_OPT_RX_PACKED_STREAM
2578 efx_rx_qpush_ps_credits(
2579 __in efx_rxq_t *erp);
2581 extern __checkReturn uint8_t *
2582 efx_rx_qps_packet_info(
2583 __in efx_rxq_t *erp,
2584 __in uint8_t *buffer,
2585 __in uint32_t buffer_length,
2586 __in uint32_t current_offset,
2587 __out uint16_t *lengthp,
2588 __out uint32_t *next_offsetp,
2589 __out uint32_t *timestamp);
2592 extern __checkReturn efx_rc_t
2594 __in efx_rxq_t *erp);
2598 __in efx_rxq_t *erp);
2602 __in efx_rxq_t *erp);
2606 typedef struct efx_txq_s efx_txq_t;
2608 #if EFSYS_OPT_QSTATS
2610 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2611 typedef enum efx_tx_qstat_e {
2617 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2619 #endif /* EFSYS_OPT_QSTATS */
2621 extern __checkReturn efx_rc_t
2623 __in efx_nic_t *enp);
2627 __in efx_nic_t *enp);
2629 #define EFX_TXQ_MINNDESCS 512
2631 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2632 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2633 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2635 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2637 #define EFX_TXQ_CKSUM_IPV4 0x0001
2638 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2639 #define EFX_TXQ_FATSOV2 0x0004
2640 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2641 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2643 extern __checkReturn efx_rc_t
2645 __in efx_nic_t *enp,
2646 __in unsigned int index,
2647 __in unsigned int label,
2648 __in efsys_mem_t *esmp,
2651 __in uint16_t flags,
2652 __in efx_evq_t *eep,
2653 __deref_out efx_txq_t **etpp,
2654 __out unsigned int *addedp);
2656 extern __checkReturn efx_rc_t
2658 __in efx_txq_t *etp,
2659 __in_ecount(ndescs) efx_buffer_t *eb,
2660 __in unsigned int ndescs,
2661 __in unsigned int completed,
2662 __inout unsigned int *addedp);
2664 extern __checkReturn efx_rc_t
2666 __in efx_txq_t *etp,
2667 __in unsigned int ns);
2671 __in efx_txq_t *etp,
2672 __in unsigned int added,
2673 __in unsigned int pushed);
2675 extern __checkReturn efx_rc_t
2677 __in efx_txq_t *etp);
2681 __in efx_txq_t *etp);
2683 extern __checkReturn efx_rc_t
2685 __in efx_txq_t *etp);
2688 efx_tx_qpio_disable(
2689 __in efx_txq_t *etp);
2691 extern __checkReturn efx_rc_t
2693 __in efx_txq_t *etp,
2694 __in_ecount(buf_length) uint8_t *buffer,
2695 __in size_t buf_length,
2696 __in size_t pio_buf_offset);
2698 extern __checkReturn efx_rc_t
2700 __in efx_txq_t *etp,
2701 __in size_t pkt_length,
2702 __in unsigned int completed,
2703 __inout unsigned int *addedp);
2705 extern __checkReturn efx_rc_t
2707 __in efx_txq_t *etp,
2708 __in_ecount(n) efx_desc_t *ed,
2709 __in unsigned int n,
2710 __in unsigned int completed,
2711 __inout unsigned int *addedp);
2714 efx_tx_qdesc_dma_create(
2715 __in efx_txq_t *etp,
2716 __in efsys_dma_addr_t addr,
2719 __out efx_desc_t *edp);
2722 efx_tx_qdesc_tso_create(
2723 __in efx_txq_t *etp,
2724 __in uint16_t ipv4_id,
2725 __in uint32_t tcp_seq,
2726 __in uint8_t tcp_flags,
2727 __out efx_desc_t *edp);
2729 /* Number of FATSOv2 option descriptors */
2730 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2732 /* Maximum number of DMA segments per TSO packet (not superframe) */
2733 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2736 efx_tx_qdesc_tso2_create(
2737 __in efx_txq_t *etp,
2738 __in uint16_t ipv4_id,
2739 __in uint16_t outer_ipv4_id,
2740 __in uint32_t tcp_seq,
2741 __in uint16_t tcp_mss,
2742 __out_ecount(count) efx_desc_t *edp,
2746 efx_tx_qdesc_vlantci_create(
2747 __in efx_txq_t *etp,
2749 __out efx_desc_t *edp);
2752 efx_tx_qdesc_checksum_create(
2753 __in efx_txq_t *etp,
2754 __in uint16_t flags,
2755 __out efx_desc_t *edp);
2757 #if EFSYS_OPT_QSTATS
2763 __in efx_nic_t *etp,
2764 __in unsigned int id);
2766 #endif /* EFSYS_OPT_NAMES */
2769 efx_tx_qstats_update(
2770 __in efx_txq_t *etp,
2771 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2773 #endif /* EFSYS_OPT_QSTATS */
2777 __in efx_txq_t *etp);
2782 #if EFSYS_OPT_FILTER
2784 #define EFX_ETHER_TYPE_IPV4 0x0800
2785 #define EFX_ETHER_TYPE_IPV6 0x86DD
2787 #define EFX_IPPROTO_TCP 6
2788 #define EFX_IPPROTO_UDP 17
2789 #define EFX_IPPROTO_GRE 47
2791 /* Use RSS to spread across multiple queues */
2792 #define EFX_FILTER_FLAG_RX_RSS 0x01
2793 /* Enable RX scatter */
2794 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2796 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2797 * May only be set by the filter implementation for each type.
2798 * A removal request will restore the automatic filter in its place.
2800 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2801 /* Filter is for RX */
2802 #define EFX_FILTER_FLAG_RX 0x08
2803 /* Filter is for TX */
2804 #define EFX_FILTER_FLAG_TX 0x10
2805 /* Set match flag on the received packet */
2806 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2807 /* Set match mark on the received packet */
2808 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2810 typedef uint8_t efx_filter_flags_t;
2813 * Flags which specify the fields to match on. The values are the same as in the
2814 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2817 /* Match by remote IP host address */
2818 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2819 /* Match by local IP host address */
2820 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2821 /* Match by remote MAC address */
2822 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2823 /* Match by remote TCP/UDP port */
2824 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2825 /* Match by remote TCP/UDP port */
2826 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2827 /* Match by local TCP/UDP port */
2828 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2829 /* Match by Ether-type */
2830 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2831 /* Match by inner VLAN ID */
2832 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2833 /* Match by outer VLAN ID */
2834 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2835 /* Match by IP transport protocol */
2836 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2837 /* Match by VNI or VSID */
2838 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2839 /* For encapsulated packets, match by inner frame local MAC address */
2840 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2841 /* For encapsulated packets, match all multicast inner frames */
2842 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2843 /* For encapsulated packets, match all unicast inner frames */
2844 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2846 * Match by encap type, this flag does not correspond to
2847 * the MCDI match flags and any unoccupied value may be used
2849 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2850 /* Match otherwise-unmatched multicast and broadcast packets */
2851 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2852 /* Match otherwise-unmatched unicast packets */
2853 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2855 typedef uint32_t efx_filter_match_flags_t;
2857 typedef enum efx_filter_priority_s {
2858 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2859 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2860 * address list or hardware
2861 * requirements. This may only be used
2862 * by the filter implementation for
2864 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2865 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2866 * client (e.g. SR-IOV, HyperV VMQ etc.)
2868 } efx_filter_priority_t;
2871 * FIXME: All these fields are assumed to be in little-endian byte order.
2872 * It may be better for some to be big-endian. See bug42804.
2875 typedef struct efx_filter_spec_s {
2876 efx_filter_match_flags_t efs_match_flags;
2877 uint8_t efs_priority;
2878 efx_filter_flags_t efs_flags;
2879 uint16_t efs_dmaq_id;
2880 uint32_t efs_rss_context;
2881 uint16_t efs_outer_vid;
2882 uint16_t efs_inner_vid;
2883 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2884 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2885 uint16_t efs_ether_type;
2886 uint8_t efs_ip_proto;
2887 efx_tunnel_protocol_t efs_encap_type;
2888 uint16_t efs_loc_port;
2889 uint16_t efs_rem_port;
2890 efx_oword_t efs_rem_host;
2891 efx_oword_t efs_loc_host;
2892 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2893 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2895 } efx_filter_spec_t;
2898 /* Default values for use in filter specifications */
2899 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2900 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2902 extern __checkReturn efx_rc_t
2904 __in efx_nic_t *enp);
2908 __in efx_nic_t *enp);
2910 extern __checkReturn efx_rc_t
2912 __in efx_nic_t *enp,
2913 __inout efx_filter_spec_t *spec);
2915 extern __checkReturn efx_rc_t
2917 __in efx_nic_t *enp,
2918 __inout efx_filter_spec_t *spec);
2920 extern __checkReturn efx_rc_t
2922 __in efx_nic_t *enp);
2924 extern __checkReturn efx_rc_t
2925 efx_filter_supported_filters(
2926 __in efx_nic_t *enp,
2927 __out_ecount(buffer_length) uint32_t *buffer,
2928 __in size_t buffer_length,
2929 __out size_t *list_lengthp);
2932 efx_filter_spec_init_rx(
2933 __out efx_filter_spec_t *spec,
2934 __in efx_filter_priority_t priority,
2935 __in efx_filter_flags_t flags,
2936 __in efx_rxq_t *erp);
2939 efx_filter_spec_init_tx(
2940 __out efx_filter_spec_t *spec,
2941 __in efx_txq_t *etp);
2943 extern __checkReturn efx_rc_t
2944 efx_filter_spec_set_ipv4_local(
2945 __inout efx_filter_spec_t *spec,
2948 __in uint16_t port);
2950 extern __checkReturn efx_rc_t
2951 efx_filter_spec_set_ipv4_full(
2952 __inout efx_filter_spec_t *spec,
2954 __in uint32_t lhost,
2955 __in uint16_t lport,
2956 __in uint32_t rhost,
2957 __in uint16_t rport);
2959 extern __checkReturn efx_rc_t
2960 efx_filter_spec_set_eth_local(
2961 __inout efx_filter_spec_t *spec,
2963 __in const uint8_t *addr);
2966 efx_filter_spec_set_ether_type(
2967 __inout efx_filter_spec_t *spec,
2968 __in uint16_t ether_type);
2970 extern __checkReturn efx_rc_t
2971 efx_filter_spec_set_uc_def(
2972 __inout efx_filter_spec_t *spec);
2974 extern __checkReturn efx_rc_t
2975 efx_filter_spec_set_mc_def(
2976 __inout efx_filter_spec_t *spec);
2978 typedef enum efx_filter_inner_frame_match_e {
2979 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2980 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2981 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2982 } efx_filter_inner_frame_match_t;
2984 extern __checkReturn efx_rc_t
2985 efx_filter_spec_set_encap_type(
2986 __inout efx_filter_spec_t *spec,
2987 __in efx_tunnel_protocol_t encap_type,
2988 __in efx_filter_inner_frame_match_t inner_frame_match);
2990 extern __checkReturn efx_rc_t
2991 efx_filter_spec_set_vxlan(
2992 __inout efx_filter_spec_t *spec,
2993 __in const uint8_t *vni,
2994 __in const uint8_t *inner_addr,
2995 __in const uint8_t *outer_addr);
2997 extern __checkReturn efx_rc_t
2998 efx_filter_spec_set_geneve(
2999 __inout efx_filter_spec_t *spec,
3000 __in const uint8_t *vni,
3001 __in const uint8_t *inner_addr,
3002 __in const uint8_t *outer_addr);
3004 extern __checkReturn efx_rc_t
3005 efx_filter_spec_set_nvgre(
3006 __inout efx_filter_spec_t *spec,
3007 __in const uint8_t *vsid,
3008 __in const uint8_t *inner_addr,
3009 __in const uint8_t *outer_addr);
3011 #if EFSYS_OPT_RX_SCALE
3012 extern __checkReturn efx_rc_t
3013 efx_filter_spec_set_rss_context(
3014 __inout efx_filter_spec_t *spec,
3015 __in uint32_t rss_context);
3017 #endif /* EFSYS_OPT_FILTER */
3021 extern __checkReturn uint32_t
3023 __in_ecount(count) uint32_t const *input,
3025 __in uint32_t init);
3027 extern __checkReturn uint32_t
3029 __in_ecount(length) uint8_t const *input,
3031 __in uint32_t init);
3033 #if EFSYS_OPT_LICENSING
3037 typedef struct efx_key_stats_s {
3039 uint32_t eks_invalid;
3040 uint32_t eks_blacklisted;
3041 uint32_t eks_unverifiable;
3042 uint32_t eks_wrong_node;
3043 uint32_t eks_licensed_apps_lo;
3044 uint32_t eks_licensed_apps_hi;
3045 uint32_t eks_licensed_features_lo;
3046 uint32_t eks_licensed_features_hi;
3049 extern __checkReturn efx_rc_t
3051 __in efx_nic_t *enp);
3055 __in efx_nic_t *enp);
3057 extern __checkReturn boolean_t
3058 efx_lic_check_support(
3059 __in efx_nic_t *enp);
3061 extern __checkReturn efx_rc_t
3062 efx_lic_update_licenses(
3063 __in efx_nic_t *enp);
3065 extern __checkReturn efx_rc_t
3066 efx_lic_get_key_stats(
3067 __in efx_nic_t *enp,
3068 __out efx_key_stats_t *ksp);
3070 extern __checkReturn efx_rc_t
3072 __in efx_nic_t *enp,
3073 __in uint64_t app_id,
3074 __out boolean_t *licensedp);
3076 extern __checkReturn efx_rc_t
3078 __in efx_nic_t *enp,
3079 __in size_t buffer_size,
3080 __out uint32_t *typep,
3081 __out size_t *lengthp,
3082 __out_opt uint8_t *bufferp);
3085 extern __checkReturn efx_rc_t
3087 __in efx_nic_t *enp,
3088 __in_bcount(buffer_size)
3090 __in size_t buffer_size,
3091 __out uint32_t *startp);
3093 extern __checkReturn efx_rc_t
3095 __in efx_nic_t *enp,
3096 __in_bcount(buffer_size)
3098 __in size_t buffer_size,
3099 __in uint32_t offset,
3100 __out uint32_t *endp);
3102 extern __checkReturn __success(return != B_FALSE) boolean_t
3104 __in efx_nic_t *enp,
3105 __in_bcount(buffer_size)
3107 __in size_t buffer_size,
3108 __in uint32_t offset,
3109 __out uint32_t *startp,
3110 __out uint32_t *lengthp);
3112 extern __checkReturn __success(return != B_FALSE) boolean_t
3113 efx_lic_validate_key(
3114 __in efx_nic_t *enp,
3115 __in_bcount(length) caddr_t keyp,
3116 __in uint32_t length);
3118 extern __checkReturn efx_rc_t
3120 __in efx_nic_t *enp,
3121 __in_bcount(buffer_size)
3123 __in size_t buffer_size,
3124 __in uint32_t offset,
3125 __in uint32_t length,
3126 __out_bcount_part(key_max_size, *lengthp)
3128 __in size_t key_max_size,
3129 __out uint32_t *lengthp);
3131 extern __checkReturn efx_rc_t
3133 __in efx_nic_t *enp,
3134 __in_bcount(buffer_size)
3136 __in size_t buffer_size,
3137 __in uint32_t offset,
3138 __in_bcount(length) caddr_t keyp,
3139 __in uint32_t length,
3140 __out uint32_t *lengthp);
3142 __checkReturn efx_rc_t
3144 __in efx_nic_t *enp,
3145 __in_bcount(buffer_size)
3147 __in size_t buffer_size,
3148 __in uint32_t offset,
3149 __in uint32_t length,
3151 __out uint32_t *deltap);
3153 extern __checkReturn efx_rc_t
3154 efx_lic_create_partition(
3155 __in efx_nic_t *enp,
3156 __in_bcount(buffer_size)
3158 __in size_t buffer_size);
3160 extern __checkReturn efx_rc_t
3161 efx_lic_finish_partition(
3162 __in efx_nic_t *enp,
3163 __in_bcount(buffer_size)
3165 __in size_t buffer_size);
3167 #endif /* EFSYS_OPT_LICENSING */
3171 #if EFSYS_OPT_TUNNEL
3173 extern __checkReturn efx_rc_t
3175 __in efx_nic_t *enp);
3179 __in efx_nic_t *enp);
3182 * For overlay network encapsulation using UDP, the firmware needs to know
3183 * the configured UDP port for the overlay so it can decode encapsulated
3185 * The UDP port/protocol list is global.
3188 extern __checkReturn efx_rc_t
3189 efx_tunnel_config_udp_add(
3190 __in efx_nic_t *enp,
3191 __in uint16_t port /* host/cpu-endian */,
3192 __in efx_tunnel_protocol_t protocol);
3194 extern __checkReturn efx_rc_t
3195 efx_tunnel_config_udp_remove(
3196 __in efx_nic_t *enp,
3197 __in uint16_t port /* host/cpu-endian */,
3198 __in efx_tunnel_protocol_t protocol);
3201 efx_tunnel_config_clear(
3202 __in efx_nic_t *enp);
3205 * Apply tunnel UDP ports configuration to hardware.
3207 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3210 extern __checkReturn efx_rc_t
3211 efx_tunnel_reconfigure(
3212 __in efx_nic_t *enp);
3214 #endif /* EFSYS_OPT_TUNNEL */
3216 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3219 * Firmware subvariant choice options.
3221 * It may be switched to no Tx checksum if attached drivers are either
3222 * preboot or firmware subvariant aware and no VIS are allocated.
3223 * If may be always switched to default explicitly using set request or
3224 * implicitly if unaware driver is attaching. If switching is done when
3225 * a driver is attached, it gets MC_REBOOT event and should recreate its
3228 * See SF-119419-TC DPDK Firmware Driver Interface and
3229 * SF-109306-TC EF10 for Driver Writers for details.
3231 typedef enum efx_nic_fw_subvariant_e {
3232 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3233 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3234 EFX_NIC_FW_SUBVARIANT_NTYPES
3235 } efx_nic_fw_subvariant_t;
3237 extern __checkReturn efx_rc_t
3238 efx_nic_get_fw_subvariant(
3239 __in efx_nic_t *enp,
3240 __out efx_nic_fw_subvariant_t *subvariantp);
3242 extern __checkReturn efx_rc_t
3243 efx_nic_set_fw_subvariant(
3244 __in efx_nic_t *enp,
3245 __in efx_nic_fw_subvariant_t subvariant);
3247 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3249 typedef enum efx_phy_fec_type_e {
3250 EFX_PHY_FEC_NONE = 0,
3253 } efx_phy_fec_type_t;
3255 extern __checkReturn efx_rc_t
3256 efx_phy_fec_type_get(
3257 __in efx_nic_t *enp,
3258 __out efx_phy_fec_type_t *typep);
3260 typedef struct efx_phy_link_state_s {
3261 uint32_t epls_adv_cap_mask;
3262 uint32_t epls_lp_cap_mask;
3263 uint32_t epls_ld_cap_mask;
3264 unsigned int epls_fcntl;
3265 efx_phy_fec_type_t epls_fec;
3266 efx_link_mode_t epls_link_mode;
3267 } efx_phy_link_state_t;
3269 extern __checkReturn efx_rc_t
3270 efx_phy_link_state_get(
3271 __in efx_nic_t *enp,
3272 __out efx_phy_link_state_t *eplsp);
3279 #endif /* _SYS_EFX_H */