1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if EFSYS_OPT_MEDFORD2
33 #include "medford2_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD2 */
36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
37 #include "ef10_impl.h"
38 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
44 #define EFX_MOD_MCDI 0x00000001
45 #define EFX_MOD_PROBE 0x00000002
46 #define EFX_MOD_NVRAM 0x00000004
47 #define EFX_MOD_VPD 0x00000008
48 #define EFX_MOD_NIC 0x00000010
49 #define EFX_MOD_INTR 0x00000020
50 #define EFX_MOD_EV 0x00000040
51 #define EFX_MOD_RX 0x00000080
52 #define EFX_MOD_TX 0x00000100
53 #define EFX_MOD_PORT 0x00000200
54 #define EFX_MOD_MON 0x00000400
55 #define EFX_MOD_FILTER 0x00001000
56 #define EFX_MOD_LIC 0x00002000
57 #define EFX_MOD_TUNNEL 0x00004000
59 #define EFX_RESET_PHY 0x00000001
60 #define EFX_RESET_RXQ_ERR 0x00000002
61 #define EFX_RESET_TXQ_ERR 0x00000004
62 #define EFX_RESET_HW_UNAVAIL 0x00000008
64 typedef enum efx_mac_type_e {
73 typedef struct efx_ev_ops_s {
74 efx_rc_t (*eevo_init)(efx_nic_t *);
75 void (*eevo_fini)(efx_nic_t *);
76 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
77 efsys_mem_t *, size_t, uint32_t,
78 uint32_t, uint32_t, efx_evq_t *);
79 void (*eevo_qdestroy)(efx_evq_t *);
80 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
81 void (*eevo_qpost)(efx_evq_t *, uint16_t);
82 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
84 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
88 typedef struct efx_tx_ops_s {
89 efx_rc_t (*etxo_init)(efx_nic_t *);
90 void (*etxo_fini)(efx_nic_t *);
91 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
92 unsigned int, unsigned int,
93 efsys_mem_t *, size_t,
95 efx_evq_t *, efx_txq_t *,
97 void (*etxo_qdestroy)(efx_txq_t *);
98 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
99 unsigned int, unsigned int,
101 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
102 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
103 efx_rc_t (*etxo_qflush)(efx_txq_t *);
104 void (*etxo_qenable)(efx_txq_t *);
105 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
106 void (*etxo_qpio_disable)(efx_txq_t *);
107 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
109 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
111 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
112 unsigned int, unsigned int,
114 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
117 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
120 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
121 uint16_t, uint32_t, uint16_t,
123 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
125 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
128 void (*etxo_qstats_update)(efx_txq_t *,
133 typedef union efx_rxq_type_data_u {
134 /* Dummy member to have non-empty union if no options are enabled */
136 #if EFSYS_OPT_RX_PACKED_STREAM
138 uint32_t eps_buf_size;
139 } ertd_packed_stream;
141 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
143 uint32_t eessb_bufs_per_desc;
144 uint32_t eessb_max_dma_len;
145 uint32_t eessb_buf_stride;
146 uint32_t eessb_hol_block_timeout;
147 } ertd_es_super_buffer;
149 } efx_rxq_type_data_t;
151 typedef struct efx_rx_ops_s {
152 efx_rc_t (*erxo_init)(efx_nic_t *);
153 void (*erxo_fini)(efx_nic_t *);
154 #if EFSYS_OPT_RX_SCATTER
155 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
157 #if EFSYS_OPT_RX_SCALE
158 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
159 efx_rx_scale_context_type_t,
160 uint32_t, uint32_t *);
161 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
162 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
164 efx_rx_hash_type_t, boolean_t);
165 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
167 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
168 unsigned int *, size_t);
169 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
171 #endif /* EFSYS_OPT_RX_SCALE */
172 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
174 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
175 unsigned int, unsigned int,
177 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
178 #if EFSYS_OPT_RX_PACKED_STREAM
179 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
180 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
182 uint16_t *, uint32_t *, uint32_t *);
184 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
185 void (*erxo_qenable)(efx_rxq_t *);
186 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
187 unsigned int, efx_rxq_type_t,
188 const efx_rxq_type_data_t *,
189 efsys_mem_t *, size_t, uint32_t,
191 efx_evq_t *, efx_rxq_t *);
192 void (*erxo_qdestroy)(efx_rxq_t *);
195 typedef struct efx_mac_ops_s {
196 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
197 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
198 efx_rc_t (*emo_addr_set)(efx_nic_t *);
199 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
200 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
201 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
202 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
203 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
204 efx_rxq_t *, boolean_t);
205 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
206 #if EFSYS_OPT_LOOPBACK
207 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
208 efx_loopback_type_t);
209 #endif /* EFSYS_OPT_LOOPBACK */
210 #if EFSYS_OPT_MAC_STATS
211 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
212 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
213 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
214 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
215 uint16_t, boolean_t);
216 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
217 efsys_stat_t *, uint32_t *);
218 #endif /* EFSYS_OPT_MAC_STATS */
221 typedef struct efx_phy_ops_s {
222 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
223 efx_rc_t (*epo_reset)(efx_nic_t *);
224 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
225 efx_rc_t (*epo_verify)(efx_nic_t *);
226 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
227 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
228 #if EFSYS_OPT_PHY_STATS
229 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
231 #endif /* EFSYS_OPT_PHY_STATS */
233 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
234 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
235 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
236 efx_bist_result_t *, uint32_t *,
237 unsigned long *, size_t);
238 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
239 #endif /* EFSYS_OPT_BIST */
243 typedef struct efx_filter_ops_s {
244 efx_rc_t (*efo_init)(efx_nic_t *);
245 void (*efo_fini)(efx_nic_t *);
246 efx_rc_t (*efo_restore)(efx_nic_t *);
247 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
248 boolean_t may_replace);
249 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
250 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
252 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
253 boolean_t, boolean_t, boolean_t,
254 uint8_t const *, uint32_t);
257 extern __checkReturn efx_rc_t
258 efx_filter_reconfigure(
260 __in_ecount(6) uint8_t const *mac_addr,
261 __in boolean_t all_unicst,
262 __in boolean_t mulcst,
263 __in boolean_t all_mulcst,
264 __in boolean_t brdcst,
265 __in_ecount(6*count) uint8_t const *addrs,
266 __in uint32_t count);
268 #endif /* EFSYS_OPT_FILTER */
271 typedef struct efx_tunnel_ops_s {
272 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
273 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
275 #endif /* EFSYS_OPT_TUNNEL */
277 typedef struct efx_port_s {
278 efx_mac_type_t ep_mac_type;
279 uint32_t ep_phy_type;
282 uint8_t ep_mac_addr[6];
283 efx_link_mode_t ep_link_mode;
284 boolean_t ep_all_unicst;
286 boolean_t ep_all_mulcst;
288 unsigned int ep_fcntl;
289 boolean_t ep_fcntl_autoneg;
290 efx_oword_t ep_multicst_hash[2];
291 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
292 EFX_MAC_MULTICAST_LIST_MAX];
293 uint32_t ep_mulcst_addr_count;
294 #if EFSYS_OPT_LOOPBACK
295 efx_loopback_type_t ep_loopback_type;
296 efx_link_mode_t ep_loopback_link_mode;
297 #endif /* EFSYS_OPT_LOOPBACK */
298 #if EFSYS_OPT_PHY_FLAGS
299 uint32_t ep_phy_flags;
300 #endif /* EFSYS_OPT_PHY_FLAGS */
301 #if EFSYS_OPT_PHY_LED_CONTROL
302 efx_phy_led_mode_t ep_phy_led_mode;
303 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
304 efx_phy_media_type_t ep_fixed_port_type;
305 efx_phy_media_type_t ep_module_type;
306 uint32_t ep_adv_cap_mask;
307 uint32_t ep_lp_cap_mask;
308 uint32_t ep_default_adv_cap_mask;
309 uint32_t ep_phy_cap_mask;
310 boolean_t ep_mac_drain;
312 efx_bist_type_t ep_current_bist;
314 const efx_mac_ops_t *ep_emop;
315 const efx_phy_ops_t *ep_epop;
318 typedef struct efx_mon_ops_s {
319 #if EFSYS_OPT_MON_STATS
320 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
321 efx_mon_stat_value_t *);
322 efx_rc_t (*emo_limits_update)(efx_nic_t *,
323 efx_mon_stat_limits_t *);
324 #endif /* EFSYS_OPT_MON_STATS */
327 typedef struct efx_mon_s {
328 efx_mon_type_t em_type;
329 const efx_mon_ops_t *em_emop;
332 typedef struct efx_intr_ops_s {
333 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
334 void (*eio_enable)(efx_nic_t *);
335 void (*eio_disable)(efx_nic_t *);
336 void (*eio_disable_unlocked)(efx_nic_t *);
337 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
338 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
339 void (*eio_status_message)(efx_nic_t *, unsigned int,
341 void (*eio_fatal)(efx_nic_t *);
342 void (*eio_fini)(efx_nic_t *);
345 typedef struct efx_intr_s {
346 const efx_intr_ops_t *ei_eiop;
347 efsys_mem_t *ei_esmp;
348 efx_intr_type_t ei_type;
349 unsigned int ei_level;
352 typedef struct efx_nic_ops_s {
353 efx_rc_t (*eno_probe)(efx_nic_t *);
354 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
355 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
356 efx_rc_t (*eno_reset)(efx_nic_t *);
357 efx_rc_t (*eno_init)(efx_nic_t *);
358 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
359 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
360 uint32_t *, size_t *);
361 boolean_t (*eno_hw_unavailable)(efx_nic_t *);
362 void (*eno_set_hw_unavailable)(efx_nic_t *);
364 efx_rc_t (*eno_register_test)(efx_nic_t *);
365 #endif /* EFSYS_OPT_DIAG */
366 void (*eno_fini)(efx_nic_t *);
367 void (*eno_unprobe)(efx_nic_t *);
370 #ifndef EFX_TXQ_LIMIT_TARGET
371 #define EFX_TXQ_LIMIT_TARGET 259
373 #ifndef EFX_RXQ_LIMIT_TARGET
374 #define EFX_RXQ_LIMIT_TARGET 512
382 typedef struct siena_filter_spec_s {
385 uint32_t sfs_dmaq_id;
386 uint32_t sfs_dword[3];
387 } siena_filter_spec_t;
389 typedef enum siena_filter_type_e {
390 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
391 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
392 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
393 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
394 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
395 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
397 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
398 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
399 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
400 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
401 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
402 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
404 EFX_SIENA_FILTER_NTYPES
405 } siena_filter_type_t;
407 typedef enum siena_filter_tbl_id_e {
408 EFX_SIENA_FILTER_TBL_RX_IP = 0,
409 EFX_SIENA_FILTER_TBL_RX_MAC,
410 EFX_SIENA_FILTER_TBL_TX_IP,
411 EFX_SIENA_FILTER_TBL_TX_MAC,
412 EFX_SIENA_FILTER_NTBLS
413 } siena_filter_tbl_id_t;
415 typedef struct siena_filter_tbl_s {
416 int sft_size; /* number of entries */
417 int sft_used; /* active count */
418 uint32_t *sft_bitmap; /* active bitmap */
419 siena_filter_spec_t *sft_spec; /* array of saved specs */
420 } siena_filter_tbl_t;
422 typedef struct siena_filter_s {
423 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
424 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
427 #endif /* EFSYS_OPT_SIENA */
429 typedef struct efx_filter_s {
431 siena_filter_t *ef_siena_filter;
432 #endif /* EFSYS_OPT_SIENA */
433 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
434 ef10_filter_table_t *ef_ef10_filter_table;
435 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
441 siena_filter_tbl_clear(
443 __in siena_filter_tbl_id_t tbl);
445 #endif /* EFSYS_OPT_SIENA */
447 #endif /* EFSYS_OPT_FILTER */
451 #define EFX_TUNNEL_MAXNENTRIES (16)
455 typedef struct efx_tunnel_udp_entry_s {
456 uint16_t etue_port; /* host/cpu-endian */
457 uint16_t etue_protocol;
458 } efx_tunnel_udp_entry_t;
460 typedef struct efx_tunnel_cfg_s {
461 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
462 unsigned int etc_udp_entries_num;
465 #endif /* EFSYS_OPT_TUNNEL */
467 typedef struct efx_mcdi_ops_s {
468 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
469 void (*emco_send_request)(efx_nic_t *, void *, size_t,
471 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
472 boolean_t (*emco_poll_response)(efx_nic_t *);
473 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
474 void (*emco_fini)(efx_nic_t *);
475 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
476 efx_mcdi_feature_id_t, boolean_t *);
477 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
481 typedef struct efx_mcdi_s {
482 const efx_mcdi_ops_t *em_emcop;
483 const efx_mcdi_transport_t *em_emtp;
484 efx_mcdi_iface_t em_emip;
487 #endif /* EFSYS_OPT_MCDI */
491 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
492 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
494 typedef struct efx_nvram_ops_s {
496 efx_rc_t (*envo_test)(efx_nic_t *);
497 #endif /* EFSYS_OPT_DIAG */
498 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
500 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
501 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
502 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
503 unsigned int, caddr_t, size_t);
504 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
505 unsigned int, caddr_t, size_t);
506 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
507 unsigned int, size_t);
508 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
509 unsigned int, caddr_t, size_t);
510 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
512 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
513 uint32_t *, uint16_t *);
514 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
516 efx_rc_t (*envo_buffer_validate)(uint32_t,
519 #endif /* EFSYS_OPT_NVRAM */
522 typedef struct efx_vpd_ops_s {
523 efx_rc_t (*evpdo_init)(efx_nic_t *);
524 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
525 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
526 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
527 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
528 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
530 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
532 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
533 efx_vpd_value_t *, unsigned int *);
534 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
535 void (*evpdo_fini)(efx_nic_t *);
537 #endif /* EFSYS_OPT_VPD */
539 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
541 __checkReturn efx_rc_t
542 efx_mcdi_nvram_partitions(
544 __out_bcount(size) caddr_t data,
546 __out unsigned int *npartnp);
548 __checkReturn efx_rc_t
549 efx_mcdi_nvram_metadata(
552 __out uint32_t *subtypep,
553 __out_ecount(4) uint16_t version[4],
554 __out_bcount_opt(size) char *descp,
557 __checkReturn efx_rc_t
561 __out_opt size_t *sizep,
562 __out_opt uint32_t *addressp,
563 __out_opt uint32_t *erase_sizep,
564 __out_opt uint32_t *write_sizep);
566 __checkReturn efx_rc_t
567 efx_mcdi_nvram_update_start(
569 __in uint32_t partn);
571 __checkReturn efx_rc_t
575 __in uint32_t offset,
576 __out_bcount(size) caddr_t data,
580 __checkReturn efx_rc_t
581 efx_mcdi_nvram_erase(
584 __in uint32_t offset,
587 __checkReturn efx_rc_t
588 efx_mcdi_nvram_write(
591 __in uint32_t offset,
592 __in_bcount(size) caddr_t data,
595 __checkReturn efx_rc_t
596 efx_mcdi_nvram_update_finish(
599 __in boolean_t reboot,
600 __out_opt uint32_t *verify_resultp);
604 __checkReturn efx_rc_t
607 __in uint32_t partn);
609 #endif /* EFSYS_OPT_DIAG */
611 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
613 #if EFSYS_OPT_LICENSING
615 typedef struct efx_lic_ops_s {
616 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
617 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
618 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
619 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
620 size_t *, uint8_t *);
621 efx_rc_t (*elo_find_start)
622 (efx_nic_t *, caddr_t, size_t, uint32_t *);
623 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
624 uint32_t, uint32_t *);
625 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
626 uint32_t, uint32_t *, uint32_t *);
627 boolean_t (*elo_validate_key)(efx_nic_t *,
629 efx_rc_t (*elo_read_key)(efx_nic_t *,
630 caddr_t, size_t, uint32_t, uint32_t,
631 caddr_t, size_t, uint32_t *);
632 efx_rc_t (*elo_write_key)(efx_nic_t *,
633 caddr_t, size_t, uint32_t,
634 caddr_t, uint32_t, uint32_t *);
635 efx_rc_t (*elo_delete_key)(efx_nic_t *,
636 caddr_t, size_t, uint32_t,
637 uint32_t, uint32_t, uint32_t *);
638 efx_rc_t (*elo_create_partition)(efx_nic_t *,
640 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
646 typedef struct efx_drv_cfg_s {
647 uint32_t edc_min_vi_count;
648 uint32_t edc_max_vi_count;
650 uint32_t edc_max_piobuf_count;
651 uint32_t edc_pio_alloc_size;
656 efx_family_t en_family;
657 uint32_t en_features;
658 efsys_identifier_t *en_esip;
659 efsys_lock_t *en_eslp;
660 efsys_bar_t *en_esbp;
661 unsigned int en_mod_flags;
662 unsigned int en_reset_flags;
663 efx_nic_cfg_t en_nic_cfg;
664 efx_drv_cfg_t en_drv_cfg;
668 uint32_t en_ev_qcount;
669 uint32_t en_rx_qcount;
670 uint32_t en_tx_qcount;
671 const efx_nic_ops_t *en_enop;
672 const efx_ev_ops_t *en_eevop;
673 const efx_tx_ops_t *en_etxop;
674 const efx_rx_ops_t *en_erxop;
675 efx_fw_variant_t efv;
677 efx_filter_t en_filter;
678 const efx_filter_ops_t *en_efop;
679 #endif /* EFSYS_OPT_FILTER */
681 efx_tunnel_cfg_t en_tunnel_cfg;
682 const efx_tunnel_ops_t *en_etop;
683 #endif /* EFSYS_OPT_TUNNEL */
686 #endif /* EFSYS_OPT_MCDI */
688 uint32_t en_nvram_partn_locked;
689 const efx_nvram_ops_t *en_envop;
690 #endif /* EFSYS_OPT_NVRAM */
692 const efx_vpd_ops_t *en_evpdop;
693 #endif /* EFSYS_OPT_VPD */
694 #if EFSYS_OPT_RX_SCALE
695 efx_rx_hash_support_t en_hash_support;
696 efx_rx_scale_context_type_t en_rss_context_type;
697 uint32_t en_rss_context;
698 #endif /* EFSYS_OPT_RX_SCALE */
699 uint32_t en_vport_id;
700 #if EFSYS_OPT_LICENSING
701 const efx_lic_ops_t *en_elop;
702 boolean_t en_licensing_supported;
707 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
708 unsigned int enu_partn_mask;
709 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
712 size_t enu_svpd_length;
713 #endif /* EFSYS_OPT_VPD */
716 #endif /* EFSYS_OPT_SIENA */
719 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
727 size_t ena_svpd_length;
728 #endif /* EFSYS_OPT_VPD */
729 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
730 uint32_t ena_piobuf_count;
731 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
732 uint32_t ena_pio_write_vi_base;
733 /* Memory BAR mapping regions */
734 uint32_t ena_uc_mem_map_offset;
735 size_t ena_uc_mem_map_size;
736 uint32_t ena_wc_mem_map_offset;
737 size_t ena_wc_mem_map_size;
740 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
744 #define EFX_NIC_MAGIC 0x02121996
746 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
747 const efx_ev_callbacks_t *, void *);
749 typedef struct efx_evq_rxq_state_s {
750 unsigned int eers_rx_read_ptr;
751 unsigned int eers_rx_mask;
752 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
753 unsigned int eers_rx_stream_npackets;
754 boolean_t eers_rx_packed_stream;
756 #if EFSYS_OPT_RX_PACKED_STREAM
757 unsigned int eers_rx_packed_stream_credits;
759 } efx_evq_rxq_state_t;
764 unsigned int ee_index;
765 unsigned int ee_mask;
766 efsys_mem_t *ee_esmp;
768 uint32_t ee_stat[EV_NQSTATS];
769 #endif /* EFSYS_OPT_QSTATS */
771 efx_ev_handler_t ee_rx;
772 efx_ev_handler_t ee_tx;
773 efx_ev_handler_t ee_driver;
774 efx_ev_handler_t ee_global;
775 efx_ev_handler_t ee_drv_gen;
777 efx_ev_handler_t ee_mcdi;
778 #endif /* EFSYS_OPT_MCDI */
780 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
785 #define EFX_EVQ_MAGIC 0x08081997
787 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
793 unsigned int er_index;
794 unsigned int er_label;
795 unsigned int er_mask;
796 efsys_mem_t *er_esmp;
797 efx_evq_rxq_state_t *er_ev_qstate;
800 #define EFX_RXQ_MAGIC 0x15022005
805 unsigned int et_index;
806 unsigned int et_mask;
807 efsys_mem_t *et_esmp;
808 #if EFSYS_OPT_HUNTINGTON
809 uint32_t et_pio_bufnum;
810 uint32_t et_pio_blknum;
811 uint32_t et_pio_write_offset;
812 uint32_t et_pio_offset;
816 uint32_t et_stat[TX_NQSTATS];
817 #endif /* EFSYS_OPT_QSTATS */
820 #define EFX_TXQ_MAGIC 0x05092005
822 #define EFX_MAC_ADDR_COPY(_dst, _src) \
824 (_dst)[0] = (_src)[0]; \
825 (_dst)[1] = (_src)[1]; \
826 (_dst)[2] = (_src)[2]; \
827 (_dst)[3] = (_src)[3]; \
828 (_dst)[4] = (_src)[4]; \
829 (_dst)[5] = (_src)[5]; \
830 _NOTE(CONSTANTCONDITION) \
833 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
835 uint16_t *_d = (uint16_t *)(_dst); \
839 _NOTE(CONSTANTCONDITION) \
842 #if EFSYS_OPT_CHECK_REG
843 #define EFX_CHECK_REG(_enp, _reg) \
845 const char *name = #_reg; \
846 char min = name[4]; \
847 char max = name[5]; \
850 switch ((_enp)->en_family) { \
851 case EFX_FAMILY_SIENA: \
855 case EFX_FAMILY_HUNTINGTON: \
859 case EFX_FAMILY_MEDFORD: \
863 case EFX_FAMILY_MEDFORD2: \
872 EFSYS_ASSERT3S(rev, >=, min); \
873 EFSYS_ASSERT3S(rev, <=, max); \
875 _NOTE(CONSTANTCONDITION) \
878 #define EFX_CHECK_REG(_enp, _reg) do { \
879 _NOTE(CONSTANTCONDITION) \
883 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
885 EFX_CHECK_REG((_enp), (_reg)); \
886 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
888 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
889 uint32_t, _reg ## _OFST, \
890 uint32_t, (_edp)->ed_u32[0]); \
891 _NOTE(CONSTANTCONDITION) \
894 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
896 EFX_CHECK_REG((_enp), (_reg)); \
897 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
898 uint32_t, _reg ## _OFST, \
899 uint32_t, (_edp)->ed_u32[0]); \
900 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
902 _NOTE(CONSTANTCONDITION) \
905 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
907 EFX_CHECK_REG((_enp), (_reg)); \
908 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
910 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
911 uint32_t, _reg ## _OFST, \
912 uint32_t, (_eqp)->eq_u32[1], \
913 uint32_t, (_eqp)->eq_u32[0]); \
914 _NOTE(CONSTANTCONDITION) \
917 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
919 EFX_CHECK_REG((_enp), (_reg)); \
920 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
921 uint32_t, _reg ## _OFST, \
922 uint32_t, (_eqp)->eq_u32[1], \
923 uint32_t, (_eqp)->eq_u32[0]); \
924 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
926 _NOTE(CONSTANTCONDITION) \
929 #define EFX_BAR_READO(_enp, _reg, _eop) \
931 EFX_CHECK_REG((_enp), (_reg)); \
932 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
934 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
935 uint32_t, _reg ## _OFST, \
936 uint32_t, (_eop)->eo_u32[3], \
937 uint32_t, (_eop)->eo_u32[2], \
938 uint32_t, (_eop)->eo_u32[1], \
939 uint32_t, (_eop)->eo_u32[0]); \
940 _NOTE(CONSTANTCONDITION) \
943 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
945 EFX_CHECK_REG((_enp), (_reg)); \
946 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
947 uint32_t, _reg ## _OFST, \
948 uint32_t, (_eop)->eo_u32[3], \
949 uint32_t, (_eop)->eo_u32[2], \
950 uint32_t, (_eop)->eo_u32[1], \
951 uint32_t, (_eop)->eo_u32[0]); \
952 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
954 _NOTE(CONSTANTCONDITION) \
958 * Accessors for memory BAR non-VI tables.
960 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
961 * to ensure the correct runtime VI window size is used on Medford2.
963 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
966 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
968 EFX_CHECK_REG((_enp), (_reg)); \
969 EFSYS_BAR_READD((_enp)->en_esbp, \
970 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
972 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
973 uint32_t, (_index), \
974 uint32_t, _reg ## _OFST, \
975 uint32_t, (_edp)->ed_u32[0]); \
976 _NOTE(CONSTANTCONDITION) \
979 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
981 EFX_CHECK_REG((_enp), (_reg)); \
982 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
983 uint32_t, (_index), \
984 uint32_t, _reg ## _OFST, \
985 uint32_t, (_edp)->ed_u32[0]); \
986 EFSYS_BAR_WRITED((_enp)->en_esbp, \
987 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
989 _NOTE(CONSTANTCONDITION) \
992 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
994 EFX_CHECK_REG((_enp), (_reg)); \
995 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
996 uint32_t, (_index), \
997 uint32_t, _reg ## _OFST, \
998 uint32_t, (_edp)->ed_u32[0]); \
999 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1001 (3 * sizeof (efx_dword_t)) + \
1002 ((_index) * _reg ## _STEP)), \
1004 _NOTE(CONSTANTCONDITION) \
1007 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
1009 EFX_CHECK_REG((_enp), (_reg)); \
1010 EFSYS_BAR_READQ((_enp)->en_esbp, \
1011 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1013 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
1014 uint32_t, (_index), \
1015 uint32_t, _reg ## _OFST, \
1016 uint32_t, (_eqp)->eq_u32[1], \
1017 uint32_t, (_eqp)->eq_u32[0]); \
1018 _NOTE(CONSTANTCONDITION) \
1021 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1023 EFX_CHECK_REG((_enp), (_reg)); \
1024 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1025 uint32_t, (_index), \
1026 uint32_t, _reg ## _OFST, \
1027 uint32_t, (_eqp)->eq_u32[1], \
1028 uint32_t, (_eqp)->eq_u32[0]); \
1029 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1030 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1032 _NOTE(CONSTANTCONDITION) \
1035 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1037 EFX_CHECK_REG((_enp), (_reg)); \
1038 EFSYS_BAR_READO((_enp)->en_esbp, \
1039 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1041 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1042 uint32_t, (_index), \
1043 uint32_t, _reg ## _OFST, \
1044 uint32_t, (_eop)->eo_u32[3], \
1045 uint32_t, (_eop)->eo_u32[2], \
1046 uint32_t, (_eop)->eo_u32[1], \
1047 uint32_t, (_eop)->eo_u32[0]); \
1048 _NOTE(CONSTANTCONDITION) \
1051 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1053 EFX_CHECK_REG((_enp), (_reg)); \
1054 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1055 uint32_t, (_index), \
1056 uint32_t, _reg ## _OFST, \
1057 uint32_t, (_eop)->eo_u32[3], \
1058 uint32_t, (_eop)->eo_u32[2], \
1059 uint32_t, (_eop)->eo_u32[1], \
1060 uint32_t, (_eop)->eo_u32[0]); \
1061 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1062 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1064 _NOTE(CONSTANTCONDITION) \
1068 * Accessors for memory BAR per-VI registers.
1070 * The VI window size is 8KB for Medford and all earlier controllers.
1071 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1074 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1076 EFX_CHECK_REG((_enp), (_reg)); \
1077 EFSYS_BAR_READD((_enp)->en_esbp, \
1078 ((_reg ## _OFST) + \
1079 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1081 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1082 uint32_t, (_index), \
1083 uint32_t, _reg ## _OFST, \
1084 uint32_t, (_edp)->ed_u32[0]); \
1085 _NOTE(CONSTANTCONDITION) \
1088 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1090 EFX_CHECK_REG((_enp), (_reg)); \
1091 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1092 uint32_t, (_index), \
1093 uint32_t, _reg ## _OFST, \
1094 uint32_t, (_edp)->ed_u32[0]); \
1095 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1096 ((_reg ## _OFST) + \
1097 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1099 _NOTE(CONSTANTCONDITION) \
1102 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1104 EFX_CHECK_REG((_enp), (_reg)); \
1105 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1106 uint32_t, (_index), \
1107 uint32_t, _reg ## _OFST, \
1108 uint32_t, (_edp)->ed_u32[0]); \
1109 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1110 ((_reg ## _OFST) + \
1111 (2 * sizeof (efx_dword_t)) + \
1112 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1114 _NOTE(CONSTANTCONDITION) \
1118 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1119 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1120 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1121 * the need for locking in the host, and are the only ones known to be safe to
1122 * use 128-bites write with.
1124 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1126 EFX_CHECK_REG((_enp), (_reg)); \
1127 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1128 const char *, #_reg, \
1129 uint32_t, (_index), \
1130 uint32_t, _reg ## _OFST, \
1131 uint32_t, (_eop)->eo_u32[3], \
1132 uint32_t, (_eop)->eo_u32[2], \
1133 uint32_t, (_eop)->eo_u32[1], \
1134 uint32_t, (_eop)->eo_u32[0]); \
1135 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1137 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1139 _NOTE(CONSTANTCONDITION) \
1142 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1144 unsigned int _new = (_wptr); \
1145 unsigned int _old = (_owptr); \
1147 if ((_new) >= (_old)) \
1148 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1149 (_old) * sizeof (efx_desc_t), \
1150 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1153 * It is cheaper to sync entire map than sync \
1154 * two parts especially when offset/size are \
1155 * ignored and entire map is synced in any case.\
1157 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1159 (_entries) * sizeof (efx_desc_t)); \
1160 _NOTE(CONSTANTCONDITION) \
1163 extern __checkReturn efx_rc_t
1165 __in efx_nic_t *enp);
1168 efx_mac_multicast_hash_compute(
1169 __in_ecount(6*count) uint8_t const *addrs,
1171 __out efx_oword_t *hash_low,
1172 __out efx_oword_t *hash_high);
1174 extern __checkReturn efx_rc_t
1176 __in efx_nic_t *enp);
1180 __in efx_nic_t *enp);
1184 /* VPD utility functions */
1186 extern __checkReturn efx_rc_t
1187 efx_vpd_hunk_length(
1188 __in_bcount(size) caddr_t data,
1190 __out size_t *lengthp);
1192 extern __checkReturn efx_rc_t
1193 efx_vpd_hunk_verify(
1194 __in_bcount(size) caddr_t data,
1196 __out_opt boolean_t *cksummedp);
1198 extern __checkReturn efx_rc_t
1199 efx_vpd_hunk_reinit(
1200 __in_bcount(size) caddr_t data,
1202 __in boolean_t wantpid);
1204 extern __checkReturn efx_rc_t
1206 __in_bcount(size) caddr_t data,
1208 __in efx_vpd_tag_t tag,
1209 __in efx_vpd_keyword_t keyword,
1210 __out unsigned int *payloadp,
1211 __out uint8_t *paylenp);
1213 extern __checkReturn efx_rc_t
1215 __in_bcount(size) caddr_t data,
1217 __out efx_vpd_tag_t *tagp,
1218 __out efx_vpd_keyword_t *keyword,
1219 __out_opt unsigned int *payloadp,
1220 __out_opt uint8_t *paylenp,
1221 __inout unsigned int *contp);
1223 extern __checkReturn efx_rc_t
1225 __in_bcount(size) caddr_t data,
1227 __in efx_vpd_value_t *evvp);
1229 #endif /* EFSYS_OPT_VPD */
1233 extern __checkReturn efx_rc_t
1234 efx_mcdi_set_workaround(
1235 __in efx_nic_t *enp,
1237 __in boolean_t enabled,
1238 __out_opt uint32_t *flagsp);
1240 extern __checkReturn efx_rc_t
1241 efx_mcdi_get_workarounds(
1242 __in efx_nic_t *enp,
1243 __out_opt uint32_t *implementedp,
1244 __out_opt uint32_t *enabledp);
1246 #endif /* EFSYS_OPT_MCDI */
1248 #if EFSYS_OPT_MAC_STATS
1251 * Closed range of stats (i.e. the first and the last are included).
1252 * The last must be greater or equal (if the range is one item only) to
1255 struct efx_mac_stats_range {
1256 efx_mac_stat_t first;
1257 efx_mac_stat_t last;
1261 efx_mac_stats_mask_add_ranges(
1262 __inout_bcount(mask_size) uint32_t *maskp,
1263 __in size_t mask_size,
1264 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1265 __in unsigned int rng_count);
1267 #endif /* EFSYS_OPT_MAC_STATS */
1273 #endif /* _SYS_EFX_IMPL_H */