1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
5 #ifndef _IFPGA_DEFINES_H_
6 #define _IFPGA_DEFINES_H_
8 #include "ifpga_compat.h"
10 #define MAX_FPGA_PORT_NUM 4
12 #define FME_FEATURE_HEADER "fme_hdr"
13 #define FME_FEATURE_THERMAL_MGMT "fme_thermal"
14 #define FME_FEATURE_POWER_MGMT "fme_power"
15 #define FME_FEATURE_GLOBAL_IPERF "fme_iperf"
16 #define FME_FEATURE_GLOBAL_ERR "fme_error"
17 #define FME_FEATURE_PR_MGMT "fme_pr"
18 #define FME_FEATURE_HSSI_ETH "fme_hssi"
19 #define FME_FEATURE_GLOBAL_DPERF "fme_dperf"
20 #define FME_FEATURE_QSPI_FLASH "fme_qspi_flash"
22 #define PORT_FEATURE_HEADER "port_hdr"
23 #define PORT_FEATURE_UAFU "port_uafu"
24 #define PORT_FEATURE_ERR "port_err"
25 #define PORT_FEATURE_UMSG "port_umsg"
26 #define PORT_FEATURE_PR "port_pr"
27 #define PORT_FEATURE_UINT "port_uint"
28 #define PORT_FEATURE_STP "port_stp"
31 * do not check the revision id as id may be dynamic under
32 * some cases, e.g, UAFU.
34 #define SKIP_REVISION_CHECK 0xff
36 #define FME_HEADER_REVISION 1
37 #define FME_THERMAL_MGMT_REVISION 0
38 #define FME_POWER_MGMT_REVISION 1
39 #define FME_GLOBAL_IPERF_REVISION 1
40 #define FME_GLOBAL_ERR_REVISION 1
41 #define FME_PR_MGMT_REVISION 2
42 #define FME_HSSI_ETH_REVISION 0
43 #define FME_GLOBAL_DPERF_REVISION 0
44 #define FME_QSPI_REVISION 0
46 #define PORT_HEADER_REVISION 0
47 /* UAFU's header info depends on the downloaded GBS */
48 #define PORT_UAFU_REVISION SKIP_REVISION_CHECK
49 #define PORT_ERR_REVISION 1
50 #define PORT_UMSG_REVISION 0
51 #define PORT_UINT_REVISION 0
52 #define PORT_STP_REVISION 1
54 #define FEATURE_TYPE_AFU 0x1
55 #define FEATURE_TYPE_BBB 0x2
56 #define FEATURE_TYPE_PRIVATE 0x3
57 #define FEATURE_TYPE_FIU 0x4
59 #define FEATURE_FIU_ID_FME 0x0
60 #define FEATURE_FIU_ID_PORT 0x1
62 #define FEATURE_ID_HEADER 0x0
63 #define FEATURE_ID_AFU 0xff
72 FME_FEATURE_ID_HEADER = 0x0,
74 FME_FEATURE_ID_THERMAL_MGMT = 0x1,
75 FME_FEATURE_ID_POWER_MGMT = 0x2,
76 FME_FEATURE_ID_GLOBAL_IPERF = 0x3,
77 FME_FEATURE_ID_GLOBAL_ERR = 0x4,
78 FME_FEATURE_ID_PR_MGMT = 0x5,
79 FME_FEATURE_ID_HSSI_ETH = 0x6,
80 FME_FEATURE_ID_GLOBAL_DPERF = 0x7,
81 FME_FEATURE_ID_QSPI_FLASH = 0x8,
83 /* one for fme header. */
84 FME_FEATURE_ID_MAX = 0x9,
87 enum port_feature_id {
88 PORT_FEATURE_ID_HEADER = 0x0,
89 PORT_FEATURE_ID_ERROR = 0x1,
90 PORT_FEATURE_ID_UMSG = 0x2,
91 PORT_FEATURE_ID_UINT = 0x3,
92 PORT_FEATURE_ID_STP = 0x4,
93 PORT_FEATURE_ID_UAFU = 0x5,
94 PORT_FEATURE_ID_MAX = 0x6,
98 * All headers and structures must be byte-packed to match the spec.
100 #pragma pack(push, 1)
102 struct feature_header {
108 u32 next_header_offset:24;
116 struct feature_bbb_header {
120 struct feature_afu_header {
131 struct feature_fiu_header {
142 struct feature_fme_capability {
146 u8 fabric_verid; /* Fabric version ID */
147 u8 socket_id:1; /* Socket id */
148 u8 rsvd1:3; /* Reserved */
149 /* pci0 link available yes /no */
150 u8 pci0_link_avile:1;
151 /* pci1 link available yes /no */
152 u8 pci1_link_avile:1;
153 /* Coherent (QPI/UPI) link available yes /no */
155 u8 rsvd2:1; /* Reserved */
156 /* IOMMU or VT-d supported yes/no */
158 u8 num_ports:3; /* Number of ports */
159 u8 sf_fab_ctl:1; /* Internal validation bit */
160 u8 rsvd3:3; /* Reserved */
162 * Address width supported in bits
163 * BXT -0x26 , SKX -0x30
165 u8 address_width_bits:6;
166 u8 rsvd4:2; /* Reserved */
167 /* Size of cache supported in kb */
169 u8 cache_assoc:4; /* Cache Associativity */
170 u16 rsvd5:15; /* Reserved */
171 u8 lock_bit:1; /* Lock bit */
176 #define FME_AFU_ACCESS_PF 0
177 #define FME_AFU_ACCESS_VF 1
179 struct feature_fme_port {
187 u8 afu_access_control:1;
189 u8 port_implemented:1;
195 struct feature_fme_fab_status {
199 u8 upilink_status:4; /* UPI Link Status */
200 u8 rsvd1:4; /* Reserved */
201 u8 pci0link_status:1; /* pci0 link status */
202 u8 rsvd2:3; /* Reserved */
203 u8 pci1link_status:1; /* pci1 link status */
204 u64 rsvd3:51; /* Reserved */
209 struct feature_fme_genprotrange2_base {
213 u16 rsvd1; /* Reserved */
214 /* Base Address of memory range */
215 u8 protected_base_addrss:4;
216 u64 rsvd2:44; /* Reserved */
221 struct feature_fme_genprotrange2_limit {
225 u16 rsvd1; /* Reserved */
226 /* Limit Address of memory range */
227 u8 protected_limit_addrss:4;
228 u16 rsvd2:11; /* Reserved */
229 u8 enable:1; /* Enable GENPROTRANGE check */
230 u32 rsvd3; /* Reserved */
235 struct feature_fme_dxe_lock {
240 * Determines write access to the DXE region CSRs
241 * 1 - CSR region is locked;
242 * 0 - it is open for write access.
246 * Determines write access to the HSSI CSR
247 * 1 - CSR region is locked;
248 * 0 - it is open for write access.
256 #define HSSI_ID_NO_HASSI 0
257 #define HSSI_ID_PCIE_RP 1
258 #define HSSI_ID_ETHERNET 2
260 struct feature_fme_bitstream_id {
264 u32 gitrepo_hash:32; /* GIT repository hash */
266 * HSSI configuration identifier:
272 u16 rsvd1:12; /* Reserved */
273 /* Bitstream version patch number */
275 /* Bitstream version minor number */
277 /* Bitstream version major number */
279 /* Bitstream version debug number */
285 struct feature_fme_bitstream_md {
289 /* Seed number userd for synthesis flow */
291 /* Synthesis date(day number - 2 digits) */
293 /* Synthesis date(month number - 2 digits) */
295 /* Synthesis date(year number - 2 digits) */
297 u64 rsvd:36; /* Reserved */
302 struct feature_fme_iommu_ctrl {
306 /* Disables IOMMU prefetcher for C0 channel */
307 u8 prefetch_disableC0:1;
308 /* Disables IOMMU prefetcher for C1 channel */
309 u8 prefetch_disableC1:1;
310 /* Disables IOMMU partial cache line writes */
311 u8 prefetch_wrdisable:1;
312 u8 rsvd1:1; /* Reserved */
314 * Select counter and read value from register
315 * iommu_stat.dbg_counters
316 * 0 - Number of 4K page translation response
317 * 1 - Number of 2M page translation response
318 * 2 - Number of 1G page translation response
321 u32 rsvd2:26; /* Reserved */
322 /* Connected to IOMMU SIP Capabilities */
323 u32 capecap_defeature;
328 struct feature_fme_iommu_stat {
332 /* Translation Enable bit from IOMMU SIP */
333 u8 translation_enable:1;
334 /* Drain request in progress */
335 u8 drain_req_inprog:1;
336 /* Invalidation current state */
338 /* C0 Response Buffer current state */
339 u8 respbuffer_stateC0:3;
340 /* C1 Response Buffer current state */
341 u8 respbuffer_stateC1:3;
342 /* Last request ID to IOMMU SIP */
344 /* Last IOMMU SIP response ID value */
346 /* Last IOMMU SIP response status value */
347 u8 last_respstatus:3;
348 /* C0 Transaction Buffer is not empty */
349 u8 transbuf_notEmptyC0:1;
350 /* C1 Transaction Buffer is not empty */
351 u8 transbuf_notEmptyC1:1;
352 /* C0 Request FIFO is not empty */
353 u8 reqFIFO_notemptyC0:1;
354 /* C1 Request FIFO is not empty */
355 u8 reqFIFO_notemptyC1:1;
356 /* C0 Response FIFO is not empty */
357 u8 respFIFO_notemptyC0:1;
358 /* C1 Response FIFO is not empty */
359 u8 respFIFO_notemptyC1:1;
360 /* C0 Response FIFO overflow detected */
361 u8 respFIFO_overflowC0:1;
362 /* C1 Response FIFO overflow detected */
363 u8 respFIFO_overflowC1:1;
364 /* C0 Transaction Buffer overflow detected */
365 u8 tranbuf_overflowC0:1;
366 /* C1 Transaction Buffer overflow detected */
367 u8 tranbuf_overflowC1:1;
368 /* Request FIFO overflow detected */
369 u8 reqFIFO_overflow:1;
370 /* IOMMU memory read in progress */
372 /* IOMMU memory write in progress */
374 u8 rsvd1:1; /* Reserved */
375 /* Value of counter selected by iommu_ctl.counter_sel */
377 u16 rsvd2:12; /* Reserved */
382 struct feature_fme_pcie0_ctrl {
386 u64 vtd_bar_lock:1; /* Lock VT-D BAR register */
388 u64 rciep:1; /* Configure PCIE0 as RCiEP */
394 struct feature_fme_llpr_smrr_base {
399 u64 base:20; /* SMRR2 memory range base address */
405 struct feature_fme_llpr_smrr_mask {
410 u64 valid:1; /* LLPR_SMRR rule is valid or not */
412 * SMRR memory range mask which determines the range
413 * of region being mapped
421 struct feature_fme_llpr_smrr2_base {
426 u64 base:20; /* SMRR2 memory range base address */
432 struct feature_fme_llpr_smrr2_mask {
437 u64 valid:1; /* LLPR_SMRR2 rule is valid or not */
439 * SMRR2 memory range mask which determines the range
440 * of region being mapped
448 struct feature_fme_llpr_meseg_base {
452 /* A[45:19] of base address memory range */
459 struct feature_fme_llpr_meseg_limit {
463 /* A[45:19] of limit address memory range */
466 u64 enable:1; /* Enable LLPR MESEG rule */
472 struct feature_fme_header {
473 struct feature_header header;
474 struct feature_afu_header afu_header;
477 struct feature_fme_capability capability;
478 struct feature_fme_port port[MAX_FPGA_PORT_NUM];
479 struct feature_fme_fab_status fab_status;
480 struct feature_fme_bitstream_id bitstream_id;
481 struct feature_fme_bitstream_md bitstream_md;
482 struct feature_fme_genprotrange2_base genprotrange2_base;
483 struct feature_fme_genprotrange2_limit genprotrange2_limit;
484 struct feature_fme_dxe_lock dxe_lock;
485 struct feature_fme_iommu_ctrl iommu_ctrl;
486 struct feature_fme_iommu_stat iommu_stat;
487 struct feature_fme_pcie0_ctrl pcie0_control;
488 struct feature_fme_llpr_smrr_base smrr_base;
489 struct feature_fme_llpr_smrr_mask smrr_mask;
490 struct feature_fme_llpr_smrr2_base smrr2_base;
491 struct feature_fme_llpr_smrr2_mask smrr2_mask;
492 struct feature_fme_llpr_meseg_base meseg_base;
493 struct feature_fme_llpr_meseg_limit meseg_limit;
496 struct feature_port_capability {
500 u8 port_number:2; /* Port Number 0-3 */
501 u8 rsvd1:6; /* Reserved */
502 u16 mmio_size; /* User MMIO size in KB */
503 u8 rsvd2; /* Reserved */
504 u8 sp_intr_num:4; /* Supported interrupts num */
505 u32 rsvd3:28; /* Reserved */
510 struct feature_port_control {
514 u8 port_sftrst:1; /* Port Soft Reset */
515 u8 rsvd1:1; /* Reserved */
516 u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
517 u8 rsvd2:1; /* Reserved */
518 u8 port_sftrst_ack:1; /* HW ACK for Soft Reset */
519 u64 rsvd3:59; /* Reserved */
524 #define PORT_POWER_STATE_NORMAL 0
525 #define PORT_POWER_STATE_AP1 1
526 #define PORT_POWER_STATE_AP2 2
527 #define PORT_POWER_STATE_AP6 6
529 struct feature_port_status {
533 u8 port_freeze:1; /* '1' - freezed '0' - normal */
534 u8 rsvd1:7; /* Reserved */
535 u8 power_state:4; /* Power State */
536 u8 ap1_event:1; /* AP1 event was detected */
537 u8 ap2_event:1; /* AP2 event was detected */
538 u64 rsvd2:50; /* Reserved */
543 /* Port Header Register Set */
544 struct feature_port_header {
545 struct feature_header header;
546 struct feature_afu_header afu_header;
549 struct feature_port_capability capability;
550 struct feature_port_control control;
551 struct feature_port_status status;
553 u64 user_clk_freq_cmd0;
554 u64 user_clk_freq_cmd1;
555 u64 user_clk_freq_sts0;
556 u64 user_clk_freq_sts1;
559 struct feature_fme_tmp_threshold {
563 u8 tmp_thshold1:7; /* temperature Threshold 1 */
564 /* temperature Threshold 1 enable/disable */
565 u8 tmp_thshold1_enable:1;
566 u8 tmp_thshold2:7; /* temperature Threshold 2 */
567 /* temperature Threshold 2 enable /disable */
568 u8 tmp_thshold2_enable:1;
569 u8 pro_hot_setpoint:7; /* Proc Hot set point */
570 u8 rsvd4:1; /* Reserved */
571 u8 therm_trip_thshold:7; /* Thermeal Trip Threshold */
572 u8 rsvd3:1; /* Reserved */
573 u8 thshold1_status:1; /* Threshold 1 Status */
574 u8 thshold2_status:1; /* Threshold 2 Status */
575 u8 rsvd5:1; /* Reserved */
576 /* Thermeal Trip Threshold status */
577 u8 therm_trip_thshold_status:1;
578 u8 rsvd6:4; /* Reserved */
579 /* Validation mode- Force Proc Hot */
581 /* Validation mode - Therm trip Hot */
583 u8 rsvd2:2; /* Reserved */
584 u8 thshold_policy:1; /* threshold policy */
585 u32 rsvd:19; /* Reserved */
590 /* Temperature Sensor Read values format 1 */
591 struct feature_fme_temp_rdsensor_fmt1 {
595 /* Reads out FPGA temperature in celsius */
597 u8 rsvd0:1; /* Reserved */
598 /* Temperature reading sequence number */
599 u16 tmp_reading_seq_num;
600 /* Temperature reading is valid */
601 u8 tmp_reading_valid:1;
602 u8 rsvd1:7; /* Reserved */
603 u16 dbg_mode:10; /* Debug mode */
604 u32 rsvd2:22; /* Reserved */
609 /* Temperature sensor read values format 2 */
610 struct feature_fme_temp_rdsensor_fmt2 {
611 u64 rsvd; /* Reserved */
614 /* Temperature Threshold Capability Register */
615 struct feature_fme_tmp_threshold_cap {
619 /* Temperature Threshold Unsupported */
620 u8 tmp_thshold_disabled:1;
621 u64 rsvd:63; /* Reserved */
626 /* FME THERNAL FEATURE */
627 struct feature_fme_thermal {
628 struct feature_header header;
629 struct feature_fme_tmp_threshold threshold;
630 struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
631 struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
632 struct feature_fme_tmp_threshold_cap threshold_cap;
635 /* Power Status register */
636 struct feature_fme_pm_status {
640 /* FPGA Power consumed, The format is to be defined */
642 /* FPGA Latency Tolerance Reporting */
643 u8 fpga_latency_report:1;
644 u64 rsvd:45; /* Reserved */
650 struct feature_fme_pm_ap_threshold {
655 * Number of clocks (5ns period) for assertion
662 u8 threshold1_status:1;
663 u8 threshold2_status:1;
664 u64 rsvd3:46; /* Reserved */
669 /* Xeon Power Limit */
670 struct feature_fme_pm_xeon_limit {
674 /* Power limit in Watts in 12.3 format */
676 /* Indicates that power limit has been written */
678 /* 0 - Turbe range, 1 - Entire range */
680 /* Time constant in XXYYY format */
682 u64 rsvd:40; /* Reserved */
687 /* FPGA Power Limit */
688 struct feature_fme_pm_fpga_limit {
692 /* Power limit in Watts in 12.3 format */
694 /* Indicates that power limit has been written */
696 /* 0 - Turbe range, 1 - Entire range */
698 /* Time constant in XXYYY format */
700 u64 rsvd:40; /* Reserved */
705 /* FME POWER FEATURE */
706 struct feature_fme_power {
707 struct feature_header header;
708 struct feature_fme_pm_status status;
709 struct feature_fme_pm_ap_threshold threshold;
710 struct feature_fme_pm_xeon_limit xeon_limit;
711 struct feature_fme_pm_fpga_limit fpga_limit;
714 #define CACHE_CHANNEL_RD 0
715 #define CACHE_CHANNEL_WR 1
717 enum iperf_cache_events {
722 IPERF_CACHE_RSVD, /* reserved */
723 IPERF_CACHE_HOLD_REQ,
724 IPERF_CACHE_DATA_WR_PORT_CONTEN,
725 IPERF_CACHE_TAG_WR_PORT_CONTEN,
726 IPERF_CACHE_TX_REQ_STALL,
727 IPERF_CACHE_RX_REQ_STALL,
728 IPERF_CACHE_EVICTIONS,
731 /* FPMON Cache Control */
732 struct feature_fme_ifpmon_ch_ctl {
736 u8 reset_counters:1; /* Reset Counters */
737 u8 rsvd1:7; /* Reserved */
738 u8 freeze:1; /* Freeze if set to 1 */
739 u8 rsvd2:7; /* Reserved */
740 u8 cache_event:4; /* Select the cache event */
741 u8 cci_chsel:1; /* Select the channel */
742 u64 rsvd3:43; /* Reserved */
747 /* FPMON Cache Counter */
748 struct feature_fme_ifpmon_ch_ctr {
752 /* Cache Counter for even addresse */
753 u64 cache_counter:48;
754 u16 rsvd:12; /* Reserved */
755 /* Cache Event being reported */
761 enum iperf_fab_events {
772 #define FAB_DISABLE_FILTER 0
773 #define FAB_ENABLE_FILTER 1
775 /* FPMON FAB Control */
776 struct feature_fme_ifpmon_fab_ctl {
780 u8 reset_counters:1; /* Reset Counters */
781 u8 rsvd:7; /* Reserved */
782 u8 freeze:1; /* Set to 1 frozen counter */
783 u8 rsvd1:7; /* Reserved */
784 u8 fab_evtcode:4; /* Fabric Event Code */
785 u8 port_id:2; /* Port ID */
786 u8 rsvd2:1; /* Reserved */
787 u8 port_filter:1; /* Port Filter */
788 u64 rsvd3:40; /* Reserved */
793 /* FPMON Event Counter */
794 struct feature_fme_ifpmon_fab_ctr {
798 u64 fab_cnt:60; /* Fabric event counter */
799 /* Fabric event code being reported */
805 /* FPMON Clock Counter */
806 struct feature_fme_ifpmon_clk_ctr {
807 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */
810 enum iperf_vtd_events {
811 IPERF_VTD_AFU_MEM_RD_TRANS,
812 IPERF_VTD_AFU_MEM_WR_TRANS,
813 IPERF_VTD_AFU_DEVTLB_RD_HIT,
814 IPERF_VTD_AFU_DEVTLB_WR_HIT,
815 IPERF_VTD_DEVTLB_4K_FILL,
816 IPERF_VTD_DEVTLB_2M_FILL,
817 IPERF_VTD_DEVTLB_1G_FILL,
820 /* VT-d control register */
821 struct feature_fme_ifpmon_vtd_ctl {
825 u8 reset_counters:1; /* Reset Counters */
826 u8 rsvd:7; /* Reserved */
827 u8 freeze:1; /* Set to 1 frozen counter */
828 u8 rsvd1:7; /* Reserved */
829 u8 vtd_evtcode:4; /* VTd and TLB event code */
830 u64 rsvd2:44; /* Reserved */
835 /* VT-d event counter */
836 struct feature_fme_ifpmon_vtd_ctr {
840 u64 vtd_counter:48; /* VTd event counter */
841 u16 rsvd:12; /* Reserved */
842 u8 event_code:4; /* VTd event code */
847 enum iperf_vtd_sip_events {
848 IPERF_VTD_SIP_IOTLB_4K_HIT,
849 IPERF_VTD_SIP_IOTLB_2M_HIT,
850 IPERF_VTD_SIP_IOTLB_1G_HIT,
851 IPERF_VTD_SIP_SLPWC_L3_HIT,
852 IPERF_VTD_SIP_SLPWC_L4_HIT,
853 IPERF_VTD_SIP_RCC_HIT,
854 IPERF_VTD_SIP_IOTLB_4K_MISS,
855 IPERF_VTD_SIP_IOTLB_2M_MISS,
856 IPERF_VTD_SIP_IOTLB_1G_MISS,
857 IPERF_VTD_SIP_SLPWC_L3_MISS,
858 IPERF_VTD_SIP_SLPWC_L4_MISS,
859 IPERF_VTD_SIP_RCC_MISS,
862 /* VT-d SIP control register */
863 struct feature_fme_ifpmon_vtd_sip_ctl {
867 u8 reset_counters:1; /* Reset Counters */
868 u8 rsvd:7; /* Reserved */
869 u8 freeze:1; /* Set to 1 frozen counter */
870 u8 rsvd1:7; /* Reserved */
871 u8 vtd_evtcode:4; /* VTd and TLB event code */
872 u64 rsvd2:44; /* Reserved */
877 /* VT-d SIP event counter */
878 struct feature_fme_ifpmon_vtd_sip_ctr {
882 u64 vtd_counter:48; /* VTd event counter */
883 u16 rsvd:12; /* Reserved */
884 u8 event_code:4; /* VTd event code */
889 /* FME IPERF FEATURE */
890 struct feature_fme_iperf {
891 struct feature_header header;
892 struct feature_fme_ifpmon_ch_ctl ch_ctl;
893 struct feature_fme_ifpmon_ch_ctr ch_ctr0;
894 struct feature_fme_ifpmon_ch_ctr ch_ctr1;
895 struct feature_fme_ifpmon_fab_ctl fab_ctl;
896 struct feature_fme_ifpmon_fab_ctr fab_ctr;
897 struct feature_fme_ifpmon_clk_ctr clk;
898 struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
899 struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
900 struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
901 struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
904 enum dperf_fab_events {
907 DPERF_FAB_MMIO_RD = 6,
911 /* FPMON FAB Control */
912 struct feature_fme_dfpmon_fab_ctl {
916 u8 reset_counters:1; /* Reset Counters */
917 u8 rsvd:7; /* Reserved */
918 u8 freeze:1; /* Set to 1 frozen counter */
919 u8 rsvd1:7; /* Reserved */
920 u8 fab_evtcode:4; /* Fabric Event Code */
921 u8 port_id:2; /* Port ID */
922 u8 rsvd2:1; /* Reserved */
923 u8 port_filter:1; /* Port Filter */
924 u64 rsvd3:40; /* Reserved */
929 /* FPMON Event Counter */
930 struct feature_fme_dfpmon_fab_ctr {
934 u64 fab_cnt:60; /* Fabric event counter */
935 /* Fabric event code being reported */
941 /* FPMON Clock Counter */
942 struct feature_fme_dfpmon_clk_ctr {
943 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */
946 /* FME DPERF FEATURE */
947 struct feature_fme_dperf {
948 struct feature_header header;
950 struct feature_fme_dfpmon_fab_ctl fab_ctl;
951 struct feature_fme_dfpmon_fab_ctr fab_ctr;
952 struct feature_fme_dfpmon_clk_ctr clk;
955 struct feature_fme_error0 {
956 #define FME_ERROR0_MASK 0xFFUL
957 #define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */
961 u8 fabric_err:1; /* Fabric error */
962 u8 fabfifo_overflow:1; /* Fabric fifo overflow */
963 u8 kticdc_parity_err:2;/* KTI CDC Parity Error */
964 u8 iommu_parity_err:1; /* IOMMU Parity error */
965 /* AFU PF/VF access mismatch detected */
966 u8 afu_acc_mode_err:1;
967 u8 mbp_err:1; /* Indicates an MBP event */
968 /* PCIE0 CDC Parity Error */
969 u8 pcie0cdc_parity_err:5;
970 /* PCIE1 CDC Parity Error */
971 u8 pcie1cdc_parity_err:5;
972 /* CVL CDC Parity Error */
973 u8 cvlcdc_parity_err:3;
974 u64 rsvd:44; /* Reserved */
979 /* PCIe0 Error Status register */
980 struct feature_fme_pcie0_error {
981 #define FME_PCIE0_ERROR_MASK 0xFFUL
985 u8 formattype_err:1; /* TLP format/type error */
986 u8 MWAddr_err:1; /* TLP MW address error */
987 u8 MWAddrLength_err:1; /* TLP MW length error */
988 u8 MRAddr_err:1; /* TLP MR address error */
989 u8 MRAddrLength_err:1; /* TLP MR length error */
990 u8 cpl_tag_err:1; /* TLP CPL tag error */
991 u8 cpl_status_err:1; /* TLP CPL status error */
992 u8 cpl_timeout_err:1; /* TLP CPL timeout */
993 u8 cci_parity_err:1; /* CCI bridge parity error */
994 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */
995 u64 rsvd:52; /* Reserved */
996 u8 vfnumb_err:1; /* Number of error VF */
997 u8 funct_type_err:1; /* Virtual (1) or Physical */
1002 /* PCIe1 Error Status register */
1003 struct feature_fme_pcie1_error {
1004 #define FME_PCIE1_ERROR_MASK 0xFFUL
1008 u8 formattype_err:1; /* TLP format/type error */
1009 u8 MWAddr_err:1; /* TLP MW address error */
1010 u8 MWAddrLength_err:1; /* TLP MW length error */
1011 u8 MRAddr_err:1; /* TLP MR address error */
1012 u8 MRAddrLength_err:1; /* TLP MR length error */
1013 u8 cpl_tag_err:1; /* TLP CPL tag error */
1014 u8 cpl_status_err:1; /* TLP CPL status error */
1015 u8 cpl_timeout_err:1; /* TLP CPL timeout */
1016 u8 cci_parity_err:1; /* CCI bridge parity error */
1017 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */
1018 u64 rsvd:54; /* Reserved */
1023 /* FME First Error register */
1024 struct feature_fme_first_error {
1025 #define FME_FIRST_ERROR_MASK ((1ULL << 60) - 1)
1030 * Indicates the Error Register that was
1033 u64 err_reg_status:60;
1035 * Holds 60 LSBs from the Error register that was
1043 /* FME Next Error register */
1044 struct feature_fme_next_error {
1045 #define FME_NEXT_ERROR_MASK ((1ULL << 60) - 1)
1050 * Indicates the Error Register that was
1053 u64 err_reg_status:60;
1055 * Holds 60 LSBs from the Error register that was
1063 /* RAS Non Fatal Error Status register */
1064 struct feature_fme_ras_nonfaterror {
1068 /* thremal threshold AP1 */
1069 u8 temp_thresh_ap1:1;
1070 /* thremal threshold AP2 */
1071 u8 temp_thresh_ap2:1;
1072 u8 pcie_error:1; /* pcie Error */
1073 u8 portfatal_error:1; /* port fatal error */
1074 u8 proc_hot:1; /* Indicates a ProcHot event */
1075 /* Indicates an AFU PF/VF access mismatch */
1076 u8 afu_acc_mode_err:1;
1077 /* Injected nonfata Error */
1078 u8 injected_nonfata_err:1;
1080 /* Temperature threshold triggered AP6*/
1081 u8 temp_thresh_AP6:1;
1082 /* Power threshold triggered AP1 */
1083 u8 power_thresh_AP1:1;
1084 /* Power threshold triggered AP2 */
1085 u8 power_thresh_AP2:1;
1086 /* Indicates a MBP event */
1088 u64 rsvd2:51; /* Reserved */
1093 /* RAS Catastrophic Fatal Error Status register */
1094 struct feature_fme_ras_catfaterror {
1098 /* KTI Link layer error detected */
1099 u8 ktilink_fatal_err:1;
1100 /* tag-n-cache error detected */
1101 u8 tagcch_fatal_err:1;
1102 /* CCI error detected */
1104 /* KTI Protocol error detected */
1105 u8 ktiprpto_fatal_err:1;
1106 /* Fatal DRAM error detected */
1107 u8 dram_fatal_err:1;
1108 /* IOMMU detected */
1109 u8 iommu_fatal_err:1;
1110 /* Fabric Fatal Error */
1111 u8 fabric_fatal_err:1;
1112 /* PCIe possion Error */
1113 u8 pcie_poison_err:1;
1114 /* Injected fatal Error */
1115 u8 inject_fata_err:1;
1116 /* Catastrophic CRC Error */
1117 u8 crc_catast_err:1;
1118 /* Catastrophic Thermal Error */
1119 u8 therm_catast_err:1;
1120 /* Injected Catastrophic Error */
1121 u8 injected_catast_err:1;
1127 /* RAS Error injection register */
1128 struct feature_fme_ras_error_inj {
1129 #define FME_RAS_ERROR_INJ_MASK 0x7UL
1133 u8 catast_error:1; /* Catastrophic error flag */
1134 u8 fatal_error:1; /* Fatal error flag */
1135 u8 nonfatal_error:1; /* NonFatal error flag */
1136 u64 rsvd:61; /* Reserved */
1141 /* FME error capabilities */
1142 struct feature_fme_error_capability {
1147 /* MSI-X vector table entry number */
1148 u16 intr_vector_num:12;
1149 u64 rsvd:51; /* Reserved */
1154 /* FME ERR FEATURE */
1155 struct feature_fme_err {
1156 struct feature_header header;
1157 struct feature_fme_error0 fme_err_mask;
1158 struct feature_fme_error0 fme_err;
1159 struct feature_fme_pcie0_error pcie0_err_mask;
1160 struct feature_fme_pcie0_error pcie0_err;
1161 struct feature_fme_pcie1_error pcie1_err_mask;
1162 struct feature_fme_pcie1_error pcie1_err;
1163 struct feature_fme_first_error fme_first_err;
1164 struct feature_fme_next_error fme_next_err;
1165 struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1166 struct feature_fme_ras_nonfaterror ras_nonfaterr;
1167 struct feature_fme_ras_catfaterror ras_catfat_mask;
1168 struct feature_fme_ras_catfaterror ras_catfaterr;
1169 struct feature_fme_ras_error_inj ras_error_inj;
1170 struct feature_fme_error_capability fme_err_capability;
1173 /* FME Partial Reconfiguration Control */
1174 struct feature_fme_pr_ctl {
1178 u8 pr_reset:1; /* Reset PR Engine */
1179 u8 rsvd3:3; /* Reserved */
1180 u8 pr_reset_ack:1; /* Reset PR Engine Ack */
1181 u8 rsvd4:3; /* Reserved */
1182 u8 pr_regionid:2; /* PR Region ID */
1183 u8 rsvd1:2; /* Reserved */
1184 u8 pr_start_req:1; /* PR Start Request */
1185 u8 pr_push_complete:1; /* PR Data push complete */
1186 u8 pr_kind:1; /* PR Data push complete */
1187 u32 rsvd:17; /* Reserved */
1188 u32 config_data; /* Config data TBD */
1193 /* FME Partial Reconfiguration Status */
1194 struct feature_fme_pr_status {
1198 u16 pr_credit:9; /* PR Credits */
1199 u8 rsvd2:7; /* Reserved */
1200 u8 pr_status:1; /* PR status */
1201 u8 rsvd:3; /* Reserved */
1202 /* Altra PR Controller Block status */
1203 u8 pr_controller_status:3;
1204 u8 rsvd1:1; /* Reserved */
1205 u8 pr_host_status:4; /* PR Host status */
1206 u8 rsvd3:4; /* Reserved */
1207 /* Security Block Status fields (TBD) */
1208 u32 security_bstatus;
1213 /* FME Partial Reconfiguration Data */
1214 struct feature_fme_pr_data {
1216 u64 csr; /* PR data from the raw-binary file */
1218 /* PR data from the raw-binary file */
1225 /* FME PR Public Key */
1226 struct feature_fme_pr_key {
1227 u64 key; /* FME PR Public Hash */
1230 /* FME PR FEATURE */
1231 struct feature_fme_pr {
1232 struct feature_header header;
1233 /*Partial Reconfiguration control */
1234 struct feature_fme_pr_ctl ccip_fme_pr_control;
1236 /* Partial Reconfiguration Status */
1237 struct feature_fme_pr_status ccip_fme_pr_status;
1239 /* Partial Reconfiguration data */
1240 struct feature_fme_pr_data ccip_fme_pr_data;
1242 /* Partial Reconfiguration data */
1243 u64 ccip_fme_pr_err;
1247 /* Partial Reconfiguration data registers */
1259 /* PR Interface ID */
1260 u64 fme_pr_intfc_id_l;
1261 u64 fme_pr_intfc_id_h;
1263 /* MSIX filed to be Added */
1266 /* FME HSSI Control */
1267 struct feature_fme_hssi_eth_ctrl {
1271 u32 data:32; /* HSSI data */
1272 u16 address:16; /* HSSI address */
1276 * 0x08 - SW register RD request
1277 * 0x10 - SW register WR request
1278 * 0x40 - Auxiliar bus RD request
1279 * 0x80 - Auxiliar bus WR request
1286 /* FME HSSI Status */
1287 struct feature_fme_hssi_eth_stat {
1291 u32 data:32; /* HSSI data */
1292 u8 acknowledge:1; /* HSSI acknowledge */
1293 u8 spare:1; /* HSSI spare */
1294 u32 rsvd:30; /* Reserved */
1299 /* FME HSSI FEATURE */
1300 struct feature_fme_hssi {
1301 struct feature_header header;
1302 struct feature_fme_hssi_eth_ctrl hssi_control;
1303 struct feature_fme_hssi_eth_stat hssi_status;
1306 #define PORT_ERR_MASK 0xfff0703ff001f
1307 struct feature_port_err_key {
1311 /* Tx Channel0: Overflow */
1312 u8 tx_ch0_overflow:1;
1313 /* Tx Channel0: Invalid request encoding */
1314 u8 tx_ch0_invaldreq :1;
1315 /* Tx Channel0: Request with cl_len=3 not supported */
1316 u8 tx_ch0_cl_len3:1;
1317 /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1318 u8 tx_ch0_cl_len2:1;
1319 /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1320 u8 tx_ch0_cl_len4:1;
1322 u16 rsvd1:4; /* Reserved */
1324 /* AFU MMIO RD received while PORT is in reset */
1325 u8 mmio_rd_whilerst:1;
1326 /* AFU MMIO WR received while PORT is in reset */
1327 u8 mmio_wr_whilerst:1;
1329 u16 rsvd2:5; /* Reserved */
1331 /* Tx Channel1: Overflow */
1332 u8 tx_ch1_overflow:1;
1333 /* Tx Channel1: Invalid request encoding */
1334 u8 tx_ch1_invaldreq:1;
1335 /* Tx Channel1: Request with cl_len=3 not supported */
1336 u8 tx_ch1_cl_len3:1;
1337 /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1338 u8 tx_ch1_cl_len2:1;
1339 /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1340 u8 tx_ch1_cl_len4:1;
1342 /* Tx Channel1: Insufficient data payload */
1343 u8 tx_ch1_insuff_data:1;
1344 /* Tx Channel1: Data payload overrun */
1345 u8 tx_ch1_data_overrun:1;
1346 /* Tx Channel1 : Incorrect address */
1347 u8 tx_ch1_incorr_addr:1;
1348 /* Tx Channel1 : NON-Zero SOP Detected */
1350 /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1351 u8 tx_ch1_illegal_vcsel:1;
1353 u8 rsvd3:6; /* Reserved */
1355 /* MMIO Read Timeout in AFU */
1356 u8 mmioread_timeout:1;
1358 /* Tx Channel2: FIFO Overflow */
1359 u8 tx_ch2_fifo_overflow:1;
1361 /* MMIO read is not matching pending request */
1362 u8 unexp_mmio_resp:1;
1364 u8 rsvd4:5; /* Reserved */
1366 /* Number of pending Requests: counter overflow */
1367 u8 tx_req_counter_overflow:1;
1368 /* Req with Address violating SMM Range */
1370 /* Req with Address violating second SMM Range */
1371 u8 llpr_smrr2_err:1;
1372 /* Req with Address violating ME Stolen message */
1374 /* Req with Address violating Generic Protected Range */
1375 u8 genprot_range_err:1;
1376 /* Req with Address violating Legacy Range low */
1377 u8 legrange_low_err:1;
1378 /* Req with Address violating Legacy Range High */
1379 u8 legrange_high_err:1;
1380 /* Req with Address violating VGA memory range */
1381 u8 vgmem_range_err:1;
1382 u8 page_fault_err:1; /* Page fault */
1383 u8 pmr_err:1; /* PMR Error */
1384 u8 ap6_event:1; /* AP6 event */
1385 /* VF FLR detected on Port with PF access control */
1386 u8 vfflr_access_err:1;
1387 u16 rsvd5:12; /* Reserved */
1392 /* Port first error register, not contain all error bits in error register. */
1393 struct feature_port_first_err_key {
1397 u8 tx_ch0_overflow:1;
1398 u8 tx_ch0_invaldreq :1;
1399 u8 tx_ch0_cl_len3:1;
1400 u8 tx_ch0_cl_len2:1;
1401 u8 tx_ch0_cl_len4:1;
1402 u8 rsvd1:4; /* Reserved */
1403 u8 mmio_rd_whilerst:1;
1404 u8 mmio_wr_whilerst:1;
1405 u8 rsvd2:5; /* Reserved */
1406 u8 tx_ch1_overflow:1;
1407 u8 tx_ch1_invaldreq:1;
1408 u8 tx_ch1_cl_len3:1;
1409 u8 tx_ch1_cl_len2:1;
1410 u8 tx_ch1_cl_len4:1;
1411 u8 tx_ch1_insuff_data:1;
1412 u8 tx_ch1_data_overrun:1;
1413 u8 tx_ch1_incorr_addr:1;
1415 u8 tx_ch1_illegal_vcsel:1;
1416 u8 rsvd3:6; /* Reserved */
1417 u8 mmioread_timeout:1;
1418 u8 tx_ch2_fifo_overflow:1;
1419 u8 rsvd4:6; /* Reserved */
1420 u8 tx_req_counter_overflow:1;
1421 u32 rsvd5:23; /* Reserved */
1426 /* Port malformed Req0 */
1427 struct feature_port_malformed_req0 {
1431 /* Port malformed Req1 */
1432 struct feature_port_malformed_req1 {
1436 /* Port debug register */
1437 struct feature_port_debug {
1441 /* Port error capabilities */
1442 struct feature_port_err_capability {
1447 /* MSI-X vector table entry number */
1448 u16 intr_vector_num:12;
1449 u64 rsvd:51; /* Reserved */
1454 /* PORT FEATURE ERROR */
1455 struct feature_port_error {
1456 struct feature_header header;
1457 struct feature_port_err_key error_mask;
1458 struct feature_port_err_key port_error;
1459 struct feature_port_first_err_key port_first_error;
1460 struct feature_port_malformed_req0 malreq0;
1461 struct feature_port_malformed_req1 malreq1;
1462 struct feature_port_debug port_debug;
1463 struct feature_port_err_capability error_capability;
1466 /* Port UMSG Capability */
1467 struct feature_port_umsg_cap {
1471 /* Number of umsg allocated to this port */
1473 /* Enable / Disable UMsg engine for this port */
1475 /* Usmg initialization status */
1476 u8 umsg_init_complete:1;
1477 /* IOMMU can not translate the umsg base address */
1478 u8 umsg_trans_error:1;
1479 u64 rsvd:53; /* Reserved */
1484 /* Port UMSG base address */
1485 struct feature_port_umsg_baseaddr {
1489 u64 base_addr:48; /* 48 bit physical address */
1490 u16 rsvd; /* Reserved */
1495 struct feature_port_umsg_mode {
1499 u32 umsg_hint_enable; /* UMSG hint enable/disable */
1500 u32 rsvd; /* Reserved */
1505 /* PORT FEATURE UMSG */
1506 struct feature_port_umsg {
1507 struct feature_header header;
1508 struct feature_port_umsg_cap capability;
1509 struct feature_port_umsg_baseaddr baseaddr;
1510 struct feature_port_umsg_mode mode;
1513 #define UMSG_EN_POLL_INVL 10 /* us */
1514 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1516 /* Port UINT Capability */
1517 struct feature_port_uint_cap {
1521 u16 intr_num:12; /* Supported interrupts num */
1522 /* First MSI-X vector table entry number */
1523 u16 first_vec_num:12;
1529 /* PORT FEATURE UINT */
1530 struct feature_port_uint {
1531 struct feature_header header;
1532 struct feature_port_uint_cap capability;
1535 /* STP region supports mmap operation, so use page aligned size. */
1536 #define PORT_FEATURE_STP_REGION_SIZE \
1537 IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1539 /* Port STP status register (for debug only)*/
1540 struct feature_port_stp_status {
1544 /* SLD Hub end-point read/write timeout */
1545 u8 sld_ep_timeout:1;
1546 /* Remote STP in reset/disable */
1548 u8 unsupported_read:1;
1549 /* MMIO timeout detected and faked with a response */
1553 u8 txfifo_overflow:1;
1554 u8 txfifo_underflow:1;
1555 u8 rxfifo_overflow:1;
1556 u8 rxfifo_underflow:1;
1557 /* Number of MMIO write requests */
1559 /* Number of MMIO read requests */
1561 /* Number of MMIO read responses */
1569 * Most registers in STP region are not touched by driver, but mmapped to user
1570 * space. So they are not defined in below data structure, as its actual size
1571 * is 0x18c per spec.
1573 struct feature_port_stp {
1574 struct feature_header header;
1575 struct feature_port_stp_status stp_status;
1579 * enum fpga_pr_states - fpga PR states
1580 * @FPGA_PR_STATE_UNKNOWN: can't determine state
1581 * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1582 * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1583 * @FPGA_PR_STATE_WRITE: writing image to FPGA
1584 * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1585 * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1586 * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1587 * @FPGA_PR_STATE_OPERATING: FPGA PR done
1589 enum fpga_pr_states {
1590 /* canot determine state states */
1591 FPGA_PR_STATE_UNKNOWN,
1593 /* write sequence: init, write, complete */
1594 FPGA_PR_STATE_WRITE_INIT,
1595 FPGA_PR_STATE_WRITE_INIT_ERR,
1596 FPGA_PR_STATE_WRITE,
1597 FPGA_PR_STATE_WRITE_ERR,
1598 FPGA_PR_STATE_WRITE_COMPLETE,
1599 FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1606 * FPGA Manager flags
1607 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1609 #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
1612 * struct fpga_pr_info - specific information to a FPGA PR
1613 * @flags: boolean flags as defined above
1614 * @pr_err: PR error code
1615 * @state: fpga manager state
1618 struct fpga_pr_info {
1621 enum fpga_pr_states state;
1625 #define DEFINE_FPGA_PR_ERR_MSG(_name_) \
1626 static const char * const _name_[] = { \
1627 "PR operation error detected", \
1628 "PR CRC error detected", \
1629 "PR incompatiable bitstream error detected", \
1630 "PR IP protocol error detected", \
1631 "PR FIFO overflow error detected", \
1632 "PR timeout error detected", \
1633 "PR secure load error detected", \
1636 #define RST_POLL_INVL 10 /* us */
1637 #define RST_POLL_TIMEOUT 1000 /* us */
1639 #define PR_WAIT_TIMEOUT 15000000
1641 #define PR_HOST_STATUS_IDLE 0
1642 #define PR_MAX_ERR_NUM 7
1644 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1647 * green bitstream header must be byte-packed to match the
1656 #define GBS_GUID_H 0x414750466e6f6558
1657 #define GBS_GUID_L 0x31303076534247b7
1658 #define is_valid_bts(bts_hdr) \
1659 (((bts_hdr)->guid_h == GBS_GUID_H) && \
1660 ((bts_hdr)->guid_l == GBS_GUID_L))
1663 #endif /* _BASE_IFPGA_DEFINES_H_ */