1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82598.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_82598_MAX_TX_QUEUES 32
41 #define IXGBE_82598_MAX_RX_QUEUES 64
42 #define IXGBE_82598_RAR_ENTRIES 16
43 #define IXGBE_82598_MC_TBL_SIZE 128
44 #define IXGBE_82598_VFT_TBL_SIZE 128
45 #define IXGBE_82598_RX_PB_SIZE 512
47 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed,
50 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
51 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
52 bool autoneg_wait_to_complete);
53 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
54 ixgbe_link_speed *speed, bool *link_up,
55 bool link_up_wait_to_complete);
56 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg_wait_to_complete);
59 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg_wait_to_complete);
62 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
63 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
64 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
65 STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
66 u32 headroom, int strategy);
67 STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
70 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
71 * @hw: pointer to the HW structure
73 * The defaults for 82598 should be in the range of 50us to 50ms,
74 * however the hardware default for these parts is 500us to 1ms which is less
75 * than the 10ms recommended by the pci-e spec. To address this we need to
76 * increase the value to either 10ms to 250ms for capability version 1 config,
77 * or 16ms to 55ms for version 2.
79 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
81 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
84 /* only take action if timeout value is defaulted to 0 */
85 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
89 * if capababilities version is type 1 we can write the
90 * timeout of 10ms to 250ms through the GCR register
92 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
93 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
98 * for version 2 capabilities we need to write the config space
99 * directly in order to set the completion timeout value for
102 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
103 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
104 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
106 /* disable completion timeout resend */
107 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
108 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
112 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
113 * @hw: pointer to hardware structure
115 * Initialize the function pointers and assign the MAC type for 82598.
116 * Does not touch the hardware.
118 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
120 struct ixgbe_mac_info *mac = &hw->mac;
121 struct ixgbe_phy_info *phy = &hw->phy;
124 DEBUGFUNC("ixgbe_init_ops_82598");
126 ret_val = ixgbe_init_phy_ops_generic(hw);
127 ret_val = ixgbe_init_ops_generic(hw);
130 phy->ops.init = ixgbe_init_phy_ops_82598;
133 mac->ops.start_hw = ixgbe_start_hw_82598;
134 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598;
135 mac->ops.reset_hw = ixgbe_reset_hw_82598;
136 mac->ops.get_media_type = ixgbe_get_media_type_82598;
137 mac->ops.get_supported_physical_layer =
138 ixgbe_get_supported_physical_layer_82598;
139 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;
140 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;
141 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;
142 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;
144 /* RAR, Multicast, VLAN */
145 mac->ops.set_vmdq = ixgbe_set_vmdq_82598;
146 mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;
147 mac->ops.set_vfta = ixgbe_set_vfta_82598;
148 mac->ops.set_vlvf = NULL;
149 mac->ops.clear_vfta = ixgbe_clear_vfta_82598;
152 mac->ops.fc_enable = ixgbe_fc_enable_82598;
154 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
155 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
156 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
157 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
158 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
159 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
160 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
163 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;
164 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598;
167 mac->ops.check_link = ixgbe_check_mac_link_82598;
168 mac->ops.setup_link = ixgbe_setup_mac_link_82598;
169 mac->ops.flap_tx_laser = NULL;
170 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;
171 mac->ops.setup_rxpba = ixgbe_set_rxpba_82598;
173 /* Manageability interface */
174 mac->ops.set_fw_drv_ver = NULL;
176 mac->ops.get_rtrup2tc = NULL;
182 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
183 * @hw: pointer to hardware structure
185 * Initialize any function pointers that were not able to be
186 * set during init_shared_code because the PHY/SFP type was
187 * not known. Perform the SFP init if necessary.
190 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
192 struct ixgbe_mac_info *mac = &hw->mac;
193 struct ixgbe_phy_info *phy = &hw->phy;
194 s32 ret_val = IXGBE_SUCCESS;
195 u16 list_offset, data_offset;
197 DEBUGFUNC("ixgbe_init_phy_ops_82598");
199 /* Identify the PHY */
200 phy->ops.identify(hw);
202 /* Overwrite the link function pointers if copper PHY */
203 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
204 mac->ops.setup_link = ixgbe_setup_copper_link_82598;
205 mac->ops.get_link_capabilities =
206 ixgbe_get_copper_link_capabilities_generic;
209 switch (hw->phy.type) {
211 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
212 phy->ops.check_link = ixgbe_check_phy_link_tnx;
213 phy->ops.get_firmware_version =
214 ixgbe_get_phy_firmware_version_tnx;
217 phy->ops.reset = ixgbe_reset_phy_nl;
219 /* Call SFP+ identify routine to get the SFP+ module type */
220 ret_val = phy->ops.identify_sfp(hw);
221 if (ret_val != IXGBE_SUCCESS)
223 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
224 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
228 /* Check to see if SFP+ module is supported */
229 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
232 if (ret_val != IXGBE_SUCCESS) {
233 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
246 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
247 * @hw: pointer to hardware structure
249 * Starts the hardware using the generic start_hw function.
250 * Disables relaxed ordering Then set pcie completion timeout
253 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
257 s32 ret_val = IXGBE_SUCCESS;
259 DEBUGFUNC("ixgbe_start_hw_82598");
261 ret_val = ixgbe_start_hw_generic(hw);
265 /* Disable relaxed ordering */
266 for (i = 0; ((i < hw->mac.max_tx_queues) &&
267 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
268 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
269 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
270 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
273 for (i = 0; ((i < hw->mac.max_rx_queues) &&
274 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
275 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
276 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
277 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
278 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
281 /* set the completion timeout for interface */
282 ixgbe_set_pcie_completion_timeout(hw);
288 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
289 * @hw: pointer to hardware structure
290 * @speed: pointer to link speed
291 * @autoneg: boolean auto-negotiation value
293 * Determines the link capabilities by reading the AUTOC register.
295 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
296 ixgbe_link_speed *speed,
299 s32 status = IXGBE_SUCCESS;
302 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
305 * Determine link capabilities based on the stored value of AUTOC,
306 * which represents EEPROM defaults. If AUTOC value has not been
307 * stored, use the current register value.
309 if (hw->mac.orig_link_settings_stored)
310 autoc = hw->mac.orig_autoc;
312 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
314 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
315 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
316 *speed = IXGBE_LINK_SPEED_1GB_FULL;
320 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
321 *speed = IXGBE_LINK_SPEED_10GB_FULL;
325 case IXGBE_AUTOC_LMS_1G_AN:
326 *speed = IXGBE_LINK_SPEED_1GB_FULL;
330 case IXGBE_AUTOC_LMS_KX4_AN:
331 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
332 *speed = IXGBE_LINK_SPEED_UNKNOWN;
333 if (autoc & IXGBE_AUTOC_KX4_SUPP)
334 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
335 if (autoc & IXGBE_AUTOC_KX_SUPP)
336 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
341 status = IXGBE_ERR_LINK_SETUP;
349 * ixgbe_get_media_type_82598 - Determines media type
350 * @hw: pointer to hardware structure
352 * Returns the media type (fiber, copper, backplane)
354 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
356 enum ixgbe_media_type media_type;
358 DEBUGFUNC("ixgbe_get_media_type_82598");
360 /* Detect if there is a copper PHY attached. */
361 switch (hw->phy.type) {
362 case ixgbe_phy_cu_unknown:
364 media_type = ixgbe_media_type_copper;
370 /* Media type for I82598 is based on device ID */
371 switch (hw->device_id) {
372 case IXGBE_DEV_ID_82598:
373 case IXGBE_DEV_ID_82598_BX:
374 /* Default device ID is mezzanine card KX/KX4 */
375 media_type = ixgbe_media_type_backplane;
377 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
378 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
379 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
380 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
381 case IXGBE_DEV_ID_82598EB_XF_LR:
382 case IXGBE_DEV_ID_82598EB_SFP_LOM:
383 media_type = ixgbe_media_type_fiber;
385 case IXGBE_DEV_ID_82598EB_CX4:
386 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
387 media_type = ixgbe_media_type_cx4;
389 case IXGBE_DEV_ID_82598AT:
390 case IXGBE_DEV_ID_82598AT2:
391 media_type = ixgbe_media_type_copper;
394 media_type = ixgbe_media_type_unknown;
402 * ixgbe_fc_enable_82598 - Enable flow control
403 * @hw: pointer to hardware structure
405 * Enable flow control according to the current settings.
407 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
409 s32 ret_val = IXGBE_SUCCESS;
418 DEBUGFUNC("ixgbe_fc_enable_82598");
420 /* Validate the water mark configuration */
421 if (!hw->fc.pause_time) {
422 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
426 /* Low water mark of zero causes XOFF floods */
427 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
428 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
429 hw->fc.high_water[i]) {
430 if (!hw->fc.low_water[i] ||
431 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
432 DEBUGOUT("Invalid water mark configuration\n");
433 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
440 * On 82598 having Rx FC on causes resets while doing 1G
441 * so if it's on turn it off once we know link_speed. For
442 * more details see 82598 Specification update.
444 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
445 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
446 switch (hw->fc.requested_mode) {
448 hw->fc.requested_mode = ixgbe_fc_tx_pause;
450 case ixgbe_fc_rx_pause:
451 hw->fc.requested_mode = ixgbe_fc_none;
459 /* Negotiate the fc mode to use */
460 ixgbe_fc_autoneg(hw);
462 /* Disable any previous flow control settings */
463 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
464 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
466 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
467 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
470 * The possible values of fc.current_mode are:
471 * 0: Flow control is completely disabled
472 * 1: Rx flow control is enabled (we can receive pause frames,
473 * but not send pause frames).
474 * 2: Tx flow control is enabled (we can send pause frames but
475 * we do not support receiving pause frames).
476 * 3: Both Rx and Tx flow control (symmetric) are enabled.
479 switch (hw->fc.current_mode) {
482 * Flow control is disabled by software override or autoneg.
483 * The code below will actually disable it in the HW.
486 case ixgbe_fc_rx_pause:
488 * Rx Flow control is enabled and Tx Flow control is
489 * disabled by software override. Since there really
490 * isn't a way to advertise that we are capable of RX
491 * Pause ONLY, we will advertise that we support both
492 * symmetric and asymmetric Rx PAUSE. Later, we will
493 * disable the adapter's ability to send PAUSE frames.
495 fctrl_reg |= IXGBE_FCTRL_RFCE;
497 case ixgbe_fc_tx_pause:
499 * Tx Flow control is enabled, and Rx Flow control is
500 * disabled by software override.
502 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
505 /* Flow control (both Rx and Tx) is enabled by SW override. */
506 fctrl_reg |= IXGBE_FCTRL_RFCE;
507 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
510 DEBUGOUT("Flow control param set incorrectly\n");
511 ret_val = IXGBE_ERR_CONFIG;
516 /* Set 802.3x based flow control settings. */
517 fctrl_reg |= IXGBE_FCTRL_DPF;
518 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
519 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
521 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
522 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
523 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
524 hw->fc.high_water[i]) {
525 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
526 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
527 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
528 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
530 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
531 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
536 /* Configure pause time (2 TCs per register) */
537 reg = hw->fc.pause_time * 0x00010001;
538 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
539 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
541 /* Configure flow control refresh threshold value */
542 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
549 * ixgbe_start_mac_link_82598 - Configures MAC link settings
550 * @hw: pointer to hardware structure
552 * Configures link settings based on values in the ixgbe_hw struct.
553 * Restarts the link. Performs autonegotiation if needed.
555 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
556 bool autoneg_wait_to_complete)
561 s32 status = IXGBE_SUCCESS;
563 DEBUGFUNC("ixgbe_start_mac_link_82598");
566 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
567 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
568 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
570 /* Only poll for autoneg to complete if specified to do so */
571 if (autoneg_wait_to_complete) {
572 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
573 IXGBE_AUTOC_LMS_KX4_AN ||
574 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
575 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
576 links_reg = 0; /* Just in case Autoneg time = 0 */
577 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
578 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
579 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
583 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
584 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
585 DEBUGOUT("Autonegotiation did not complete.\n");
590 /* Add delay to filter out noises during initial link setup */
597 * ixgbe_validate_link_ready - Function looks for phy link
598 * @hw: pointer to hardware structure
600 * Function indicates success when phy link is available. If phy is not ready
601 * within 5 seconds of MAC indicating link, the function returns error.
603 STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
608 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
609 return IXGBE_SUCCESS;
612 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
613 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
614 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
616 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
617 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
623 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
624 DEBUGOUT("Link was indicated but link is down\n");
625 return IXGBE_ERR_LINK_SETUP;
628 return IXGBE_SUCCESS;
632 * ixgbe_check_mac_link_82598 - Get link/speed status
633 * @hw: pointer to hardware structure
634 * @speed: pointer to link speed
635 * @link_up: true is link is up, false otherwise
636 * @link_up_wait_to_complete: bool used to wait for link up or not
638 * Reads the links register to determine if link is up and the current speed
640 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
641 ixgbe_link_speed *speed, bool *link_up,
642 bool link_up_wait_to_complete)
646 u16 link_reg, adapt_comp_reg;
648 DEBUGFUNC("ixgbe_check_mac_link_82598");
651 * SERDES PHY requires us to read link status from undocumented
652 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
653 * indicates link down. OxC00C is read to check that the XAUI lanes
654 * are active. Bit 0 clear indicates active; set indicates inactive.
656 if (hw->phy.type == ixgbe_phy_nl) {
657 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
658 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
659 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
661 if (link_up_wait_to_complete) {
662 for (i = 0; i < hw->mac.max_link_up_time; i++) {
663 if ((link_reg & 1) &&
664 ((adapt_comp_reg & 1) == 0)) {
671 hw->phy.ops.read_reg(hw, 0xC79F,
674 hw->phy.ops.read_reg(hw, 0xC00C,
679 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
685 if (*link_up == false)
689 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
690 if (link_up_wait_to_complete) {
691 for (i = 0; i < hw->mac.max_link_up_time; i++) {
692 if (links_reg & IXGBE_LINKS_UP) {
699 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
702 if (links_reg & IXGBE_LINKS_UP)
708 if (links_reg & IXGBE_LINKS_SPEED)
709 *speed = IXGBE_LINK_SPEED_10GB_FULL;
711 *speed = IXGBE_LINK_SPEED_1GB_FULL;
713 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
714 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
718 return IXGBE_SUCCESS;
722 * ixgbe_setup_mac_link_82598 - Set MAC link speed
723 * @hw: pointer to hardware structure
724 * @speed: new link speed
725 * @autoneg_wait_to_complete: true when waiting for completion is needed
727 * Set the link speed in the AUTOC register and restarts link.
729 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
730 ixgbe_link_speed speed,
731 bool autoneg_wait_to_complete)
733 bool autoneg = false;
734 s32 status = IXGBE_SUCCESS;
735 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
736 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
737 u32 autoc = curr_autoc;
738 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
740 DEBUGFUNC("ixgbe_setup_mac_link_82598");
742 /* Check to see if speed passed in is supported. */
743 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
744 speed &= link_capabilities;
746 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
747 status = IXGBE_ERR_LINK_SETUP;
749 /* Set KX4/KX support according to speed requested */
750 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
751 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
752 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
753 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
754 autoc |= IXGBE_AUTOC_KX4_SUPP;
755 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
756 autoc |= IXGBE_AUTOC_KX_SUPP;
757 if (autoc != curr_autoc)
758 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
761 if (status == IXGBE_SUCCESS) {
763 * Setup and restart the link based on the new values in
764 * ixgbe_hw This will write the AUTOC register based on the new
767 status = ixgbe_start_mac_link_82598(hw,
768 autoneg_wait_to_complete);
776 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
777 * @hw: pointer to hardware structure
778 * @speed: new link speed
779 * @autoneg_wait_to_complete: true if waiting is needed to complete
781 * Sets the link speed in the AUTOC register in the MAC and restarts link.
783 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
784 ixgbe_link_speed speed,
785 bool autoneg_wait_to_complete)
789 DEBUGFUNC("ixgbe_setup_copper_link_82598");
791 /* Setup the PHY according to input speed */
792 status = hw->phy.ops.setup_link_speed(hw, speed,
793 autoneg_wait_to_complete);
795 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
801 * ixgbe_reset_hw_82598 - Performs hardware reset
802 * @hw: pointer to hardware structure
804 * Resets the hardware by resetting the transmit and receive units, masks and
805 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
808 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
810 s32 status = IXGBE_SUCCESS;
811 s32 phy_status = IXGBE_SUCCESS;
818 DEBUGFUNC("ixgbe_reset_hw_82598");
820 /* Call adapter stop to disable tx/rx and clear interrupts */
821 status = hw->mac.ops.stop_adapter(hw);
822 if (status != IXGBE_SUCCESS)
826 * Power up the Atlas Tx lanes if they are currently powered down.
827 * Atlas Tx lanes are powered down for MAC loopback tests, but
828 * they are not automatically restored on reset.
830 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
831 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
832 /* Enable Tx Atlas so packets can be transmitted again */
833 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
835 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
836 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
839 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
841 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
842 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
845 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
847 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
848 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
851 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
853 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
854 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
859 if (hw->phy.reset_disable == false) {
860 /* PHY ops must be identified and initialized prior to reset */
862 /* Init PHY and function pointers, perform SFP setup */
863 phy_status = hw->phy.ops.init(hw);
864 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
866 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
869 hw->phy.ops.reset(hw);
874 * Issue global reset to the MAC. This needs to be a SW reset.
875 * If link reset is used, it might reset the MAC when mng is using it
877 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
878 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
879 IXGBE_WRITE_FLUSH(hw);
881 /* Poll for reset bit to self-clear indicating reset is complete */
882 for (i = 0; i < 10; i++) {
884 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
885 if (!(ctrl & IXGBE_CTRL_RST))
888 if (ctrl & IXGBE_CTRL_RST) {
889 status = IXGBE_ERR_RESET_FAILED;
890 DEBUGOUT("Reset polling failed to complete.\n");
896 * Double resets are required for recovery from certain error
897 * conditions. Between resets, it is necessary to stall to allow time
898 * for any pending HW events to complete.
900 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
901 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
905 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
906 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
907 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
910 * Store the original AUTOC value if it has not been
911 * stored off yet. Otherwise restore the stored original
912 * AUTOC value since the reset operation sets back to deaults.
914 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
915 if (hw->mac.orig_link_settings_stored == false) {
916 hw->mac.orig_autoc = autoc;
917 hw->mac.orig_link_settings_stored = true;
918 } else if (autoc != hw->mac.orig_autoc) {
919 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
922 /* Store the permanent mac address */
923 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
926 * Store MAC address from RAR0, clear receive address registers, and
927 * clear the multicast table
929 hw->mac.ops.init_rx_addrs(hw);
932 if (phy_status != IXGBE_SUCCESS)
939 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
940 * @hw: pointer to hardware struct
941 * @rar: receive address register index to associate with a VMDq index
942 * @vmdq: VMDq set index
944 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
947 u32 rar_entries = hw->mac.num_rar_entries;
949 DEBUGFUNC("ixgbe_set_vmdq_82598");
951 /* Make sure we are using a valid rar index range */
952 if (rar >= rar_entries) {
953 DEBUGOUT1("RAR index %d is out of range.\n", rar);
954 return IXGBE_ERR_INVALID_ARGUMENT;
957 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
958 rar_high &= ~IXGBE_RAH_VIND_MASK;
959 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
960 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
961 return IXGBE_SUCCESS;
965 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
966 * @hw: pointer to hardware struct
967 * @rar: receive address register index to associate with a VMDq index
968 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
970 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
973 u32 rar_entries = hw->mac.num_rar_entries;
975 UNREFERENCED_1PARAMETER(vmdq);
977 /* Make sure we are using a valid rar index range */
978 if (rar >= rar_entries) {
979 DEBUGOUT1("RAR index %d is out of range.\n", rar);
980 return IXGBE_ERR_INVALID_ARGUMENT;
983 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
984 if (rar_high & IXGBE_RAH_VIND_MASK) {
985 rar_high &= ~IXGBE_RAH_VIND_MASK;
986 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
989 return IXGBE_SUCCESS;
993 * ixgbe_set_vfta_82598 - Set VLAN filter table
994 * @hw: pointer to hardware structure
995 * @vlan: VLAN id to write to VLAN filter
996 * @vind: VMDq output index that maps queue to VLAN id in VFTA
997 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
999 * Turn on/off specified VLAN in the VLAN filter table.
1001 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1009 DEBUGFUNC("ixgbe_set_vfta_82598");
1012 return IXGBE_ERR_PARAM;
1014 /* Determine 32-bit word position in array */
1015 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1017 /* Determine the location of the (VMD) queue index */
1018 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1019 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1021 /* Set the nibble for VMD queue index */
1022 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
1023 bits &= (~(0x0F << bitindex));
1024 bits |= (vind << bitindex);
1025 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
1027 /* Determine the location of the bit for this VLAN id */
1028 bitindex = vlan & 0x1F; /* lower five bits */
1030 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1032 /* Turn on this VLAN id */
1033 bits |= (1 << bitindex);
1035 /* Turn off this VLAN id */
1036 bits &= ~(1 << bitindex);
1037 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1039 return IXGBE_SUCCESS;
1043 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1044 * @hw: pointer to hardware structure
1046 * Clears the VLAN filer table, and the VMDq index associated with the filter
1048 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1053 DEBUGFUNC("ixgbe_clear_vfta_82598");
1055 for (offset = 0; offset < hw->mac.vft_size; offset++)
1056 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1058 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1059 for (offset = 0; offset < hw->mac.vft_size; offset++)
1060 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1063 return IXGBE_SUCCESS;
1067 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1068 * @hw: pointer to hardware structure
1069 * @reg: analog register to read
1072 * Performs read operation to Atlas analog register specified.
1074 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1078 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1080 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1081 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1082 IXGBE_WRITE_FLUSH(hw);
1084 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1085 *val = (u8)atlas_ctl;
1087 return IXGBE_SUCCESS;
1091 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1092 * @hw: pointer to hardware structure
1093 * @reg: atlas register to write
1094 * @val: value to write
1096 * Performs write operation to Atlas analog register specified.
1098 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1102 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1104 atlas_ctl = (reg << 8) | val;
1105 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1106 IXGBE_WRITE_FLUSH(hw);
1109 return IXGBE_SUCCESS;
1113 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1114 * @hw: pointer to hardware structure
1115 * @dev_addr: address to read from
1116 * @byte_offset: byte offset to read from dev_addr
1117 * @eeprom_data: value read
1119 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1121 STATIC s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
1122 u8 byte_offset, u8 *eeprom_data)
1124 s32 status = IXGBE_SUCCESS;
1131 DEBUGFUNC("ixgbe_read_i2c_phy_82598");
1133 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1134 gssr = IXGBE_GSSR_PHY1_SM;
1136 gssr = IXGBE_GSSR_PHY0_SM;
1138 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
1139 return IXGBE_ERR_SWFW_SYNC;
1141 if (hw->phy.type == ixgbe_phy_nl) {
1143 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1144 * 0xC30D. These registers are used to talk to the SFP+
1145 * module's EEPROM through the SDA/SCL (I2C) interface.
1147 sfp_addr = (dev_addr << 8) + byte_offset;
1148 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1149 hw->phy.ops.write_reg_mdi(hw,
1150 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1151 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1155 for (i = 0; i < 100; i++) {
1156 hw->phy.ops.read_reg_mdi(hw,
1157 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1158 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1160 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1161 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1166 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1167 DEBUGOUT("EEPROM read did not pass.\n");
1168 status = IXGBE_ERR_SFP_NOT_PRESENT;
1173 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1174 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1176 *eeprom_data = (u8)(sfp_data >> 8);
1178 status = IXGBE_ERR_PHY;
1182 hw->mac.ops.release_swfw_sync(hw, gssr);
1187 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1188 * @hw: pointer to hardware structure
1189 * @byte_offset: EEPROM byte offset to read
1190 * @eeprom_data: value read
1192 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1194 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1197 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1198 byte_offset, eeprom_data);
1202 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1203 * @hw: pointer to hardware structure
1204 * @byte_offset: byte offset at address 0xA2
1205 * @eeprom_data: value read
1207 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1209 STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1212 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1213 byte_offset, sff8472_data);
1217 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1218 * @hw: pointer to hardware structure
1220 * Determines physical layer capabilities of the current configuration.
1222 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1224 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1225 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1226 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1227 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1228 u16 ext_ability = 0;
1230 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1232 hw->phy.ops.identify(hw);
1234 /* Copper PHY must be checked before AUTOC LMS to determine correct
1235 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1236 switch (hw->phy.type) {
1238 case ixgbe_phy_cu_unknown:
1239 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1240 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1241 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1242 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1243 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1244 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1245 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1246 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1252 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1253 case IXGBE_AUTOC_LMS_1G_AN:
1254 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1255 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1256 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1258 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1260 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1261 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1262 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1263 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1264 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1266 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1268 case IXGBE_AUTOC_LMS_KX4_AN:
1269 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1270 if (autoc & IXGBE_AUTOC_KX_SUPP)
1271 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1272 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1273 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1279 if (hw->phy.type == ixgbe_phy_nl) {
1280 hw->phy.ops.identify_sfp(hw);
1282 switch (hw->phy.sfp_type) {
1283 case ixgbe_sfp_type_da_cu:
1284 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1286 case ixgbe_sfp_type_sr:
1287 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1289 case ixgbe_sfp_type_lr:
1290 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1293 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1298 switch (hw->device_id) {
1299 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1300 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1302 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1303 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1304 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1305 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1307 case IXGBE_DEV_ID_82598EB_XF_LR:
1308 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1315 return physical_layer;
1319 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1321 * @hw: pointer to the HW structure
1323 * Calls common function and corrects issue with some single port devices
1324 * that enable LAN1 but not LAN0.
1326 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1328 struct ixgbe_bus_info *bus = &hw->bus;
1332 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1334 ixgbe_set_lan_id_multi_port_pcie(hw);
1336 /* check if LAN0 is disabled */
1337 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1338 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1340 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1342 /* if LAN0 is completely disabled force function to 0 */
1343 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1344 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1345 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1353 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1354 * @hw: pointer to hardware structure
1357 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1362 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1364 /* Enable relaxed ordering */
1365 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1366 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1367 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1368 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1369 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1372 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1373 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1374 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1375 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
1376 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
1377 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1383 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1384 * @hw: pointer to hardware structure
1385 * @num_pb: number of packet buffers to allocate
1386 * @headroom: reserve n KB of headroom
1387 * @strategy: packet buffer allocation strategy
1389 STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1390 u32 headroom, int strategy)
1392 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1394 UNREFERENCED_1PARAMETER(headroom);
1399 /* Setup Rx packet buffer sizes */
1401 case PBA_STRATEGY_WEIGHTED:
1402 /* Setup the first four at 80KB */
1403 rxpktsize = IXGBE_RXPBSIZE_80KB;
1405 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1406 /* Setup the last four at 48KB...don't re-init i */
1407 rxpktsize = IXGBE_RXPBSIZE_48KB;
1409 case PBA_STRATEGY_EQUAL:
1411 /* Divide the remaining Rx packet buffer evenly among the TCs */
1412 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1413 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1417 /* Setup Tx packet buffer sizes */
1418 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1419 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1423 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit
1424 * @hw: pointer to hardware structure
1425 * @regval: register value to write to RXCTRL
1427 * Enables the Rx DMA unit
1429 s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)
1431 DEBUGFUNC("ixgbe_enable_rx_dma_82598");
1433 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1435 return IXGBE_SUCCESS;