1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82598.h"
38 #include "ixgbe_dcb_82599.h"
41 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
42 * credits from the configured bandwidth percentages. Credits
43 * are the smallest unit programmable into the underlying
44 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
45 * groups so this is much simplified from the CEE case.
47 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
50 int min_percent = 100;
51 int min_credit, multiplier;
54 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
55 IXGBE_DCB_CREDIT_QUANTUM;
57 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
58 if (bw[i] < min_percent && bw[i])
62 multiplier = (min_credit / min_percent) + 1;
64 /* Find out the hw credits for each TC */
65 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
66 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
72 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
79 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
80 * @ixgbe_dcb_config: Struct containing DCB settings.
81 * @direction: Configuring either Tx or Rx.
83 * This function calculates the credits allocated to each traffic class.
84 * It should be called only after the rules are checked by
85 * ixgbe_dcb_check_config_cee().
87 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
88 struct ixgbe_dcb_config *dcb_config,
89 u32 max_frame_size, u8 direction)
91 struct ixgbe_dcb_tc_path *p;
92 u32 min_multiplier = 0;
93 u16 min_percent = 100;
94 s32 ret_val = IXGBE_SUCCESS;
95 /* Initialization values default for Tx settings */
97 u32 credit_refill = 0;
99 u16 link_percentage = 0;
103 if (dcb_config == NULL) {
104 ret_val = IXGBE_ERR_CONFIG;
108 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
109 IXGBE_DCB_CREDIT_QUANTUM;
111 /* Find smallest link percentage */
112 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
113 p = &dcb_config->tc_config[i].path[direction];
114 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
115 link_percentage = p->bwg_percent;
117 link_percentage = (link_percentage * bw_percent) / 100;
119 if (link_percentage && link_percentage < min_percent)
120 min_percent = link_percentage;
124 * The ratio between traffic classes will control the bandwidth
125 * percentages seen on the wire. To calculate this ratio we use
126 * a multiplier. It is required that the refill credits must be
127 * larger than the max frame size so here we find the smallest
128 * multiplier that will allow all bandwidth percentages to be
129 * greater than the max frame size.
131 min_multiplier = (min_credit / min_percent) + 1;
133 /* Find out the link percentage for each TC first */
134 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
135 p = &dcb_config->tc_config[i].path[direction];
136 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
138 link_percentage = p->bwg_percent;
139 /* Must be careful of integer division for very small nums */
140 link_percentage = (link_percentage * bw_percent) / 100;
141 if (p->bwg_percent > 0 && link_percentage == 0)
144 /* Save link_percentage for reference */
145 p->link_percent = (u8)link_percentage;
147 /* Calculate credit refill ratio using multiplier */
148 credit_refill = min(link_percentage * min_multiplier,
149 (u32)IXGBE_DCB_MAX_CREDIT_REFILL);
150 p->data_credits_refill = (u16)credit_refill;
152 /* Calculate maximum credit for the TC */
153 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
156 * Adjustment based on rule checking, if the percentage
157 * of a TC is too small, the maximum credit may not be
158 * enough to send out a jumbo frame in data plane arbitration.
160 if (credit_max && (credit_max < min_credit))
161 credit_max = min_credit;
163 if (direction == IXGBE_DCB_TX_CONFIG) {
165 * Adjustment based on rule checking, if the
166 * percentage of a TC is too small, the maximum
167 * credit may not be enough to send out a TSO
168 * packet in descriptor plane arbitration.
170 if (credit_max && (credit_max <
171 IXGBE_DCB_MIN_TSO_CREDIT)
172 && (hw->mac.type == ixgbe_mac_82598EB))
173 credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
175 dcb_config->tc_config[i].desc_credits_max =
179 p->data_credits_max = (u16)credit_max;
187 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
188 * @cfg: dcb configuration to unpack into hardware consumable fields
189 * @map: user priority to traffic class map
190 * @pfc_up: u8 to store user priority PFC bitmask
192 * This unpacks the dcb configuration PFC info which is stored per
193 * traffic class into a 8bit user priority bitmask that can be
194 * consumed by hardware routines. The priority to tc map must be
195 * updated before calling this routine to use current up-to maps.
197 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
199 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
203 * If the TC for this user priority has PFC enabled then set the
204 * matching bit in 'pfc_up' to reflect that PFC is enabled.
206 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
207 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
212 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
215 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
218 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
219 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
222 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
224 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
227 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
228 max[tc] = tc_config[tc].desc_credits_max;
231 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
234 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
237 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
238 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
241 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
244 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
247 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
248 tsa[tc] = tc_config[tc].path[direction].tsa;
251 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
253 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
254 u8 prio_mask = 1 << up;
255 u8 tc = cfg->num_tcs.pg_tcs;
257 /* If tc is 0 then DCB is likely not enabled or supported */
262 * Test from maximum TC to 1 and report the first match we find. If
263 * we find no match we can assume that the TC is 0 since the TC must
264 * be set for all user priorities
266 for (tc--; tc; tc--) {
267 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
274 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
279 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
280 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
284 * ixgbe_dcb_config - Struct containing DCB settings.
285 * @dcb_config: Pointer to DCB config structure
287 * This function checks DCB rules for DCB settings.
288 * The following rules are checked:
289 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
290 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
291 * Group must total 100.
292 * 3. A Traffic Class should not be set to both Link Strict Priority
293 * and Group Strict Priority.
294 * 4. Link strict Bandwidth Groups can only have link strict traffic classes
295 * with zero bandwidth.
297 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
299 struct ixgbe_dcb_tc_path *p;
300 s32 ret_val = IXGBE_SUCCESS;
301 u8 i, j, bw = 0, bw_id;
302 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
303 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
305 memset(bw_sum, 0, sizeof(bw_sum));
306 memset(link_strict, 0, sizeof(link_strict));
308 /* First Tx, then Rx */
309 for (i = 0; i < 2; i++) {
310 /* Check each traffic class for rule violation */
311 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
312 p = &dcb_config->tc_config[j].path[i];
317 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
318 ret_val = IXGBE_ERR_CONFIG;
321 if (p->tsa == ixgbe_dcb_tsa_strict) {
322 link_strict[i][bw_id] = true;
323 /* Link strict should have zero bandwidth */
325 ret_val = IXGBE_ERR_CONFIG;
330 * Traffic classes without link strict
331 * should have non-zero bandwidth.
333 ret_val = IXGBE_ERR_CONFIG;
336 bw_sum[i][bw_id] += bw;
341 /* Check each bandwidth group for rule violation */
342 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
343 bw += dcb_config->bw_percentage[i][j];
345 * Sum of bandwidth percentages of all traffic classes
346 * within a Bandwidth Group must total 100 except for
347 * link strict group (zero bandwidth).
349 if (link_strict[i][j]) {
352 * Link strict group should have zero
355 ret_val = IXGBE_ERR_CONFIG;
358 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
360 ret_val = IXGBE_ERR_CONFIG;
365 if (bw != IXGBE_DCB_BW_PERCENT) {
366 ret_val = IXGBE_ERR_CONFIG;
372 DEBUGOUT2("DCB error code %d while checking %s settings.\n",
373 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
379 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
380 * @hw: pointer to hardware structure
381 * @stats: pointer to statistics structure
382 * @tc_count: Number of elements in bwg_array.
384 * This function returns the status data for each of the Traffic Classes in use.
386 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
389 s32 ret = IXGBE_NOT_IMPLEMENTED;
390 switch (hw->mac.type) {
391 case ixgbe_mac_82598EB:
392 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
394 case ixgbe_mac_82599EB:
397 case ixgbe_mac_X550EM_x:
398 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
407 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
408 * @hw: pointer to hardware structure
409 * @stats: pointer to statistics structure
410 * @tc_count: Number of elements in bwg_array.
412 * This function returns the CBFC status data for each of the Traffic Classes.
414 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
417 s32 ret = IXGBE_NOT_IMPLEMENTED;
418 switch (hw->mac.type) {
419 case ixgbe_mac_82598EB:
420 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
422 case ixgbe_mac_82599EB:
425 case ixgbe_mac_X550EM_x:
426 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
435 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
436 * @hw: pointer to hardware structure
437 * @dcb_config: pointer to ixgbe_dcb_config structure
439 * Configure Rx Data Arbiter and credits for each traffic class.
441 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
442 struct ixgbe_dcb_config *dcb_config)
444 s32 ret = IXGBE_NOT_IMPLEMENTED;
445 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
446 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
447 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
448 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
449 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
451 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
452 ixgbe_dcb_unpack_max_cee(dcb_config, max);
453 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
454 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
455 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
457 switch (hw->mac.type) {
458 case ixgbe_mac_82598EB:
459 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
461 case ixgbe_mac_82599EB:
464 case ixgbe_mac_X550EM_x:
465 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
475 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
476 * @hw: pointer to hardware structure
477 * @dcb_config: pointer to ixgbe_dcb_config structure
479 * Configure Tx Descriptor Arbiter and credits for each traffic class.
481 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
482 struct ixgbe_dcb_config *dcb_config)
484 s32 ret = IXGBE_NOT_IMPLEMENTED;
485 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
486 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
487 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
488 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
490 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
491 ixgbe_dcb_unpack_max_cee(dcb_config, max);
492 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
493 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
495 switch (hw->mac.type) {
496 case ixgbe_mac_82598EB:
497 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
500 case ixgbe_mac_82599EB:
503 case ixgbe_mac_X550EM_x:
504 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
514 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
515 * @hw: pointer to hardware structure
516 * @dcb_config: pointer to ixgbe_dcb_config structure
518 * Configure Tx Data Arbiter and credits for each traffic class.
520 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
521 struct ixgbe_dcb_config *dcb_config)
523 s32 ret = IXGBE_NOT_IMPLEMENTED;
524 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
525 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
526 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
527 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
528 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
530 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
531 ixgbe_dcb_unpack_max_cee(dcb_config, max);
532 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
533 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
534 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
536 switch (hw->mac.type) {
537 case ixgbe_mac_82598EB:
538 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
541 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X550EM_x:
545 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
556 * ixgbe_dcb_config_pfc_cee - Config priority flow control
557 * @hw: pointer to hardware structure
558 * @dcb_config: pointer to ixgbe_dcb_config structure
560 * Configure Priority Flow Control for each traffic class.
562 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
563 struct ixgbe_dcb_config *dcb_config)
565 s32 ret = IXGBE_NOT_IMPLEMENTED;
567 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
569 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
570 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
572 switch (hw->mac.type) {
573 case ixgbe_mac_82598EB:
574 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
576 case ixgbe_mac_82599EB:
579 case ixgbe_mac_X550EM_x:
580 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
589 * ixgbe_dcb_config_tc_stats - Config traffic class statistics
590 * @hw: pointer to hardware structure
592 * Configure queue statistics registers, all queues belonging to same traffic
593 * class uses a single set of queue statistics counters.
595 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
597 s32 ret = IXGBE_NOT_IMPLEMENTED;
598 switch (hw->mac.type) {
599 case ixgbe_mac_82598EB:
600 ret = ixgbe_dcb_config_tc_stats_82598(hw);
602 case ixgbe_mac_82599EB:
605 case ixgbe_mac_X550EM_x:
606 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
615 * ixgbe_dcb_hw_config_cee - Config and enable DCB
616 * @hw: pointer to hardware structure
617 * @dcb_config: pointer to ixgbe_dcb_config structure
619 * Configure dcb settings and enable dcb mode.
621 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
622 struct ixgbe_dcb_config *dcb_config)
624 s32 ret = IXGBE_NOT_IMPLEMENTED;
626 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
627 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
628 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
629 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
630 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
632 /* Unpack CEE standard containers */
633 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
634 ixgbe_dcb_unpack_max_cee(dcb_config, max);
635 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
636 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
637 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
639 switch (hw->mac.type) {
640 case ixgbe_mac_82598EB:
641 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
642 refill, max, bwgid, tsa);
644 case ixgbe_mac_82599EB:
647 case ixgbe_mac_X550EM_x:
648 ixgbe_dcb_config_82599(hw, dcb_config);
649 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
653 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
659 if (!ret && dcb_config->pfc_mode_enable) {
660 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
661 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
667 /* Helper routines to abstract HW specifics from DCB netlink ops */
668 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
670 int ret = IXGBE_ERR_PARAM;
672 switch (hw->mac.type) {
673 case ixgbe_mac_82598EB:
674 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
676 case ixgbe_mac_82599EB:
679 case ixgbe_mac_X550EM_x:
680 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
688 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
689 u8 *bwg_id, u8 *tsa, u8 *map)
691 switch (hw->mac.type) {
692 case ixgbe_mac_82598EB:
693 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
694 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
696 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
699 case ixgbe_mac_82599EB:
702 case ixgbe_mac_X550EM_x:
703 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
705 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
707 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,