4 * Copyright (C) Cavium networks Ltd. 2016.
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33 #ifndef _THUNDERX_NICVF_HW_DEFS_H
34 #define _THUNDERX_NICVF_HW_DEFS_H
39 #include "nicvf_plat.h"
41 /* Virtual function register offsets */
43 #define NIC_VF_CFG (0x000020)
44 #define NIC_VF_PF_MAILBOX_0_1 (0x000130)
45 #define NIC_VF_INT (0x000200)
46 #define NIC_VF_INT_W1S (0x000220)
47 #define NIC_VF_ENA_W1C (0x000240)
48 #define NIC_VF_ENA_W1S (0x000260)
50 #define NIC_VNIC_RSS_CFG (0x0020E0)
51 #define NIC_VNIC_RSS_KEY_0_4 (0x002200)
52 #define NIC_VNIC_TX_STAT_0_4 (0x004000)
53 #define NIC_VNIC_RX_STAT_0_13 (0x004100)
54 #define NIC_VNIC_RQ_GEN_CFG (0x010010)
56 #define NIC_QSET_CQ_0_7_CFG (0x010400)
57 #define NIC_QSET_CQ_0_7_CFG2 (0x010408)
58 #define NIC_QSET_CQ_0_7_THRESH (0x010410)
59 #define NIC_QSET_CQ_0_7_BASE (0x010420)
60 #define NIC_QSET_CQ_0_7_HEAD (0x010428)
61 #define NIC_QSET_CQ_0_7_TAIL (0x010430)
62 #define NIC_QSET_CQ_0_7_DOOR (0x010438)
63 #define NIC_QSET_CQ_0_7_STATUS (0x010440)
64 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
65 #define NIC_QSET_CQ_0_7_DEBUG (0x010450)
67 #define NIC_QSET_RQ_0_7_CFG (0x010600)
68 #define NIC_QSET_RQ_0_7_STATUS0 (0x010700)
69 #define NIC_QSET_RQ_0_7_STATUS1 (0x010708)
71 #define NIC_QSET_SQ_0_7_CFG (0x010800)
72 #define NIC_QSET_SQ_0_7_THRESH (0x010810)
73 #define NIC_QSET_SQ_0_7_BASE (0x010820)
74 #define NIC_QSET_SQ_0_7_HEAD (0x010828)
75 #define NIC_QSET_SQ_0_7_TAIL (0x010830)
76 #define NIC_QSET_SQ_0_7_DOOR (0x010838)
77 #define NIC_QSET_SQ_0_7_STATUS (0x010840)
78 #define NIC_QSET_SQ_0_7_DEBUG (0x010848)
79 #define NIC_QSET_SQ_0_7_STATUS0 (0x010900)
80 #define NIC_QSET_SQ_0_7_STATUS1 (0x010908)
82 #define NIC_QSET_RBDR_0_1_CFG (0x010C00)
83 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
84 #define NIC_QSET_RBDR_0_1_BASE (0x010C20)
85 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
86 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
87 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
88 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
89 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
90 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS (0x010C50)
92 /* vNIC HW Constants */
94 #define NIC_Q_NUM_SHIFT 18
96 #define MAX_QUEUE_SET 128
97 #define MAX_RCV_QUEUES_PER_QS 8
98 #define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
99 #define MAX_SND_QUEUES_PER_QS 8
100 #define MAX_CMP_QUEUES_PER_QS 8
102 #define NICVF_INTR_CQ_SHIFT 0
103 #define NICVF_INTR_SQ_SHIFT 8
104 #define NICVF_INTR_RBDR_SHIFT 16
105 #define NICVF_INTR_PKT_DROP_SHIFT 20
106 #define NICVF_INTR_TCP_TIMER_SHIFT 21
107 #define NICVF_INTR_MBOX_SHIFT 22
108 #define NICVF_INTR_QS_ERR_SHIFT 23
110 #define NICVF_QS_RQ_DIS_APAD_SHIFT 22
112 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
113 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
114 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
115 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT)
116 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT)
117 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT)
118 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT)
119 #define NICVF_INTR_ALL_MASK (0x7FFFFF)
121 #define NICVF_CQ_WR_FULL (1ULL << 26)
122 #define NICVF_CQ_WR_DISABLE (1ULL << 25)
123 #define NICVF_CQ_WR_FAULT (1ULL << 24)
124 #define NICVF_CQ_ERR_MASK (NICVF_CQ_WR_FULL |\
125 NICVF_CQ_WR_DISABLE |\
127 #define NICVF_CQ_CQE_COUNT_MASK (0xFFFF)
129 #define NICVF_SQ_ERR_STOPPED (1ULL << 21)
130 #define NICVF_SQ_ERR_SEND (1ULL << 20)
131 #define NICVF_SQ_ERR_DPE (1ULL << 19)
132 #define NICVF_SQ_ERR_MASK (NICVF_SQ_ERR_STOPPED |\
135 #define NICVF_SQ_STATUS_STOPPED_BIT (21)
137 #define NICVF_RBDR_FIFO_STATE_SHIFT (62)
138 #define NICVF_RBDR_FIFO_STATE_MASK (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT)
139 #define NICVF_RBDR_COUNT_MASK (0x7FFFF)
142 #define NICVF_CQ_RESET (1ULL << 41)
143 #define NICVF_SQ_RESET (1ULL << 17)
144 #define NICVF_RBDR_RESET (1ULL << 43)
147 #define NIC_MAX_RSS_HASH_BITS (8)
148 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
149 #define RSS_HASH_KEY_SIZE (5) /* 320 bit key */
150 #define RSS_HASH_KEY_BYTE_SIZE (40) /* 320 bit key */
152 #define RSS_L2_EXTENDED_HASH_ENA (1 << 0)
153 #define RSS_IP_ENA (1 << 1)
154 #define RSS_TCP_ENA (1 << 2)
155 #define RSS_TCP_SYN_ENA (1 << 3)
156 #define RSS_UDP_ENA (1 << 4)
157 #define RSS_L4_EXTENDED_ENA (1 << 5)
158 #define RSS_L3_BI_DIRECTION_ENA (1 << 7)
159 #define RSS_L4_BI_DIRECTION_ENA (1 << 8)
160 #define RSS_TUN_VXLAN_ENA (1 << 9)
161 #define RSS_TUN_GENEVE_ENA (1 << 10)
162 #define RSS_TUN_NVGRE_ENA (1 << 11)
164 #define RBDR_QUEUE_SZ_8K (8 * 1024)
165 #define RBDR_QUEUE_SZ_16K (16 * 1024)
166 #define RBDR_QUEUE_SZ_32K (32 * 1024)
167 #define RBDR_QUEUE_SZ_64K (64 * 1024)
168 #define RBDR_QUEUE_SZ_128K (128 * 1024)
169 #define RBDR_QUEUE_SZ_256K (256 * 1024)
170 #define RBDR_QUEUE_SZ_512K (512 * 1024)
171 #define RBDR_QUEUE_SZ_MAX RBDR_QUEUE_SZ_512K
173 #define RBDR_SIZE_SHIFT (13) /* 8k */
175 #define SND_QUEUE_SZ_1K (1 * 1024)
176 #define SND_QUEUE_SZ_2K (2 * 1024)
177 #define SND_QUEUE_SZ_4K (4 * 1024)
178 #define SND_QUEUE_SZ_8K (8 * 1024)
179 #define SND_QUEUE_SZ_16K (16 * 1024)
180 #define SND_QUEUE_SZ_32K (32 * 1024)
181 #define SND_QUEUE_SZ_64K (64 * 1024)
182 #define SND_QUEUE_SZ_MAX SND_QUEUE_SZ_64K
184 #define SND_QSIZE_SHIFT (10) /* 1k */
186 #define CMP_QUEUE_SZ_1K (1 * 1024)
187 #define CMP_QUEUE_SZ_2K (2 * 1024)
188 #define CMP_QUEUE_SZ_4K (4 * 1024)
189 #define CMP_QUEUE_SZ_8K (8 * 1024)
190 #define CMP_QUEUE_SZ_16K (16 * 1024)
191 #define CMP_QUEUE_SZ_32K (32 * 1024)
192 #define CMP_QUEUE_SZ_64K (64 * 1024)
193 #define CMP_QUEUE_SZ_MAX CMP_QUEUE_SZ_64K
195 #define CMP_QSIZE_SHIFT (10) /* 1k */
197 #define NICVF_QSIZE_MIN_VAL (0)
198 #define NICVF_QSIZE_MAX_VAL (6)
200 /* Min/Max packet size */
201 #define NIC_HW_MIN_FRS (64)
202 #define NIC_HW_MAX_FRS (9200) /* 9216 max pkt including FCS */
203 #define NIC_HW_MAX_SEGS (12)
205 /* Descriptor alignments */
206 #define NICVF_RBDR_BASE_ALIGN_BYTES (128) /* 7 bits */
207 #define NICVF_CQ_BASE_ALIGN_BYTES (512) /* 9 bits */
208 #define NICVF_SQ_BASE_ALIGN_BYTES (128) /* 7 bits */
210 #define NICVF_CQE_RBPTR_WORD (6)
211 #define NICVF_CQE_RX2_RBPTR_WORD (7)
213 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
214 #define assert_primary(nic) assert((nic)->sqs_mode == 0)
216 typedef uint64_t nicvf_phys_addr_t;
218 /* vNIC HW Enumerations */
220 enum nic_send_ld_type_e {
221 NIC_SEND_LD_TYPE_E_LDD,
222 NIC_SEND_LD_TYPE_E_LDT,
223 NIC_SEND_LD_TYPE_E_LDWB,
224 NIC_SEND_LD_TYPE_E_ENUM_LAST,
227 enum ether_type_algorithm {
232 ETYPE_ALG_VLAN_STRIP,
239 L3TYPE_IPV4_OPTIONS = 0x5,
241 L3TYPE_IPV6_OPTIONS = 0x7,
242 L3TYPE_ET_STOP = 0xD,
246 #define NICVF_L3TYPE_OPTIONS_MASK ((uint8_t)1)
247 #define NICVF_L3TYPE_IPVX_MASK ((uint8_t)0x06)
262 /* CPI and RSSI configuration */
263 enum cpi_algorithm_type {
270 enum rss_algorithm_type {
285 RSS_HASH_TCP_SYN_DIS,
293 /* Completion queue entry types */
297 CQE_TYPE_RX_SPLIT = 0x3,
298 CQE_TYPE_RX_TCP = 0x4,
300 CQE_TYPE_SEND_PTP = 0x9,
303 enum cqe_rx_tcp_status {
304 CQE_RX_STATUS_VALID_TCP_CNXT,
305 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
308 enum cqe_send_status {
309 CQE_SEND_STATUS_GOOD,
310 CQE_SEND_STATUS_DESC_FAULT = 0x01,
311 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
312 CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
313 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
314 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
315 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
316 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
317 CQE_SEND_STATUS_LOCK_VIOL = 0x84,
318 CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
319 CQE_SEND_STATUS_DATA_FAULT = 0x86,
320 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
321 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
322 CQE_SEND_STATUS_MEM_FAULT = 0x89,
323 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
324 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
327 enum cqe_rx_tcp_end_reason {
328 CQE_RX_TCP_END_FIN_FLAG_DET,
329 CQE_RX_TCP_END_INVALID_FLAG,
330 CQE_RX_TCP_END_TIMEOUT,
331 CQE_RX_TCP_END_OUT_OF_SEQ,
332 CQE_RX_TCP_END_PKT_ERR,
333 CQE_RX_TCP_END_QS_DISABLED = 0x0F,
336 /* Packet protocol level error enumeration */
337 enum cqe_rx_err_level {
344 /* Packet protocol level error type enumeration */
345 enum cqe_rx_err_opcode {
347 CQE_RX_ERR_RE_PARTIAL,
348 CQE_RX_ERR_RE_JABBER,
349 CQE_RX_ERR_RE_FCS = 0x7,
350 CQE_RX_ERR_RE_TERMINATE = 0x9,
351 CQE_RX_ERR_RE_RX_CTL = 0xb,
352 CQE_RX_ERR_PREL2_ERR = 0x1f,
353 CQE_RX_ERR_L2_FRAGMENT = 0x20,
354 CQE_RX_ERR_L2_OVERRUN = 0x21,
355 CQE_RX_ERR_L2_PFCS = 0x22,
356 CQE_RX_ERR_L2_PUNY = 0x23,
357 CQE_RX_ERR_L2_MAL = 0x24,
358 CQE_RX_ERR_L2_OVERSIZE = 0x25,
359 CQE_RX_ERR_L2_UNDERSIZE = 0x26,
360 CQE_RX_ERR_L2_LENMISM = 0x27,
361 CQE_RX_ERR_L2_PCLP = 0x28,
362 CQE_RX_ERR_IP_NOT = 0x41,
363 CQE_RX_ERR_IP_CHK = 0x42,
364 CQE_RX_ERR_IP_MAL = 0x43,
365 CQE_RX_ERR_IP_MALD = 0x44,
366 CQE_RX_ERR_IP_HOP = 0x45,
367 CQE_RX_ERR_L3_ICRC = 0x46,
368 CQE_RX_ERR_L3_PCLP = 0x47,
369 CQE_RX_ERR_L4_MAL = 0x61,
370 CQE_RX_ERR_L4_CHK = 0x62,
371 CQE_RX_ERR_UDP_LEN = 0x63,
372 CQE_RX_ERR_L4_PORT = 0x64,
373 CQE_RX_ERR_TCP_FLAG = 0x65,
374 CQE_RX_ERR_TCP_OFFSET = 0x66,
375 CQE_RX_ERR_L4_PCLP = 0x67,
376 CQE_RX_ERR_RBDR_TRUNC = 0x70,
379 enum send_l4_csum_type {
380 SEND_L4_CSUM_DISABLE,
391 enum send_load_type {
397 enum send_mem_alg_type {
399 SEND_MEMALG_ADD = 0x08,
400 SEND_MEMALG_SUB = 0x09,
401 SEND_MEMALG_ADDLEN = 0x0A,
402 SEND_MEMALG_SUBLEN = 0x0B,
405 enum send_mem_dsz_type {
408 SEND_MEMDSZ_B8 = 0x03,
411 enum sq_subdesc_type {
412 SQ_DESC_TYPE_INVALID,
415 SQ_DESC_TYPE_IMMEDIATE,
439 L4_UDP_GENEVE = 0x09,
453 RBDR_FIFO_STATE_INACTIVE,
454 RBDR_FIFO_STATE_ACTIVE,
455 RBDR_FIFO_STATE_RESET,
456 RBDR_FIFO_STATE_FAIL,
459 enum rq_cache_allocation {
462 RQ_CACHE_ALLOC_FIRST,
466 enum cq_rx_errlvl_e {
475 CQ_RX_ERROP_RE_PARTIAL = 0x1,
476 CQ_RX_ERROP_RE_JABBER = 0x2,
477 CQ_RX_ERROP_RE_FCS = 0x7,
478 CQ_RX_ERROP_RE_TERMINATE = 0x9,
479 CQ_RX_ERROP_RE_RX_CTL = 0xb,
480 CQ_RX_ERROP_PREL2_ERR = 0x1f,
481 CQ_RX_ERROP_L2_FRAGMENT = 0x20,
482 CQ_RX_ERROP_L2_OVERRUN = 0x21,
483 CQ_RX_ERROP_L2_PFCS = 0x22,
484 CQ_RX_ERROP_L2_PUNY = 0x23,
485 CQ_RX_ERROP_L2_MAL = 0x24,
486 CQ_RX_ERROP_L2_OVERSIZE = 0x25,
487 CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
488 CQ_RX_ERROP_L2_LENMISM = 0x27,
489 CQ_RX_ERROP_L2_PCLP = 0x28,
490 CQ_RX_ERROP_IP_NOT = 0x41,
491 CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
492 CQ_RX_ERROP_IP_MAL = 0x43,
493 CQ_RX_ERROP_IP_MALD = 0x44,
494 CQ_RX_ERROP_IP_HOP = 0x45,
495 CQ_RX_ERROP_L3_ICRC = 0x46,
496 CQ_RX_ERROP_L3_PCLP = 0x47,
497 CQ_RX_ERROP_L4_MAL = 0x61,
498 CQ_RX_ERROP_L4_CHK = 0x62,
499 CQ_RX_ERROP_UDP_LEN = 0x63,
500 CQ_RX_ERROP_L4_PORT = 0x64,
501 CQ_RX_ERROP_TCP_FLAG = 0x65,
502 CQ_RX_ERROP_TCP_OFFSET = 0x66,
503 CQ_RX_ERROP_L4_PCLP = 0x67,
504 CQ_RX_ERROP_RBDR_TRUNC = 0x70,
509 CQ_TX_ERROP_DESC_FAULT = 0x10,
510 CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
511 CQ_TX_ERROP_SUBDC_ERR = 0x12,
512 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
513 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
514 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
515 CQ_TX_ERROP_LOCK_VIOL = 0x83,
516 CQ_TX_ERROP_DATA_FAULT = 0x84,
517 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
518 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
519 CQ_TX_ERROP_MEM_FAULT = 0x87,
520 CQ_TX_ERROP_CK_OVERLAP = 0x88,
521 CQ_TX_ERROP_CK_OFLOW = 0x89,
522 CQ_TX_ERROP_ENUM_LAST = 0x8a,
525 enum rq_sq_stats_reg_offset {
530 enum nic_stat_vnic_rx_e {
547 enum nic_stat_vnic_tx_e {
555 /* vNIC HW Register structures */
560 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
562 uint64_t stdn_fault:1;
570 uint64_t vlan_found:1;
571 uint64_t vlan_stripped:1;
572 uint64_t vlan2_found:1;
573 uint64_t vlan2_stripped:1;
576 uint64_t l2_present:1;
577 uint64_t err_level:3;
578 uint64_t err_opcode:8;
580 uint64_t err_opcode:8;
581 uint64_t err_level:3;
582 uint64_t l2_present:1;
585 uint64_t vlan2_stripped:1;
586 uint64_t vlan2_found:1;
587 uint64_t vlan_stripped:1;
588 uint64_t vlan_found:1;
596 uint64_t stdn_fault:1;
605 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
610 uint64_t cq_pkt_len:8;
611 uint64_t align_pad:3;
617 uint64_t align_pad:3;
618 uint64_t cq_pkt_len:8;
630 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
632 uint64_t vlan_tci:16;
634 uint64_t vlan2_ptr:8;
636 uint64_t vlan2_ptr:8;
638 uint64_t vlan_tci:16;
647 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
664 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
681 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
698 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
699 uint64_t vlan_found:1;
700 uint64_t vlan_stripped:1;
701 uint64_t vlan2_found:1;
702 uint64_t vlan2_stripped:1;
705 uint64_t inner_l4type:4;
706 uint64_t inner_l3type:4;
708 uint64_t vlan2_ptr:8;
711 uint64_t inner_l3ptr:8;
712 uint64_t inner_l4ptr:8;
714 uint64_t inner_l4ptr:8;
715 uint64_t inner_l3ptr:8;
718 uint64_t vlan2_ptr:8;
720 uint64_t inner_l3type:4;
721 uint64_t inner_l4type:4;
724 uint64_t vlan2_stripped:1;
725 uint64_t vlan2_found:1;
726 uint64_t vlan_stripped:1;
727 uint64_t vlan_found:1;
733 cqe_rx_word0_t word0;
734 cqe_rx_word1_t word1;
735 cqe_rx_word2_t word2;
736 cqe_rx_word3_t word3;
737 cqe_rx_word4_t word4;
738 cqe_rx_word5_t word5;
739 cqe_rx2_word6_t word6; /* if NIC_PF_RX_CFG[CQE_RX2_ENA] set */
742 struct cqe_rx_tcp_err_t {
743 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
744 uint64_t cqe_type:4; /* W0 */
747 uint64_t rsvd1:4; /* W1 */
748 uint64_t partial_first:1;
750 uint64_t rbdr_bytes:8;
757 uint64_t rbdr_bytes:8;
759 uint64_t partial_first:1;
764 struct cqe_rx_tcp_t {
765 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
766 uint64_t cqe_type:4; /* W0 */
768 uint64_t cq_tcp_status:8;
770 uint64_t rsvd1:32; /* W1 */
771 uint64_t tcp_cntx_bytes:8;
773 uint64_t tcp_err_bytes:16;
775 uint64_t cq_tcp_status:8;
777 uint64_t cqe_type:4; /* W0 */
779 uint64_t tcp_err_bytes:16;
781 uint64_t tcp_cntx_bytes:8;
782 uint64_t rsvd1:32; /* W1 */
787 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
788 uint64_t cqe_type:4; /* W0 */
796 uint64_t send_status:8;
798 uint64_t ptp_timestamp:64; /* W1 */
799 #elif NICVF_BYTE_ORDER == NICVF_LITTLE_ENDIAN
800 uint64_t send_status:8;
808 uint64_t cqe_type:4; /* W0 */
810 uint64_t ptp_timestamp:64;
814 struct cq_entry_type_t {
815 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
826 struct cq_entry_type_t type;
827 struct cqe_rx_t rx_hdr;
828 struct cqe_rx_tcp_t rx_tcp_hdr;
829 struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
830 struct cqe_send_t cqe_send;
833 NICVF_STATIC_ASSERT(sizeof(union cq_entry_t) == 512);
835 struct rbdr_entry_t {
836 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
840 uint64_t buf_addr:42;
841 uint64_t cache_align:7;
843 nicvf_phys_addr_t full_addr;
848 uint64_t cache_align:7;
849 uint64_t buf_addr:42;
852 nicvf_phys_addr_t full_addr;
857 NICVF_STATIC_ASSERT(sizeof(struct rbdr_entry_t) == sizeof(uint64_t));
859 /* TCP reassembly context */
860 struct rbe_tcp_cnxt_t {
861 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
862 uint64_t tcp_pkt_cnt:12;
864 uint64_t align_hdr_bytes:4;
865 uint64_t align_ptr_bytes:4;
866 uint64_t ptr_bytes:16;
870 uint64_t tcp_end_reason:2;
871 uint64_t tcp_status:4;
873 uint64_t tcp_status:4;
874 uint64_t tcp_end_reason:2;
878 uint64_t ptr_bytes:16;
879 uint64_t align_ptr_bytes:4;
880 uint64_t align_hdr_bytes:4;
882 uint64_t tcp_pkt_cnt:12;
886 /* Always Big endian */
890 uint64_t skip_length:6;
891 uint64_t disable_rss:1;
892 uint64_t disable_tcp_reassembly:1;
899 struct sq_crc_subdesc {
900 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
902 uint64_t crc_ival:32;
903 uint64_t subdesc_type:4;
906 uint64_t crc_insert_pos:16;
907 uint64_t hdr_start:16;
911 uint64_t hdr_start:16;
912 uint64_t crc_insert_pos:16;
915 uint64_t subdesc_type:4;
916 uint64_t crc_ival:32;
921 struct sq_gather_subdesc {
922 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
923 uint64_t subdesc_type:4; /* W0 */
928 uint64_t rsvd1:15; /* W1 */
934 uint64_t subdesc_type:4; /* W0 */
937 uint64_t rsvd1:15; /* W1 */
941 /* SQ immediate subdescriptor */
942 struct sq_imm_subdesc {
943 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
944 uint64_t subdesc_type:4; /* W0 */
948 uint64_t data:64; /* W1 */
952 uint64_t subdesc_type:4; /* W0 */
954 uint64_t data:64; /* W1 */
958 struct sq_mem_subdesc {
959 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
960 uint64_t subdesc_type:4; /* W0 */
967 uint64_t rsvd1:15; /* W1 */
975 uint64_t subdesc_type:4; /* W0 */
978 uint64_t rsvd1:15; /* W1 */
982 struct sq_hdr_subdesc {
983 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
984 uint64_t subdesc_type:4;
986 uint64_t post_cqe:1; /* Post CQE on no error also */
987 uint64_t dont_send:1;
989 uint64_t subdesc_cnt:8;
992 uint64_t csum_inner_l4:2;
993 uint64_t csum_inner_l3:1;
995 uint64_t l4_offset:8;
996 uint64_t l3_offset:8;
998 uint64_t tot_len:20; /* W0 */
1001 uint64_t inner_l4_offset:8;
1002 uint64_t inner_l3_offset:8;
1003 uint64_t tso_start:8;
1005 uint64_t tso_max_paysize:14; /* W1 */
1007 uint64_t tot_len:20;
1009 uint64_t l3_offset:8;
1010 uint64_t l4_offset:8;
1012 uint64_t csum_inner_l3:1;
1013 uint64_t csum_inner_l4:2;
1016 uint64_t subdesc_cnt:8;
1018 uint64_t dont_send:1;
1019 uint64_t post_cqe:1; /* Post CQE on no error also */
1021 uint64_t subdesc_type:4; /* W0 */
1023 uint64_t tso_max_paysize:14;
1025 uint64_t tso_start:8;
1026 uint64_t inner_l3_offset:8;
1027 uint64_t inner_l4_offset:8;
1028 uint64_t rsvd2:24; /* W1 */
1032 /* Each sq entry is 128 bits wide */
1035 struct sq_hdr_subdesc hdr;
1036 struct sq_imm_subdesc imm;
1037 struct sq_gather_subdesc gather;
1038 struct sq_crc_subdesc crc;
1039 struct sq_mem_subdesc mem;
1042 NICVF_STATIC_ASSERT(sizeof(union sq_entry_t) == 16);
1044 /* Queue config register formats */
1045 struct rq_cfg { union { struct {
1046 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1047 uint64_t reserved_2_63:62;
1049 uint64_t reserved_0:1;
1051 uint64_t reserved_0:1;
1053 uint64_t reserved_2_63:62;
1059 struct cq_cfg { union { struct {
1060 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1061 uint64_t reserved_43_63:21;
1065 uint64_t reserved_35_39:5;
1067 uint64_t reserved_25_31:7;
1069 uint64_t reserved_0_15:16;
1071 uint64_t reserved_0_15:16;
1073 uint64_t reserved_25_31:7;
1075 uint64_t reserved_35_39:5;
1079 uint64_t reserved_43_63:21;
1085 struct sq_cfg { union { struct {
1086 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1087 uint64_t reserved_20_63:44;
1089 uint64_t reserved_18_18:1;
1092 uint64_t reserved_11_15:5;
1094 uint64_t reserved_3_7:5;
1095 uint64_t tstmp_bgx_intf:3;
1097 uint64_t tstmp_bgx_intf:3;
1098 uint64_t reserved_3_7:5;
1100 uint64_t reserved_11_15:5;
1103 uint64_t reserved_18_18:1;
1105 uint64_t reserved_20_63:44;
1111 struct rbdr_cfg { union { struct {
1112 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1113 uint64_t reserved_45_63:19;
1117 uint64_t reserved_36_41:6;
1119 uint64_t reserved_25_31:7;
1121 uint64_t reserved_12_15:4;
1125 uint64_t reserved_12_15:4;
1127 uint64_t reserved_25_31:7;
1129 uint64_t reserved_36_41:6;
1133 uint64_t reserved_45_63:19;
1139 struct pf_qs_cfg { union { struct {
1140 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1141 uint64_t reserved_32_63:32;
1143 uint64_t reserved_27_30:4;
1144 uint64_t sq_ins_ena:1;
1145 uint64_t sq_ins_pos:6;
1146 uint64_t lock_ena:1;
1147 uint64_t lock_viol_cqe_ena:1;
1148 uint64_t send_tstmp_ena:1;
1150 uint64_t reserved_7_15:9;
1154 uint64_t reserved_7_15:9;
1156 uint64_t send_tstmp_ena:1;
1157 uint64_t lock_viol_cqe_ena:1;
1158 uint64_t lock_ena:1;
1159 uint64_t sq_ins_pos:6;
1160 uint64_t sq_ins_ena:1;
1161 uint64_t reserved_27_30:4;
1163 uint64_t reserved_32_63:32;
1169 struct pf_rq_cfg { union { struct {
1170 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1171 uint64_t reserved1:1;
1172 uint64_t reserved0:34;
1173 uint64_t strip_pre_l2:1;
1177 uint64_t rbdr_cont_qs:7;
1178 uint64_t rbdr_cont_idx:1;
1179 uint64_t rbdr_strt_qs:7;
1180 uint64_t rbdr_strt_idx:1;
1182 uint64_t rbdr_strt_idx:1;
1183 uint64_t rbdr_strt_qs:7;
1184 uint64_t rbdr_cont_idx:1;
1185 uint64_t rbdr_cont_qs:7;
1189 uint64_t strip_pre_l2:1;
1190 uint64_t reserved0:34;
1191 uint64_t reserved1:1;
1197 struct pf_rq_drop_cfg { union { struct {
1198 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
1199 uint64_t rbdr_red:1;
1201 uint64_t reserved3:14;
1202 uint64_t rbdr_pass:8;
1203 uint64_t rbdr_drop:8;
1204 uint64_t reserved2:8;
1207 uint64_t reserved1:8;
1209 uint64_t reserved1:8;
1212 uint64_t reserved2:8;
1213 uint64_t rbdr_drop:8;
1214 uint64_t rbdr_pass:8;
1215 uint64_t reserved3:14;
1217 uint64_t rbdr_red:1;
1223 #endif /* _THUNDERX_NICVF_HW_DEFS_H */