2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written consent.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
40 #include "bnx2x_ethdev.h"
42 #if __BYTE_ORDER == __LITTLE_ENDIAN
46 #ifndef __LITTLE_ENDIAN
47 #define __LITTLE_ENDIAN
51 #else /* _BIG_ENDIAN */
59 #undef __LITTLE_ENDIAN
62 #include "ecore_mfw_req.h"
63 #include "ecore_fw_defs.h"
64 #include "ecore_hsi.h"
65 #include "ecore_reg.h"
66 #include "bnx2x_stats.h"
67 #include "bnx2x_vfpf.h"
71 #include <linux/pci_regs.h>
73 #define PCIY_PMG PCI_CAP_ID_PM
74 #define PCIY_MSI PCI_CAP_ID_MSI
75 #define PCIY_EXPRESS PCI_CAP_ID_EXP
76 #define PCIY_MSIX PCI_CAP_ID_MSIX
77 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
78 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
79 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
80 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
81 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
82 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
83 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
84 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
85 #define PCIR_POWER_STATUS PCI_PM_CTRL
86 #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
87 #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
88 #define PCIM_PSTAT_D3 0x3
89 #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
90 #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
91 #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
93 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
94 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
95 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
97 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
98 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
99 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
100 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
101 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
102 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
103 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
104 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
107 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
110 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
113 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
116 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
120 int bnx2x_ilog2(int x)
131 #define ilog2(x) bnx2x_ilog2(x)
134 #include "ecore_sp.h"
136 struct bnx2x_device_type {
144 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
145 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
147 #define BNX2X_PAGE_SHIFT 12
148 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
149 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
150 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
152 #if BNX2X_PAGE_SIZE != 4096
153 #error Page sizes other than 4KB are unsupported!
156 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
157 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
158 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
160 /* dropless fc FW/HW related params */
161 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
162 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
163 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
164 #define FW_PREFETCH_CNT 16U
165 #define DROPLESS_FC_HEADROOM 100
170 #define MCLBYTES (1 << MCLSHIFT)
172 #if BNX2X_PAGE_SIZE < 2048
173 #define MJUMPAGESIZE MCLBYTES
174 #elif BNX2X_PAGE_SIZE <= 8192
175 #define MJUMPAGESIZE BNX2X_PAGE_SIZE
177 #define MJUMPAGESIZE (8 * 1024)
179 #define MJUM9BYTES (9 * 1024)
180 #define MJUM16BYTES (16 * 1024)
183 * Transmit Buffer Descriptor (tx_bd) definitions*
185 /* NUM_TX_PAGES must be a power of 2. */
186 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
187 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
189 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
190 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
191 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
193 #define NEXT_TX_BD(x) \
194 ((((x) & USABLE_TX_BD_PER_PAGE) == \
195 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
197 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
198 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
199 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
202 * Trigger pending transmits when the number of available BDs is greater
203 * than 1/8 of the total number of usable BDs.
205 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
206 #define BNX2X_TX_TIMEOUT 5
209 * Receive Buffer Descriptor (rx_bd) definitions*
211 //#define NUM_RX_PAGES 1
212 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
213 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
214 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
215 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
216 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
217 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
218 #define RX_BD_NEXT_PAGE_DESC_CNT 2
220 #define NEXT_RX_BD(x) \
221 ((((x) & RX_BD_PER_PAGE_MASK) == \
222 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
225 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
226 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
227 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
230 * Receive Completion Queue definitions*
232 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
233 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
234 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
235 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
236 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
237 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
238 #define RCQ_NEXT_PAGE_DESC_CNT 1
240 #define NEXT_RCQ_IDX(x) \
241 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
242 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
245 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
247 #define RCQ_BD_PAGES(q) \
248 (q->nb_rx_pages * CQE_BD_REL)
250 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
251 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
252 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
255 * dropless fc calculations for BDs
256 * Number of BDs should be as number of buffers in BRB:
257 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
258 * "next" elements on each page
260 #define NUM_BD_REQ(sc) \
262 #define NUM_BD_PG_REQ(sc) \
263 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
264 #define BD_TH_LO(sc) \
266 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
268 #define BD_TH_HI(sc) \
269 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
270 #define MIN_RX_AVAIL(sc) \
271 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
274 * dropless fc calculations for RCQs
275 * Number of RCQs should be as number of buffers in BRB:
276 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
277 * "next" elements on each page
279 #define NUM_RCQ_REQ(sc) \
281 #define NUM_RCQ_PG_REQ(sc) \
282 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
283 #define RCQ_TH_LO(sc) \
285 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
287 #define RCQ_TH_HI(sc) \
288 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
290 /* Load / Unload modes */
291 #define LOAD_NORMAL 0
294 #define LOAD_LOOPBACK_EXT 3
295 #define UNLOAD_NORMAL 0
296 #define UNLOAD_CLOSE 1
297 #define UNLOAD_RECOVERY 2
299 /* Some constants... */
300 //#define MAX_PATH_NUM 2
301 //#define E2_MAX_NUM_OF_VFS 64
302 //#define E1H_FUNC_MAX 8
303 //#define E2_FUNC_MAX 4 /* per path */
304 #define MAX_VNIC_NUM 4
305 #define MAX_FUNC_NUM 8 /* common to all chips */
306 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
307 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
308 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
310 #define ILT_NUM_PAGE_ENTRIES 3072
312 * 57711 we use whole table since we have 8 functions.
313 * 57712 we have only 4 functions, but use same size per func, so only half
314 * of the table is used.
316 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
317 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
319 * the phys address is shifted right 12 bits and has an added
320 * 1=valid bit added to the 53rd bit
321 * then since this is a wide register(TM)
322 * we split it into two 32 bit writes
324 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
325 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
327 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
329 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
330 #define ETH_MIN_PACKET_SIZE 60
331 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
332 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
333 /* TCP with Timestamp Option (32) + IPv6 (40) */
335 /* max supported alignment is 256 (8 shift) */
336 #define BNX2X_RX_ALIGN_SHIFT 8
337 /* FW uses 2 cache lines alignment for start packet and size */
338 #define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
339 #define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)
341 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
347 /* Used to manage DMA allocations. */
349 struct bnx2x_softc *sc;
353 char msg[RTE_MEMZONE_NAMESIZE - 6];
356 /* attn group wiring */
357 #define MAX_DYNAMIC_ATTN_GRPS 8
371 union bnx2x_host_hc_status_block {
372 /* pointer to fp status block e2 */
373 struct host_hc_status_block_e2 *e2_sb;
374 /* pointer to fp status block e1x */
375 struct host_hc_status_block_e1x *e1x_sb;
378 union bnx2x_db_prod {
379 struct doorbell_set_prod data;
383 struct bnx2x_sw_tx_bd {
387 /* set on the first BD descriptor when there is a split BD */
388 #define BNX2X_TSO_SPLIT_BD (1 << 0)
392 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
393 * instances of the fastpath structure when using multiple queues.
395 struct bnx2x_fastpath {
396 /* pointer back to parent structure */
397 struct bnx2x_softc *sc;
400 struct bnx2x_dma sb_dma;
401 union bnx2x_host_hc_status_block status_block;
403 phys_addr_t tx_desc_mapping;
405 phys_addr_t rx_desc_mapping;
406 phys_addr_t rx_comp_mapping;
408 uint16_t *sb_index_values;
409 uint16_t *sb_running_index;
410 uint32_t ustorm_rx_prods_offset;
412 uint8_t igu_sb_id; /* status block number in HW */
413 uint8_t fw_sb_id; /* status block number in FW */
415 uint32_t rx_buf_size;
419 #define BNX2X_FP_STATE_CLOSED 0x01
420 #define BNX2X_FP_STATE_IRQ 0x02
421 #define BNX2X_FP_STATE_OPENING 0x04
422 #define BNX2X_FP_STATE_OPEN 0x08
423 #define BNX2X_FP_STATE_HALTING 0x10
424 #define BNX2X_FP_STATE_HALTED 0x20
426 /* reference back to this fastpath queue number */
427 uint8_t index; /* this is also the 'cid' */
428 #define FP_IDX(fp) (fp->index)
430 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
432 #define FP_CL_ID(fp) (fp->cl_id)
437 union bnx2x_db_prod tx_db;
439 struct tstorm_per_queue_stats old_tclient;
440 struct ustorm_per_queue_stats old_uclient;
441 struct xstorm_per_queue_stats old_xclient;
442 struct bnx2x_eth_q_stats eth_q_stats;
443 struct bnx2x_eth_q_stats_old eth_q_stats_old;
445 /* Pointer to the receive consumer in the status block */
446 uint16_t *rx_cq_cons_sb;
448 /* Pointer to the transmit consumer in the status block */
449 uint16_t *tx_cons_sb;
451 /* transmit timeout until chip reset */
454 }; /* struct bnx2x_fastpath */
456 #define BNX2X_MAX_NUM_OF_VFS 64
457 #define BNX2X_VF_ID_INVALID 0xFF
459 /* maximum number of fast-path interrupt contexts */
460 #define FP_SB_MAX_E1x 16
461 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
464 struct eth_context eth;
468 /* CDU host DB constants */
469 #define CDU_ILT_PAGE_SZ_HW 2
470 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
471 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
473 #define CNIC_ISCSI_CID_MAX 256
474 #define CNIC_FCOE_CID_MAX 2048
475 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
476 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
478 #define QM_ILT_PAGE_SZ_HW 0
479 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
480 #define QM_CID_ROUND 1024
482 /* TM (timers) host DB constants */
483 #define TM_ILT_PAGE_SZ_HW 0
484 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
485 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
486 #define TM_CONN_NUM 1024
487 #define TM_ILT_SZ (8 * TM_CONN_NUM)
488 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
490 /* SRC (Searcher) host DB constants */
491 #define SRC_ILT_PAGE_SZ_HW 0
492 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
493 #define SRC_HASH_BITS 10
494 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
495 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
496 #define SRC_T2_SZ SRC_ILT_SZ
497 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
500 struct bnx2x_dma vcxt_dma;
501 union cdu_context *vcxt;
502 //phys_addr_t cxt_mapping;
509 /* defines for multiple tx priority indices */
510 #define FIRST_TX_ONLY_COS_INDEX 1
511 #define FIRST_TX_COS_INDEX 0
513 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
515 #define HC_INDEX_ETH_RX_CQ_CONS 1
516 #define HC_INDEX_OOO_TX_CQ_CONS 4
517 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
518 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
519 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
520 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
522 /* congestion management fairness mode */
523 #define CMNG_FNS_NONE 0
524 #define CMNG_FNS_MINMAX 1
526 /* CMNG constants, as derived from system spec calculations */
527 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
528 #define DEF_MIN_RATE 100
529 /* resolution of the rate shaping timer - 400 usec */
530 #define RS_PERIODIC_TIMEOUT_USEC 400
531 /* number of bytes in single QM arbitration cycle -
532 * coefficient for calculating the fairness timer */
533 #define QM_ARB_BYTES 160000
534 /* resolution of Min algorithm 1:100 */
536 /* how many bytes above threshold for the minimal credit of Min algorithm*/
537 #define MIN_ABOVE_THRESH 32768
538 /* fairness algorithm integration time coefficient -
539 * for calculating the actual Tfair */
540 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
541 /* memory of fairness algorithm - 2 cycles */
544 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
545 #define HC_SEG_ACCESS_ATTN 4
546 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
549 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
550 * control by the number of fast-path status blocks supported by the
551 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
552 * status block represents an independent interrupts context that can
553 * serve a regular L2 networking queue. However special L2 queues such
554 * as the FCoE queue do not require a FP-SB and other components like
555 * the CNIC may consume FP-SB reducing the number of possible L2 queues
557 * If the maximum number of FP-SB available is X then:
558 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
559 * regular L2 queues is Y=X-1
560 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
561 * c. If the FCoE L2 queue is supported the actual number of L2 queues
563 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
564 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
565 * FP interrupt context for the CNIC).
566 * e. The number of HW context (CID count) is always X or X+1 if FCoE
567 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
569 * So this is quite simple for now as no ULPs are supported yet. :-)
571 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
572 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
573 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
574 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
576 #define FOR_EACH_QUEUE(sc, var) \
577 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
579 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
580 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
582 #define FOR_EACH_ETH_QUEUE(sc, var) \
583 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
585 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
586 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
588 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
589 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
591 #define FOR_EACH_CNIC_QUEUE(sc, var) \
592 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
593 (var) < BNX2X_NUM_QUEUES(sc); \
602 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
603 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
604 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
605 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
606 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
607 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
609 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
610 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
611 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
612 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
613 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
615 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
616 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
617 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
618 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
619 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
620 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
622 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
623 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
624 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
625 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
626 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
627 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
628 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
631 BNX2X_PORT_QUERY_IDX,
633 BNX2X_FCOE_QUERY_IDX,
634 BNX2X_FIRST_QUEUE_QUERY_IDX,
637 struct bnx2x_fw_stats_req {
638 struct stats_query_header hdr;
639 struct stats_query_entry query[FP_SB_MAX_E1x +
640 BNX2X_FIRST_QUEUE_QUERY_IDX];
643 struct bnx2x_fw_stats_data {
644 struct stats_counter storm_counters;
645 struct per_port_stats port;
646 struct per_pf_stats pf;
647 struct per_queue_stats queue_stats[1];
650 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
651 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
652 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
657 * This is the slowpath data structure. It is mapped into non-paged memory
658 * so that the hardware can access it's contents directly and must be page
661 struct bnx2x_slowpath {
663 /* used by the DMAE command executer */
664 struct dmae_command dmae[MAX_DMAE_C];
666 /* statistics completion */
669 /* firmware defined statistics blocks */
670 union mac_stats mac_stats;
671 struct nig_stats nig_stats;
672 struct host_port_stats port_stats;
673 struct host_func_stats func_stats;
675 /* DMAE completion value and data source/sink */
680 struct mac_configuration_cmd e1x;
681 struct eth_classify_rules_ramrod_data e2;
685 struct tstorm_eth_mac_filter_config e1x;
686 struct eth_filter_rules_ramrod_data e2;
689 struct eth_rss_update_ramrod_data rss_rdata;
692 struct mac_configuration_cmd e1;
693 struct eth_multicast_rules_ramrod_data e2;
697 struct function_start_data func_start;
698 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
701 /* Queue State related ramrods */
703 struct client_init_ramrod_data init_data;
704 struct client_update_ramrod_data update_data;
708 * AFEX ramrod can not be a part of func_rdata union because these
709 * events might arrive in parallel to other events from func_rdata.
710 * If they were defined in the same union the data can get corrupted.
712 struct afex_vif_list_ramrod_data func_afex_rdata;
714 union drv_info_to_mcp drv_info_to_mcp;
715 }; /* struct bnx2x_slowpath */
718 * Port specifc data structure.
722 * Port Management Function (for 57711E only).
723 * When this field is set the driver instance is
724 * responsible for managing port specifc
725 * configurations such as handling link attentions.
729 /* Ethernet maximum transmission unit. */
732 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
734 uint32_t ext_phy_config;
736 /* Port feature config.*/
739 /* Defines the features supported by the PHY. */
740 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
742 /* Defines the features advertised by the PHY. */
743 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
744 #define ADVERTISED_10baseT_Half (1 << 1)
745 #define ADVERTISED_10baseT_Full (1 << 2)
746 #define ADVERTISED_100baseT_Half (1 << 3)
747 #define ADVERTISED_100baseT_Full (1 << 4)
748 #define ADVERTISED_1000baseT_Half (1 << 5)
749 #define ADVERTISED_1000baseT_Full (1 << 6)
750 #define ADVERTISED_TP (1 << 7)
751 #define ADVERTISED_FIBRE (1 << 8)
752 #define ADVERTISED_Autoneg (1 << 9)
753 #define ADVERTISED_Asym_Pause (1 << 10)
754 #define ADVERTISED_Pause (1 << 11)
755 #define ADVERTISED_2500baseX_Full (1 << 15)
756 #define ADVERTISED_10000baseT_Full (1 << 16)
761 * MCP scratchpad address for port specific statistics.
762 * The device is responsible for writing statistcss
763 * back to the MCP for use with management firmware such
768 struct nig_stats old_nig_stats;
769 }; /* struct bnx2x_port */
771 struct bnx2x_mf_info {
772 uint32_t mf_config[E1HVN_MAX];
774 uint32_t vnics_per_port; /* 1, 2 or 4 */
775 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
776 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
778 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
779 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
780 #define VNICS_PER_PATH(sc) \
781 ((sc)->devinfo.mf_info.vnics_per_port * \
782 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
784 uint8_t min_bw[MAX_VNIC_NUM];
785 uint8_t max_bw[MAX_VNIC_NUM];
787 uint16_t ext_id; /* vnic outer vlan or VIF ID */
788 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
789 #define INVALID_VIF_ID 0xFFFF
790 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
791 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
793 uint16_t default_vlan;
794 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
796 uint8_t niv_allowed_priorities;
797 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
799 uint8_t niv_default_cos;
800 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
802 uint8_t niv_mba_enabled;
804 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
805 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
806 int afex_def_vlan_tag;
807 uint32_t pending_max;
810 #define MF_INFO_VALID_MAC 0x0001
813 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
815 (IS_MULTI_VNIC(sc) && \
816 ((sc)->devinfo.mf_info.mf_mode != 0))
817 #define IS_MF_SD(sc) \
818 (IS_MULTI_VNIC(sc) && \
819 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
820 #define IS_MF_SI(sc) \
821 (IS_MULTI_VNIC(sc) && \
822 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
823 #define IS_MF_AFEX(sc) \
824 (IS_MULTI_VNIC(sc) && \
825 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
826 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
827 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
828 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
830 uint32_t mf_protos_supported;
831 #define MF_PROTO_SUPPORT_ETHERNET 0x1
832 #define MF_PROTO_SUPPORT_ISCSI 0x2
833 #define MF_PROTO_SUPPORT_FCOE 0x4
834 }; /* struct bnx2x_mf_info */
836 /* Device information data structure. */
837 struct bnx2x_devinfo {
841 uint16_t subvendor_id;
842 uint16_t subdevice_id;
845 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
846 * C = Chip Number (bits 16-31)
847 * R = Chip Revision (bits 12-15)
848 * M = Chip Metal (bits 4-11)
849 * B = Chip Bond ID (bits 0-3)
852 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
853 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
855 #define CHIP_NUM_57711 0x164f
856 #define CHIP_NUM_57711E 0x1650
857 #define CHIP_NUM_57712 0x1662
858 #define CHIP_NUM_57712_MF 0x1663
859 #define CHIP_NUM_57712_VF 0x166f
860 #define CHIP_NUM_57800 0x168a
861 #define CHIP_NUM_57800_MF 0x16a5
862 #define CHIP_NUM_57800_VF 0x16a9
863 #define CHIP_NUM_57810 0x168e
864 #define CHIP_NUM_57810_MF 0x16ae
865 #define CHIP_NUM_57810_VF 0x16af
866 #define CHIP_NUM_57811 0x163d
867 #define CHIP_NUM_57811_MF 0x163e
868 #define CHIP_NUM_57811_VF 0x163f
869 #define CHIP_NUM_57840_OBS 0x168d
870 #define CHIP_NUM_57840_OBS_MF 0x16ab
871 #define CHIP_NUM_57840_4_10 0x16a1
872 #define CHIP_NUM_57840_2_20 0x16a2
873 #define CHIP_NUM_57840_MF 0x16a4
874 #define CHIP_NUM_57840_VF 0x16ad
876 #define CHIP_REV_SHIFT 12
877 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
878 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
880 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
881 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
882 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
884 #define CHIP_REV_IS_SLOW(sc) \
885 (CHIP_REV(sc) > 0x00005000)
886 #define CHIP_REV_IS_FPGA(sc) \
887 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
888 #define CHIP_REV_IS_EMUL(sc) \
889 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
890 #define CHIP_REV_IS_ASIC(sc) \
891 (!CHIP_REV_IS_SLOW(sc))
893 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
894 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
896 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
897 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
898 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
899 (CHIP_IS_57711E(sc)))
900 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
902 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
903 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
904 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
905 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
906 CHIP_IS_57712_MF(sc))
908 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
909 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
910 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
911 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
912 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
913 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
914 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
915 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
916 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
917 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
918 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
919 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
920 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
921 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
922 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
924 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
925 CHIP_IS_57800_MF(sc) || \
926 CHIP_IS_57800_VF(sc) || \
927 CHIP_IS_57810(sc) || \
928 CHIP_IS_57810_MF(sc) || \
929 CHIP_IS_57810_VF(sc) || \
930 CHIP_IS_57811(sc) || \
931 CHIP_IS_57811_MF(sc) || \
932 CHIP_IS_57811_VF(sc) || \
933 CHIP_IS_57840(sc) || \
934 CHIP_IS_57840_MF(sc) || \
935 CHIP_IS_57840_VF(sc))
936 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
937 (CHIP_REV(sc) == CHIP_REV_Ax))
938 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
939 (CHIP_REV(sc) == CHIP_REV_Bx))
941 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
942 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
945 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
946 CHIP_IS_57712_MF(sc) || \
949 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
950 #define IS_PF(sc) (!IS_VF(sc))
953 * This define is used in two main places:
954 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
955 * to nic-only mode or to offload mode. Offload mode is configured if either
956 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
957 * already registered for this port (which means that the user wants storage
959 * 2. During cnic-related load, to know if offload mode is already configured
960 * in the HW or needs to be configrued. Since the transition from nic-mode to
961 * offload-mode in HW causes traffic coruption, nic-mode is configured only
962 * in ports on which storage services where never requested.
964 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
966 uint8_t chip_port_mode;
967 #define CHIP_4_PORT_MODE 0x0
968 #define CHIP_2_PORT_MODE 0x1
969 #define CHIP_PORT_MODE_NONE 0x2
970 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
971 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
974 #define INT_BLOCK_HC 0
975 #define INT_BLOCK_IGU 1
976 #define INT_BLOCK_MODE_NORMAL 0
977 #define INT_BLOCK_MODE_BW_COMP 2
978 #define CHIP_INT_MODE_IS_NBC(sc) \
979 (!CHIP_IS_E1x(sc) && \
980 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
981 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
984 uint32_t shmem2_base;
987 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
988 struct bnx2x_mf_info mf_info;
991 #define NVRAM_1MB_SIZE 0x20000
992 #define NVRAM_TIMEOUT_COUNT 30000
993 #define NVRAM_PAGE_SIZE 256
995 /* PCIe capability information */
996 uint32_t pcie_cap_flags;
997 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
998 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
999 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
1000 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
1001 uint16_t pcie_pm_cap_reg;
1002 uint16_t pcie_link_width;
1003 uint16_t pcie_link_speed;
1004 uint16_t pcie_msi_cap_reg;
1005 uint16_t pcie_msix_cap_reg;
1007 /* device configuration read from bootcode shared memory */
1009 uint32_t hw_config2;
1010 }; /* struct bnx2x_devinfo */
1012 struct bnx2x_sp_objs {
1013 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1014 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1015 }; /* struct bnx2x_sp_objs */
1018 * Data that will be used to create a link report message. We will keep the
1019 * data used for the last link report in order to prevent reporting the same
1020 * link parameters twice.
1022 struct bnx2x_link_report_data {
1023 uint16_t line_speed; /* Effective line speed */
1024 unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
1028 BNX2X_LINK_REPORT_FULL_DUPLEX,
1029 BNX2X_LINK_REPORT_LINK_DOWN,
1030 BNX2X_LINK_REPORT_RX_FC_ON,
1031 BNX2X_LINK_REPORT_TX_FC_ON
1034 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
1036 struct bnx2x_pci_cap {
1037 struct bnx2x_pci_cap *next;
1045 /* Top level device private data structure. */
1046 struct bnx2x_softc {
1050 uint32_t max_tx_queues;
1051 uint32_t max_rx_queues;
1052 const struct rte_pci_device *pci_dev;
1054 struct bnx2x_pci_cap *pci_caps;
1055 #define BNX2X_INTRS_POLL_PERIOD 1
1060 /* MAC address operations */
1061 struct bnx2x_mac_ops mac_ops;
1063 /* structures for VF mbox/response/bulletin */
1064 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1065 struct bnx2x_dma vf2pf_mbox_mapping;
1066 struct vf_acquire_resp_tlv acquire_resp;
1067 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1068 struct bnx2x_dma pf2vf_bulletin_mapping;
1069 struct bnx2x_vf_bulletin old_bulletin;
1073 int state; /* device state */
1074 #define BNX2X_STATE_CLOSED 0x0000
1075 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1076 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1077 #define BNX2X_STATE_OPEN 0x3000
1078 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1079 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1080 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1081 #define BNX2X_STATE_DISABLED 0xD000
1082 #define BNX2X_STATE_DIAG 0xE000
1083 #define BNX2X_STATE_ERROR 0xF000
1086 #define BNX2X_ONE_PORT_FLAG 0x1
1087 #define BNX2X_NO_FCOE_FLAG 0x2
1088 #define BNX2X_NO_WOL_FLAG 0x4
1089 #define BNX2X_NO_MCP_FLAG 0x8
1090 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1091 #define BNX2X_NO_ISCSI_FLAG 0x20
1092 #define BNX2X_MF_FUNC_DIS 0x40
1093 #define BNX2X_TX_SWITCHING 0x80
1094 #define BNX2X_IS_VF_FLAG 0x100
1096 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1097 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1098 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1101 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1103 uint16_t doorbell_size;
1105 /* periodic timer callout */
1106 #define PERIODIC_STOP 0
1107 #define PERIODIC_GO 1
1108 volatile unsigned long periodic_flags;
1110 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1111 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1113 uint8_t unit; /* driver instance number */
1115 int pcie_bus; /* PCIe bus number */
1116 int pcie_device; /* PCIe device/slot number */
1117 int pcie_func; /* PCIe function number */
1119 uint8_t pfunc_rel; /* function relative */
1120 uint8_t pfunc_abs; /* function absolute */
1121 uint8_t path_id; /* function absolute */
1122 #define SC_PATH(sc) (sc->path_id)
1123 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1124 #define SC_FUNC(sc) (sc->pfunc_rel)
1125 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1126 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1127 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1128 #define PORT_ID(sc) SC_PORT(sc)
1129 #define PATH_ID(sc) SC_PATH(sc)
1130 #define VNIC_ID(sc) SC_VN(sc)
1131 #define FUNC_ID(sc) SC_FUNC(sc)
1132 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1133 #define SC_FW_MB_IDX_VN(sc, vn) \
1134 (SC_PORT(sc) + (vn) * \
1135 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1136 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1138 int if_capen; /* enabled interface capabilities */
1140 struct bnx2x_devinfo devinfo;
1141 char fw_ver_str[32];
1142 char mf_mode_str[32];
1143 char pci_link_str[32];
1145 struct iro *iro_array;
1148 #define DMAE_READY(sc) (sc->dmae_ready)
1150 struct ecore_credit_pool_obj vlans_pool;
1151 struct ecore_credit_pool_obj macs_pool;
1152 struct ecore_rx_mode_obj rx_mode_obj;
1153 struct ecore_mcast_obj mcast_obj;
1154 struct ecore_rss_config_obj rss_conf_obj;
1155 struct ecore_func_sp_obj func_obj;
1158 uint16_t fw_drv_pulse_wr_seq;
1161 struct elink_params link_params;
1162 struct elink_vars link_vars;
1164 struct bnx2x_link_report_data last_reported_link;
1165 char mac_addr_str[32];
1167 uint32_t tx_ring_size;
1168 uint32_t rx_ring_size;
1173 #define BNX2X_RECOVERY_DONE 1
1174 #define BNX2X_RECOVERY_INIT 2
1175 #define BNX2X_RECOVERY_WAIT 3
1176 #define BNX2X_RECOVERY_FAILED 4
1177 #define BNX2X_RECOVERY_NIC_LOADING 5
1180 #define BNX2X_RX_MODE_NONE 0
1181 #define BNX2X_RX_MODE_NORMAL 1
1182 #define BNX2X_RX_MODE_ALLMULTI 2
1183 #define BNX2X_RX_MODE_PROMISC 3
1184 #define BNX2X_MAX_MULTICAST 64
1186 struct bnx2x_port port;
1188 struct cmng_init cmng;
1196 #define INTR_MODE_INTX 0
1197 #define INTR_MODE_MSI 1
1198 #define INTR_MODE_MSIX 2
1199 #define INTR_MODE_SINGLE_MSIX 3
1203 uint8_t igu_base_sb;
1205 uint32_t igu_base_addr;
1206 uint8_t base_fw_ndsb;
1207 #define DEF_SB_IGU_ID 16
1208 #define DEF_SB_ID HC_SP_SB_ID
1210 /* default status block */
1211 struct bnx2x_dma def_sb_dma;
1212 struct host_sp_status_block *def_sb;
1214 uint16_t def_att_idx;
1215 uint32_t attn_state;
1216 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1218 /* general SP events - stats query, cfc delete, etc */
1219 #define HC_SP_INDEX_ETH_DEF_CONS 3
1220 /* EQ completions */
1221 #define HC_SP_INDEX_EQ_CONS 7
1222 /* FCoE L2 connection completions */
1223 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1224 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1226 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1227 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1230 struct bnx2x_dma eq_dma;
1231 union event_ring_elem *eq;
1234 uint16_t *eq_cons_sb;
1235 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1236 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1237 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1238 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1239 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1240 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1241 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1242 #define NEXT_EQ_IDX(x) \
1243 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1244 ((x) + 2) : ((x) + 1))
1245 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1246 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1249 struct bnx2x_dma sp_dma;
1250 struct bnx2x_slowpath *sp;
1251 unsigned long sp_state;
1253 /* slow path queue */
1254 struct bnx2x_dma spq_dma;
1255 struct eth_spe *spq;
1256 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1257 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1258 #define MAX_SPQ_PENDING 8
1260 uint16_t spq_prod_idx;
1261 struct eth_spe *spq_prod_bd;
1262 struct eth_spe *spq_last_bd;
1263 uint16_t *dsb_sp_prod;
1265 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1266 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1268 /* fw decompression buffer */
1269 struct bnx2x_dma gz_buf_dma;
1272 #define GUNZIP_BUF(sc) (sc->gz_buf)
1273 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1274 #define GUNZIP_PHYS(sc) (phys_addr_t)((void *)(sc->gz_buf_dma.paddr))
1275 #define FW_BUF_SIZE 0x40000
1277 struct raw_op *init_ops;
1278 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1279 uint32_t *init_data; /* data blob, 32 bit granularity */
1280 uint32_t init_mode_flags;
1281 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1282 /* PRAM blobs - raw data */
1283 const uint8_t *tsem_int_table_data;
1284 const uint8_t *tsem_pram_data;
1285 const uint8_t *usem_int_table_data;
1286 const uint8_t *usem_pram_data;
1287 const uint8_t *xsem_int_table_data;
1288 const uint8_t *xsem_pram_data;
1289 const uint8_t *csem_int_table_data;
1290 const uint8_t *csem_pram_data;
1291 #define INIT_OPS(sc) (sc->init_ops)
1292 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1293 #define INIT_DATA(sc) (sc->init_data)
1294 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1295 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1296 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1297 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1298 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1299 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1300 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1301 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1303 #define PHY_FW_VER_LEN 20
1307 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1308 * context size we need 8 ILT entries.
1310 #define ILT_MAX_L2_LINES 8
1311 struct hw_context context[ILT_MAX_L2_LINES];
1312 struct ecore_ilt *ilt;
1313 #define ILT_MAX_LINES 256
1315 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1316 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1317 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1318 #define BNX2X_L2_MAX_CID(sc) \
1319 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1320 #define BNX2X_L2_CID_COUNT(sc) \
1321 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1322 #define L2_ILT_LINES(sc) \
1323 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1327 uint8_t dropless_fc;
1329 /* total number of FW statistics requests */
1330 uint8_t fw_stats_num;
1332 * This is a memory buffer that will contain both statistics ramrod
1335 struct bnx2x_dma fw_stats_dma;
1337 * FW statistics request shortcut (points at the beginning of fw_stats
1340 int fw_stats_req_size;
1341 struct bnx2x_fw_stats_req *fw_stats_req;
1342 phys_addr_t fw_stats_req_mapping;
1344 * FW statistics data shortcut (points at the beginning of fw_stats
1345 * buffer + fw_stats_req_size).
1347 int fw_stats_data_size;
1348 struct bnx2x_fw_stats_data *fw_stats_data;
1349 phys_addr_t fw_stats_data_mapping;
1351 /* tracking a pending STAT_QUERY ramrod */
1352 uint16_t stats_pending;
1353 /* number of completed statistics ramrods */
1354 uint16_t stats_comp;
1355 uint16_t stats_counter;
1359 struct bnx2x_eth_stats eth_stats;
1360 struct host_func_stats func_stats;
1361 struct bnx2x_eth_stats_old eth_stats_old;
1362 struct bnx2x_net_stats_old net_stats_old;
1363 struct bnx2x_fw_port_stats_old fw_stats_old;
1365 struct dmae_command stats_dmae; /* used by dmae command loader */
1370 /* DCB support on/off */
1372 #define BNX2X_DCB_STATE_OFF 0
1373 #define BNX2X_DCB_STATE_ON 1
1374 /* DCBX engine mode */
1376 #define BNX2X_DCBX_ENABLED_OFF 0
1377 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1378 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1379 #define BNX2X_DCBX_ENABLED_INVALID -1
1381 uint8_t cnic_support;
1382 uint8_t cnic_enabled;
1383 uint8_t cnic_loaded;
1384 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1385 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1386 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1388 /* multiple tx classes of service */
1390 #define BNX2X_MAX_PRIORITY 8
1391 /* priority to cos mapping */
1392 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1395 }; /* struct bnx2x_softc */
1397 /* IOCTL sub-commands for edebug and firmware upgrade */
1398 #define BNX2X_IOC_RD_NVRAM 1
1399 #define BNX2X_IOC_WR_NVRAM 2
1400 #define BNX2X_IOC_STATS_SHOW_NUM 3
1401 #define BNX2X_IOC_STATS_SHOW_STR 4
1402 #define BNX2X_IOC_STATS_SHOW_CNT 5
1404 struct bnx2x_nvram_data {
1405 uint32_t op; /* ioctl sub-command */
1408 uint32_t value[1]; /* variable */
1411 union bnx2x_stats_show_data {
1412 uint32_t op; /* ioctl sub-command */
1415 uint32_t num; /* return number of stats */
1416 uint32_t len; /* length of each string item */
1419 /* variable length... */
1420 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1422 /* variable length... */
1423 uint64_t stats[1]; /* holds all stats */
1426 /* function init flags */
1427 #define FUNC_FLG_RSS 0x0001
1428 #define FUNC_FLG_STATS 0x0002
1429 /* FUNC_FLG_UNMATCHED 0x0004 */
1430 #define FUNC_FLG_SPQ 0x0010
1431 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1433 struct bnx2x_func_init_params {
1434 phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1435 phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1437 uint16_t func_id; /* abs function id */
1439 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1442 /* memory resources reside at BARs 0, 2, 4 */
1443 /* Run `pciconf -lb` to see mappings */
1448 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1449 uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);
1450 uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);
1451 uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);
1453 void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val);
1454 void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val);
1455 void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);
1457 #define bnx2x_reg_write8(sc, offset, val)\
1458 *((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val
1460 #define bnx2x_reg_write16(sc, offset, val)\
1461 *((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val
1463 #define bnx2x_reg_write32(sc, offset, val)\
1464 *((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val
1466 #define bnx2x_reg_read8(sc, offset)\
1467 (*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))
1469 #define bnx2x_reg_read16(sc, offset)\
1470 (*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))
1472 #define bnx2x_reg_read32(sc, offset)\
1473 (*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))
1476 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1478 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1479 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1480 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1482 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1483 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1484 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1486 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1487 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1489 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1490 #define BNX2X_SP_MAPPING(sc, var) \
1491 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1493 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1494 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1496 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1498 #define REG_RD_DMAE(sc, offset, valp, len32) \
1500 (void)bnx2x_read_dmae(sc, offset, len32); \
1501 (void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1504 #define REG_WR_DMAE(sc, offset, valp, len32) \
1506 (void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1507 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1510 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1511 REG_WR_DMAE(sc, offset, valp, len32)
1513 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1514 REG_RD_DMAE(sc, offset, valp, len32)
1516 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1518 /* if (le32_swap) { */ \
1519 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1521 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1522 ecore_write_big_buf_wb(sc, addr, len32); \
1525 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1526 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1527 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1528 #error "Minimum DB doorbell stride is 8"
1530 #define DPM_TRIGGER_TYPE 0x40
1532 /* Doorbell macro */
1533 #define BNX2X_DB_WRITE(db_bar, val) \
1534 *((volatile uint32_t *)(db_bar)) = (val)
1536 #define BNX2X_DB_READ(db_bar) \
1537 *((volatile uint32_t *)(db_bar))
1539 #define DOORBELL_ADDR(sc, offset) \
1540 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1542 #define DOORBELL(sc, cid, val) \
1544 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1546 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1548 #define SHMEM_ADDR(sc, field) \
1549 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1550 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1551 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1552 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1554 #define SHMEM2_ADDR(sc, field) \
1555 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1556 #define SHMEM2_HAS(sc, field) \
1557 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1558 offsetof(struct shmem2_region, field)))
1559 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1560 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1562 #define MFCFG_ADDR(sc, field) \
1563 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1564 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1565 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1566 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1568 /* DMAE command defines */
1570 #define DMAE_TIMEOUT -1
1571 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1572 #define DMAE_NOT_RDY -3
1573 #define DMAE_PCI_ERR_FLAG 0x80000000
1575 #define DMAE_SRC_PCI 0
1576 #define DMAE_SRC_GRC 1
1578 #define DMAE_DST_NONE 0
1579 #define DMAE_DST_PCI 1
1580 #define DMAE_DST_GRC 2
1582 #define DMAE_COMP_PCI 0
1583 #define DMAE_COMP_GRC 1
1585 #define DMAE_COMP_REGULAR 0
1586 #define DMAE_COM_SET_ERR 1
1588 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1589 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1590 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1591 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1593 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1594 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1596 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1597 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1598 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1599 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1601 #define DMAE_CMD_PORT_0 0
1602 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1604 #define DMAE_SRC_PF 0
1605 #define DMAE_SRC_VF 1
1607 #define DMAE_DST_PF 0
1608 #define DMAE_DST_VF 1
1610 #define DMAE_C_SRC 0
1611 #define DMAE_C_DST 1
1613 #define DMAE_LEN32_RD_MAX 0x80
1614 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1616 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1618 #define MAX_DMAE_C_PER_PORT 8
1619 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1620 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1622 static const uint32_t dmae_reg_go_c[] = {
1623 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1624 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1625 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1626 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1629 #define ATTN_NIG_FOR_FUNC (1L << 8)
1630 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1631 #define GPIO_2_FUNC (1L << 10)
1632 #define GPIO_3_FUNC (1L << 11)
1633 #define GPIO_4_FUNC (1L << 12)
1634 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1635 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1636 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1637 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1638 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1639 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1640 #define ATTN_HARD_WIRED_MASK 0xff00
1641 #define ATTENTION_ID 4
1643 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1644 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1646 #define MAX_IGU_ATTN_ACK_TO 100
1648 #define STORM_ASSERT_ARRAY_SIZE 50
1650 #define BNX2X_PMF_LINK_ASSERT(sc) \
1651 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1653 #define BNX2X_MC_ASSERT_BITS \
1654 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1655 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1656 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1657 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1659 #define BNX2X_MCP_ASSERT \
1660 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1662 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1663 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1664 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1665 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1666 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1667 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1668 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1670 #define MULTI_MASK 0x7f
1672 #define PFS_PER_PORT(sc) \
1673 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1674 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1676 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1677 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1678 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1680 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1681 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1682 (i) < MAX_FUNC_NUM; \
1683 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1685 #define BNX2X_SWCID_SHIFT 17
1686 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1688 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1689 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1691 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1692 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1693 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1694 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1695 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1697 /* must be used on a CID before placing it on a HW ring */
1698 #define HW_CID(sc, x) \
1699 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1702 #define SPEED_100 100
1703 #define SPEED_1000 1000
1704 #define SPEED_2500 2500
1705 #define SPEED_10000 10000
1708 #define PCI_PM_D3hot 2
1710 int bnx2x_test_bit(int nr, volatile unsigned long * addr);
1711 void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
1712 void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
1713 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
1714 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1716 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1717 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1719 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1720 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1721 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1722 uint8_t dst_type, uint8_t with_comp,
1724 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1725 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1726 void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,
1727 uint32_t dst_addr, uint32_t len32);
1728 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1730 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1731 uint8_t sb_index, uint8_t disable,
1734 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1735 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1737 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1738 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1740 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1741 size_t size, uint32_t *data);
1743 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1744 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1746 #define BNX2X_MAC_FMT "%pM"
1747 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1753 static inline uint32_t
1754 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1758 val = REG_RD(sc, reg);
1759 if (val == expected) {
1770 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1772 mb(); /* status block is written to by the chip */
1773 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1777 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1778 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1780 struct igu_regular cmd_data = {0};
1782 cmd_data.sb_id_and_flags =
1783 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1784 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1785 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1786 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1788 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1790 /* Make sure that ACK is written */
1795 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1796 uint16_t index, uint8_t op, uint8_t update)
1798 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1799 COMMAND_REG_INT_ACK);
1800 union igu_ack_register igu_ack;
1802 igu_ack.sb.status_block_index = index;
1803 igu_ack.sb.sb_id_and_flags =
1804 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1805 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1806 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1807 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1809 REG_WR(sc, hc_addr, igu_ack.raw_data);
1811 /* Make sure that ACK is written */
1815 static inline uint32_t
1816 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1818 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1819 COMMAND_REG_SIMD_MASK);
1820 uint32_t result = REG_RD(sc, hc_addr);
1826 static inline uint32_t
1827 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1829 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1830 uint32_t result = REG_RD(sc, igu_addr);
1832 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1833 result, igu_addr); */
1839 static inline uint32_t
1840 bnx2x_ack_int(struct bnx2x_softc *sc)
1843 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1844 return bnx2x_hc_ack_int(sc);
1846 return bnx2x_igu_ack_int(sc);
1851 func_by_vn(struct bnx2x_softc *sc, int vn)
1853 return (2 * vn + SC_PORT(sc));
1857 * send notification to other functions.
1860 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1864 /* Set the attention towards other drivers on the same port */
1865 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1866 if (vn == SC_VN(sc))
1869 func = func_by_vn(sc, vn);
1870 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1871 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1876 * Statistics ID are global per chip/path, while Client IDs for E1x
1879 static inline uint8_t
1880 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1882 struct bnx2x_softc *sc = fp->sc;
1884 if (!CHIP_IS_E1x(sc)) {
1888 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
1891 int bnx2x_init(struct bnx2x_softc *sc);
1892 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1893 int bnx2x_attach(struct bnx2x_softc *sc);
1894 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1895 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
1896 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
1897 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
1898 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
1899 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts);
1900 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
1901 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
1902 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp);
1903 void bnx2x_link_status_update(struct bnx2x_softc *sc);
1904 int bnx2x_complete_sp(struct bnx2x_softc *sc);
1905 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
1906 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
1908 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
1909 void bnx2x_vf_close(struct bnx2x_softc *sc);
1910 int bnx2x_vf_init(struct bnx2x_softc *sc);
1911 void bnx2x_vf_unload(struct bnx2x_softc *sc);
1912 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1914 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
1915 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
1916 int bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1917 unsigned long *rx_accept_flags, unsigned long *tx_accept_flags);
1918 int bnx2x_check_bull(struct bnx2x_softc *sc);
1920 //#define BNX2X_PULSE
1922 #define BNX2X_PCI_CAP 1
1923 #define BNX2X_PCI_ECAP 2
1925 static inline struct bnx2x_pci_cap*
1926 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
1928 struct bnx2x_pci_cap *cap = sc->pci_caps;
1931 if (cap->id == id && cap->type == type)
1939 static inline int is_valid_ether_addr(uint8_t *addr)
1941 if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
1948 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
1950 if (sc->state == BNX2X_STATE_OPEN) {
1952 bnx2x_set_storm_rx_mode(sc);
1954 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
1955 bnx2x_vf_set_rx_mode(sc);
1958 PMD_DRV_LOG(NOTICE, "Card is not ready to change mode");
1962 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
1963 void *val, uint8_t size)
1965 if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
1966 PMD_DRV_LOG(ERR, "Can't read from PCI config space");
1973 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
1975 uint16_t val16 = val;
1977 if (rte_eal_pci_write_config(sc->pci_dev, &val16,
1978 sizeof(val16), addr) <= 0) {
1979 PMD_DRV_LOG(ERR, "Can't write to PCI config space");
1986 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
1988 uint32_t val32 = val;
1989 if (rte_eal_pci_write_config(sc->pci_dev, &val32,
1990 sizeof(val32), addr) <= 0) {
1991 PMD_DRV_LOG(ERR, "Can't write to PCI config space");
1998 #endif /* __BNX2X_H__ */