1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include "hsi_struct_def_dpdk.h"
10 #define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
11 ((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
12 RX_TPA_START_CMPL_AGG_ID_SFT)
14 #define BNXT_TPA_START_AGG_ID_TH(cmp) \
15 rte_le_to_cpu_16((cmp)->agg_id)
17 static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
18 struct rx_tpa_start_cmpl *cmp)
20 if (BNXT_CHIP_THOR(bp))
21 return BNXT_TPA_START_AGG_ID_TH(cmp);
23 return BNXT_TPA_START_AGG_ID_PRE_TH(cmp);
26 #define BNXT_TPA_END_AGG_BUFS(cmp) \
27 (((cmp)->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) \
28 >> RX_TPA_END_CMPL_AGG_BUFS_SFT)
30 #define BNXT_TPA_END_AGG_BUFS_TH(cmp) \
33 #define BNXT_TPA_END_AGG_ID(cmp) \
34 (((cmp)->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> \
35 RX_TPA_END_CMPL_AGG_ID_SFT)
37 #define BNXT_TPA_END_AGG_ID_TH(cmp) \
38 rte_le_to_cpu_16((cmp)->agg_id)
40 #define BNXT_RX_POST_THRESH 32
42 /* Number of descriptors to process per inner loop in vector mode. */
43 #define RTE_BNXT_DESCS_PER_LOOP 4U
45 struct bnxt_tpa_info {
46 struct rte_mbuf *mbuf;
49 struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
52 struct bnxt_rx_ring_info {
55 uint16_t rx_cons; /* Needed for representor */
56 struct bnxt_db_info rx_db;
57 struct bnxt_db_info ag_db;
59 struct rx_prod_pkt_bd *rx_desc_ring;
60 struct rx_prod_pkt_bd *ag_desc_ring;
61 struct rte_mbuf **rx_buf_ring; /* sw ring */
62 struct rte_mbuf **ag_buf_ring; /* sw ring */
64 rte_iova_t rx_desc_mapping;
65 rte_iova_t ag_desc_mapping;
67 struct bnxt_ring *rx_ring_struct;
68 struct bnxt_ring *ag_ring_struct;
71 * To deal with out of order return from TPA, use free buffer indicator
73 struct rte_bitmap *ag_bitmap;
75 struct bnxt_tpa_info *tpa_info;
78 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 uint16_t bnxt_dummy_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
82 void bnxt_free_rx_rings(struct bnxt *bp);
83 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
84 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
85 int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
86 int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
88 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
89 uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
91 int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
94 void bnxt_set_mark_in_mbuf(struct bnxt *bp,
95 struct rx_pkt_cmpl_hi *rxcmp1,
96 struct rte_mbuf *mbuf);
98 typedef uint32_t bnxt_cfa_code_dynfield_t;
99 extern int bnxt_cfa_code_dynfield_offset;
101 static inline bnxt_cfa_code_dynfield_t *
102 bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)
104 return RTE_MBUF_DYNFIELD(mbuf,
105 bnxt_cfa_code_dynfield_offset, bnxt_cfa_code_dynfield_t *);
108 #define BNXT_RX_META_CFA_CODE_SHIFT 19
109 #define BNXT_CFA_CODE_META_SHIFT 16
110 #define BNXT_RX_META_CFA_CODE_INT_ACT_REC_BIT 0x8000000
111 #define BNXT_RX_META_CFA_CODE_EEM_BIT 0x4000000
112 #define BNXT_CFA_META_FMT_MASK 0x70
113 #define BNXT_CFA_META_FMT_SHFT 4
114 #define BNXT_CFA_META_FMT_EM_EEM_SHFT 1
115 #define BNXT_CFA_META_FMT_EEM 3
116 #define BNXT_CFA_META_EEM_TCAM_SHIFT 31
117 #define BNXT_CFA_META_EM_TEST(x) ((x) >> BNXT_CFA_META_EEM_TCAM_SHIFT)
119 #define BNXT_PTYPE_TBL_DIM 128
120 extern uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM];
122 #define BNXT_OL_FLAGS_TBL_DIM 32
123 extern uint32_t bnxt_ol_flags_table[BNXT_OL_FLAGS_TBL_DIM];
125 #define BNXT_OL_FLAGS_ERR_TBL_DIM 16
126 extern uint32_t bnxt_ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM];