1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
103 static const char *const bnxt_dev_args[] = {
104 BNXT_DEVARG_REPRESENTOR,
106 BNXT_DEVARG_FLOW_XSTAT,
107 BNXT_DEVARG_MAX_NUM_KFLOWS,
112 * truflow == false to disable the feature
113 * truflow == true to enable the feature
115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
118 * flow_xstat == false to disable the feature
119 * flow_xstat == true to enable the feature
121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
124 * max_num_kflows must be >= 32
125 * and must be a power-of-2 supported value
126 * return: 1 -> invalid
129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
142 static void bnxt_dev_recover(void *arg);
143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
144 static void bnxt_free_rep_info(struct bnxt *bp);
146 int is_bnxt_in_error(struct bnxt *bp)
148 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
150 if (bp->flags & BNXT_FLAG_FW_RESET)
156 /***********************/
159 * High level utility functions
162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
168 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
169 BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
174 if (!BNXT_CHIP_THOR(bp))
175 return HW_HASH_INDEX_SIZE;
177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
180 static void bnxt_free_parent_info(struct bnxt *bp)
182 rte_free(bp->parent);
185 static void bnxt_free_pf_info(struct bnxt *bp)
190 static void bnxt_free_link_info(struct bnxt *bp)
192 rte_free(bp->link_info);
195 static void bnxt_free_leds_info(struct bnxt *bp)
204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
206 rte_free(bp->flow_stat);
207 bp->flow_stat = NULL;
210 static void bnxt_free_cos_queues(struct bnxt *bp)
212 rte_free(bp->rx_cos_queue);
213 rte_free(bp->tx_cos_queue);
216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
218 bnxt_free_filter_mem(bp);
219 bnxt_free_vnic_attributes(bp);
220 bnxt_free_vnic_mem(bp);
222 /* tx/rx rings are configured as part of *_queue_setup callbacks.
223 * If the number of rings change across fw update,
224 * we don't have much choice except to warn the user.
228 bnxt_free_tx_rings(bp);
229 bnxt_free_rx_rings(bp);
231 bnxt_free_async_cp_ring(bp);
232 bnxt_free_rxtx_nq_ring(bp);
234 rte_free(bp->grp_info);
238 static int bnxt_alloc_parent_info(struct bnxt *bp)
240 bp->parent = rte_zmalloc("bnxt_parent_info",
241 sizeof(struct bnxt_parent_info), 0);
242 if (bp->parent == NULL)
248 static int bnxt_alloc_pf_info(struct bnxt *bp)
250 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
257 static int bnxt_alloc_link_info(struct bnxt *bp)
260 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
261 if (bp->link_info == NULL)
267 static int bnxt_alloc_leds_info(struct bnxt *bp)
272 bp->leds = rte_zmalloc("bnxt_leds",
273 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
275 if (bp->leds == NULL)
281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
284 rte_zmalloc("bnxt_rx_cosq",
285 BNXT_COS_QUEUE_COUNT *
286 sizeof(struct bnxt_cos_queue_info),
288 if (bp->rx_cos_queue == NULL)
292 rte_zmalloc("bnxt_tx_cosq",
293 BNXT_COS_QUEUE_COUNT *
294 sizeof(struct bnxt_cos_queue_info),
296 if (bp->tx_cos_queue == NULL)
302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
304 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
305 sizeof(struct bnxt_flow_stat_info), 0);
306 if (bp->flow_stat == NULL)
312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
316 rc = bnxt_alloc_ring_grps(bp);
320 rc = bnxt_alloc_async_ring_struct(bp);
324 rc = bnxt_alloc_vnic_mem(bp);
328 rc = bnxt_alloc_vnic_attributes(bp);
332 rc = bnxt_alloc_filter_mem(bp);
336 rc = bnxt_alloc_async_cp_ring(bp);
340 rc = bnxt_alloc_rxtx_nq_ring(bp);
344 if (BNXT_FLOW_XSTATS_EN(bp)) {
345 rc = bnxt_alloc_flow_stats_info(bp);
353 bnxt_free_mem(bp, reconfig);
357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
361 uint64_t rx_offloads = dev_conf->rxmode.offloads;
362 struct bnxt_rx_queue *rxq;
366 rc = bnxt_vnic_grp_alloc(bp, vnic);
370 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
371 vnic_id, vnic, vnic->fw_grp_ids);
373 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
377 /* Alloc RSS context only if RSS mode is enabled */
378 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
379 int j, nr_ctxs = bnxt_rss_ctxts(bp);
382 for (j = 0; j < nr_ctxs; j++) {
383 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
389 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
393 vnic->num_lb_ctxts = nr_ctxs;
397 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
398 * setting is not available at this time, it will not be
399 * configured correctly in the CFA.
401 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
402 vnic->vlan_strip = true;
404 vnic->vlan_strip = false;
406 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
410 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
414 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
415 rxq = bp->eth_dev->data->rx_queues[j];
418 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
419 j, rxq->vnic, rxq->vnic->fw_grp_ids);
421 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
422 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
424 vnic->rx_queue_cnt++;
427 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
429 rc = bnxt_vnic_rss_configure(bp, vnic);
433 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
435 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
436 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
438 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
442 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
451 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
452 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
457 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
458 " rx_fc_in_tbl.ctx_id = %d\n",
459 bp->flow_stat->rx_fc_in_tbl.va,
460 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
461 bp->flow_stat->rx_fc_in_tbl.ctx_id);
463 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
464 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
469 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
470 " rx_fc_out_tbl.ctx_id = %d\n",
471 bp->flow_stat->rx_fc_out_tbl.va,
472 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
473 bp->flow_stat->rx_fc_out_tbl.ctx_id);
475 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
476 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
481 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
482 " tx_fc_in_tbl.ctx_id = %d\n",
483 bp->flow_stat->tx_fc_in_tbl.va,
484 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
485 bp->flow_stat->tx_fc_in_tbl.ctx_id);
487 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
488 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
493 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
494 " tx_fc_out_tbl.ctx_id = %d\n",
495 bp->flow_stat->tx_fc_out_tbl.va,
496 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
497 bp->flow_stat->tx_fc_out_tbl.ctx_id);
499 memset(bp->flow_stat->rx_fc_out_tbl.va,
501 bp->flow_stat->rx_fc_out_tbl.size);
502 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
503 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
504 bp->flow_stat->rx_fc_out_tbl.ctx_id,
505 bp->flow_stat->max_fc,
510 memset(bp->flow_stat->tx_fc_out_tbl.va,
512 bp->flow_stat->tx_fc_out_tbl.size);
513 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
514 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
515 bp->flow_stat->tx_fc_out_tbl.ctx_id,
516 bp->flow_stat->max_fc,
522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
523 struct bnxt_ctx_mem_buf_info *ctx)
528 ctx->va = rte_zmalloc(type, size, 0);
531 rte_mem_lock_page(ctx->va);
533 ctx->dma = rte_mem_virt2iova(ctx->va);
534 if (ctx->dma == RTE_BAD_IOVA)
540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
542 struct rte_pci_device *pdev = bp->pdev;
543 char type[RTE_MEMZONE_NAMESIZE];
547 max_fc = bp->flow_stat->max_fc;
549 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 /* 4 bytes for each counter-id */
552 rc = bnxt_alloc_ctx_mem_buf(type,
554 &bp->flow_stat->rx_fc_in_tbl);
558 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
560 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
561 rc = bnxt_alloc_ctx_mem_buf(type,
563 &bp->flow_stat->rx_fc_out_tbl);
567 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
569 /* 4 bytes for each counter-id */
570 rc = bnxt_alloc_ctx_mem_buf(type,
572 &bp->flow_stat->tx_fc_in_tbl);
576 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
578 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
579 rc = bnxt_alloc_ctx_mem_buf(type,
581 &bp->flow_stat->tx_fc_out_tbl);
585 rc = bnxt_register_fc_ctx_mem(bp);
590 static int bnxt_init_ctx_mem(struct bnxt *bp)
594 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
595 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
596 !BNXT_FLOW_XSTATS_EN(bp))
599 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
603 rc = bnxt_init_fc_ctx_mem(bp);
608 static int bnxt_init_chip(struct bnxt *bp)
610 struct rte_eth_link new;
611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
612 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
613 uint32_t intr_vector = 0;
614 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
615 uint32_t vec = BNXT_MISC_VEC_ID;
619 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
620 bp->eth_dev->data->dev_conf.rxmode.offloads |=
621 DEV_RX_OFFLOAD_JUMBO_FRAME;
622 bp->flags |= BNXT_FLAG_JUMBO;
624 bp->eth_dev->data->dev_conf.rxmode.offloads &=
625 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
626 bp->flags &= ~BNXT_FLAG_JUMBO;
629 /* THOR does not support ring groups.
630 * But we will use the array to save RSS context IDs.
632 if (BNXT_CHIP_THOR(bp))
633 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
635 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
637 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
641 rc = bnxt_alloc_hwrm_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
647 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
649 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
653 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
656 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
657 if (bp->rx_cos_queue[i].id != 0xff) {
658 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
662 "Num pools more than FW profile\n");
666 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
672 rc = bnxt_mq_rx_configure(bp);
674 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
678 /* VNIC configuration */
679 for (i = 0; i < bp->nr_vnics; i++) {
680 rc = bnxt_setup_one_vnic(bp, i);
685 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
688 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
692 /* check and configure queue intr-vector mapping */
693 if ((rte_intr_cap_multiple(intr_handle) ||
694 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
695 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
696 intr_vector = bp->eth_dev->data->nb_rx_queues;
697 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
698 if (intr_vector > bp->rx_cp_nr_rings) {
699 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
703 rc = rte_intr_efd_enable(intr_handle, intr_vector);
708 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
709 intr_handle->intr_vec =
710 rte_zmalloc("intr_vec",
711 bp->eth_dev->data->nb_rx_queues *
713 if (intr_handle->intr_vec == NULL) {
714 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
715 " intr_vec", bp->eth_dev->data->nb_rx_queues);
719 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
720 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
721 intr_handle->intr_vec, intr_handle->nb_efd,
722 intr_handle->max_intr);
723 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
725 intr_handle->intr_vec[queue_id] =
726 vec + BNXT_RX_VEC_START;
727 if (vec < base + intr_handle->nb_efd - 1)
732 /* enable uio/vfio intr/eventfd mapping */
733 rc = rte_intr_enable(intr_handle);
734 #ifndef RTE_EXEC_ENV_FREEBSD
735 /* In FreeBSD OS, nic_uio driver does not support interrupts */
740 rc = bnxt_get_hwrm_link_config(bp, &new);
742 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
746 if (!bp->link_info->link_up) {
747 rc = bnxt_set_hwrm_link_config(bp, true);
750 "HWRM link config failure rc: %x\n", rc);
754 bnxt_print_link_info(bp->eth_dev);
756 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
758 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
763 rte_free(intr_handle->intr_vec);
765 rte_intr_efd_disable(intr_handle);
767 /* Some of the error status returned by FW may not be from errno.h */
774 static int bnxt_shutdown_nic(struct bnxt *bp)
776 bnxt_free_all_hwrm_resources(bp);
777 bnxt_free_all_filters(bp);
778 bnxt_free_all_vnics(bp);
783 * Device configuration and status function
786 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
788 uint32_t link_speed = bp->link_info->support_speeds;
789 uint32_t speed_capa = 0;
791 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
792 speed_capa |= ETH_LINK_SPEED_100M;
793 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
794 speed_capa |= ETH_LINK_SPEED_100M_HD;
795 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
796 speed_capa |= ETH_LINK_SPEED_1G;
797 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
798 speed_capa |= ETH_LINK_SPEED_2_5G;
799 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
800 speed_capa |= ETH_LINK_SPEED_10G;
801 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
802 speed_capa |= ETH_LINK_SPEED_20G;
803 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
804 speed_capa |= ETH_LINK_SPEED_25G;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
806 speed_capa |= ETH_LINK_SPEED_40G;
807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
808 speed_capa |= ETH_LINK_SPEED_50G;
809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
810 speed_capa |= ETH_LINK_SPEED_100G;
811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
812 speed_capa |= ETH_LINK_SPEED_200G;
814 if (bp->link_info->auto_mode ==
815 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
816 speed_capa |= ETH_LINK_SPEED_FIXED;
818 speed_capa |= ETH_LINK_SPEED_AUTONEG;
823 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
824 struct rte_eth_dev_info *dev_info)
826 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
827 struct bnxt *bp = eth_dev->data->dev_private;
828 uint16_t max_vnics, i, j, vpool, vrxq;
829 unsigned int max_rx_rings;
832 rc = is_bnxt_in_error(bp);
837 dev_info->max_mac_addrs = bp->max_l2_ctx;
838 dev_info->max_hash_mac_addrs = 0;
840 /* PF/VF specifics */
842 dev_info->max_vfs = pdev->max_vfs;
844 max_rx_rings = BNXT_MAX_RINGS(bp);
845 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
846 dev_info->max_rx_queues = max_rx_rings;
847 dev_info->max_tx_queues = max_rx_rings;
848 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
849 dev_info->hash_key_size = 40;
850 max_vnics = bp->max_vnics;
853 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
854 dev_info->max_mtu = BNXT_MAX_MTU;
856 /* Fast path specifics */
857 dev_info->min_rx_bufsize = 1;
858 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
860 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
861 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
862 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
863 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
864 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
866 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
869 dev_info->default_rxconf = (struct rte_eth_rxconf) {
875 .rx_free_thresh = 32,
876 /* If no descriptors available, pkts are dropped by default */
880 dev_info->default_txconf = (struct rte_eth_txconf) {
886 .tx_free_thresh = 32,
889 eth_dev->data->dev_conf.intr_conf.lsc = 1;
891 eth_dev->data->dev_conf.intr_conf.rxq = 1;
892 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
893 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
894 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
895 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
900 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
901 * need further investigation.
905 vpool = 64; /* ETH_64_POOLS */
906 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
907 for (i = 0; i < 4; vpool >>= 1, i++) {
908 if (max_vnics > vpool) {
909 for (j = 0; j < 5; vrxq >>= 1, j++) {
910 if (dev_info->max_rx_queues > vrxq) {
916 /* Not enough resources to support VMDq */
920 /* Not enough resources to support VMDq */
924 dev_info->max_vmdq_pools = vpool;
925 dev_info->vmdq_queue_num = vrxq;
927 dev_info->vmdq_pool_base = 0;
928 dev_info->vmdq_queue_base = 0;
933 /* Configure the device based on the configuration provided */
934 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
936 struct bnxt *bp = eth_dev->data->dev_private;
937 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
940 bp->rx_queues = (void *)eth_dev->data->rx_queues;
941 bp->tx_queues = (void *)eth_dev->data->tx_queues;
942 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
943 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
945 rc = is_bnxt_in_error(bp);
949 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
950 rc = bnxt_hwrm_check_vf_rings(bp);
952 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
956 /* If a resource has already been allocated - in this case
957 * it is the async completion ring, free it. Reallocate it after
958 * resource reservation. This will ensure the resource counts
959 * are calculated correctly.
962 pthread_mutex_lock(&bp->def_cp_lock);
964 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
965 bnxt_disable_int(bp);
966 bnxt_free_cp_ring(bp, bp->async_cp_ring);
969 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
971 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
972 pthread_mutex_unlock(&bp->def_cp_lock);
976 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
977 rc = bnxt_alloc_async_cp_ring(bp);
979 pthread_mutex_unlock(&bp->def_cp_lock);
985 pthread_mutex_unlock(&bp->def_cp_lock);
987 /* legacy driver needs to get updated values */
988 rc = bnxt_hwrm_func_qcaps(bp);
990 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
995 /* Inherit new configurations */
996 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
997 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
998 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
999 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1000 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1002 goto resource_error;
1004 if (BNXT_HAS_RING_GRPS(bp) &&
1005 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1006 goto resource_error;
1008 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1009 bp->max_vnics < eth_dev->data->nb_rx_queues)
1010 goto resource_error;
1012 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1013 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1015 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1016 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1017 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1019 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1020 eth_dev->data->mtu =
1021 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1022 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1024 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1030 "Insufficient resources to support requested config\n");
1032 "Num Queues Requested: Tx %d, Rx %d\n",
1033 eth_dev->data->nb_tx_queues,
1034 eth_dev->data->nb_rx_queues);
1036 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1037 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1038 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1042 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1044 struct rte_eth_link *link = ð_dev->data->dev_link;
1046 if (link->link_status)
1047 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1048 eth_dev->data->port_id,
1049 (uint32_t)link->link_speed,
1050 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1051 ("full-duplex") : ("half-duplex\n"));
1053 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1054 eth_dev->data->port_id);
1058 * Determine whether the current configuration requires support for scattered
1059 * receive; return 1 if scattered receive is required and 0 if not.
1061 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1066 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1069 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1070 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1072 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1073 RTE_PKTMBUF_HEADROOM);
1074 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1080 static eth_rx_burst_t
1081 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1083 struct bnxt *bp = eth_dev->data->dev_private;
1085 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1086 #ifndef RTE_LIBRTE_IEEE1588
1088 * Vector mode receive can be enabled only if scatter rx is not
1089 * in use and rx offloads are limited to VLAN stripping and
1092 if (!eth_dev->data->scattered_rx &&
1093 !(eth_dev->data->dev_conf.rxmode.offloads &
1094 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1095 DEV_RX_OFFLOAD_KEEP_CRC |
1096 DEV_RX_OFFLOAD_JUMBO_FRAME |
1097 DEV_RX_OFFLOAD_IPV4_CKSUM |
1098 DEV_RX_OFFLOAD_UDP_CKSUM |
1099 DEV_RX_OFFLOAD_TCP_CKSUM |
1100 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1101 DEV_RX_OFFLOAD_RSS_HASH |
1102 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1103 !BNXT_TRUFLOW_EN(bp)) {
1104 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1105 eth_dev->data->port_id);
1106 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1107 return bnxt_recv_pkts_vec;
1109 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1110 eth_dev->data->port_id);
1112 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1113 eth_dev->data->port_id,
1114 eth_dev->data->scattered_rx,
1115 eth_dev->data->dev_conf.rxmode.offloads);
1118 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1119 return bnxt_recv_pkts;
1122 static eth_tx_burst_t
1123 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1125 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1126 #ifndef RTE_LIBRTE_IEEE1588
1127 struct bnxt *bp = eth_dev->data->dev_private;
1130 * Vector mode transmit can be enabled only if not using scatter rx
1133 if (!eth_dev->data->scattered_rx &&
1134 !eth_dev->data->dev_conf.txmode.offloads &&
1135 !BNXT_TRUFLOW_EN(bp)) {
1136 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1137 eth_dev->data->port_id);
1138 return bnxt_xmit_pkts_vec;
1140 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1141 eth_dev->data->port_id);
1143 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1144 eth_dev->data->port_id,
1145 eth_dev->data->scattered_rx,
1146 eth_dev->data->dev_conf.txmode.offloads);
1149 return bnxt_xmit_pkts;
1152 static int bnxt_handle_if_change_status(struct bnxt *bp)
1156 /* Since fw has undergone a reset and lost all contexts,
1157 * set fatal flag to not issue hwrm during cleanup
1159 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1160 bnxt_uninit_resources(bp, true);
1162 /* clear fatal flag so that re-init happens */
1163 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1164 rc = bnxt_init_resources(bp, true);
1166 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1171 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1173 struct bnxt *bp = eth_dev->data->dev_private;
1174 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1176 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1178 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1179 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1183 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1185 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1186 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1190 rc = bnxt_hwrm_if_change(bp, true);
1191 if (rc == 0 || rc != -EAGAIN)
1194 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1195 } while (retry_cnt--);
1200 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1201 rc = bnxt_handle_if_change_status(bp);
1206 bnxt_enable_int(bp);
1208 rc = bnxt_init_chip(bp);
1212 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1213 eth_dev->data->dev_started = 1;
1215 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1217 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1218 vlan_mask |= ETH_VLAN_FILTER_MASK;
1219 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1220 vlan_mask |= ETH_VLAN_STRIP_MASK;
1221 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1225 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1226 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1228 pthread_mutex_lock(&bp->def_cp_lock);
1229 bnxt_schedule_fw_health_check(bp);
1230 pthread_mutex_unlock(&bp->def_cp_lock);
1237 bnxt_shutdown_nic(bp);
1238 bnxt_free_tx_mbufs(bp);
1239 bnxt_free_rx_mbufs(bp);
1240 bnxt_hwrm_if_change(bp, false);
1241 eth_dev->data->dev_started = 0;
1245 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1247 struct bnxt *bp = eth_dev->data->dev_private;
1250 if (!bp->link_info->link_up)
1251 rc = bnxt_set_hwrm_link_config(bp, true);
1253 eth_dev->data->dev_link.link_status = 1;
1255 bnxt_print_link_info(eth_dev);
1259 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1261 struct bnxt *bp = eth_dev->data->dev_private;
1263 eth_dev->data->dev_link.link_status = 0;
1264 bnxt_set_hwrm_link_config(bp, false);
1265 bp->link_info->link_up = 0;
1270 static void bnxt_free_switch_domain(struct bnxt *bp)
1272 if (bp->switch_domain_id)
1273 rte_eth_switch_domain_free(bp->switch_domain_id);
1276 /* Unload the driver, release resources */
1277 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1279 struct bnxt *bp = eth_dev->data->dev_private;
1280 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1281 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1283 eth_dev->data->dev_started = 0;
1284 /* Prevent crashes when queues are still in use */
1285 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1286 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1288 bnxt_disable_int(bp);
1290 /* disable uio/vfio intr/eventfd mapping */
1291 rte_intr_disable(intr_handle);
1293 bnxt_ulp_destroy_df_rules(bp, false);
1294 bnxt_ulp_deinit(bp);
1296 bnxt_cancel_fw_health_check(bp);
1298 bnxt_dev_set_link_down_op(eth_dev);
1300 /* Wait for link to be reset and the async notification to process.
1301 * During reset recovery, there is no need to wait and
1302 * VF/NPAR functions do not have privilege to change PHY config.
1304 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1305 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1307 /* Clean queue intr-vector mapping */
1308 rte_intr_efd_disable(intr_handle);
1309 if (intr_handle->intr_vec != NULL) {
1310 rte_free(intr_handle->intr_vec);
1311 intr_handle->intr_vec = NULL;
1314 bnxt_hwrm_port_clr_stats(bp);
1315 bnxt_free_tx_mbufs(bp);
1316 bnxt_free_rx_mbufs(bp);
1317 /* Process any remaining notifications in default completion queue */
1318 bnxt_int_handler(eth_dev);
1319 bnxt_shutdown_nic(bp);
1320 bnxt_hwrm_if_change(bp, false);
1322 rte_free(bp->mark_table);
1323 bp->mark_table = NULL;
1325 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1326 bp->rx_cosq_cnt = 0;
1327 /* All filters are deleted on a port stop. */
1328 if (BNXT_FLOW_XSTATS_EN(bp))
1329 bp->flow_stat->flow_count = 0;
1332 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1334 struct bnxt *bp = eth_dev->data->dev_private;
1336 /* cancel the recovery handler before remove dev */
1337 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1338 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1339 bnxt_cancel_fc_thread(bp);
1341 if (eth_dev->data->dev_started)
1342 bnxt_dev_stop_op(eth_dev);
1344 bnxt_free_switch_domain(bp);
1346 bnxt_uninit_resources(bp, false);
1348 bnxt_free_leds_info(bp);
1349 bnxt_free_cos_queues(bp);
1350 bnxt_free_link_info(bp);
1351 bnxt_free_pf_info(bp);
1352 bnxt_free_parent_info(bp);
1354 eth_dev->dev_ops = NULL;
1355 eth_dev->rx_pkt_burst = NULL;
1356 eth_dev->tx_pkt_burst = NULL;
1358 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1359 bp->tx_mem_zone = NULL;
1360 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1361 bp->rx_mem_zone = NULL;
1363 rte_free(bp->pf->vf_info);
1364 bp->pf->vf_info = NULL;
1366 rte_free(bp->grp_info);
1367 bp->grp_info = NULL;
1370 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1373 struct bnxt *bp = eth_dev->data->dev_private;
1374 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1375 struct bnxt_vnic_info *vnic;
1376 struct bnxt_filter_info *filter, *temp_filter;
1379 if (is_bnxt_in_error(bp))
1383 * Loop through all VNICs from the specified filter flow pools to
1384 * remove the corresponding MAC addr filter
1386 for (i = 0; i < bp->nr_vnics; i++) {
1387 if (!(pool_mask & (1ULL << i)))
1390 vnic = &bp->vnic_info[i];
1391 filter = STAILQ_FIRST(&vnic->filter);
1393 temp_filter = STAILQ_NEXT(filter, next);
1394 if (filter->mac_index == index) {
1395 STAILQ_REMOVE(&vnic->filter, filter,
1396 bnxt_filter_info, next);
1397 bnxt_hwrm_clear_l2_filter(bp, filter);
1398 bnxt_free_filter(bp, filter);
1400 filter = temp_filter;
1405 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1406 struct rte_ether_addr *mac_addr, uint32_t index,
1409 struct bnxt_filter_info *filter;
1412 /* Attach requested MAC address to the new l2_filter */
1413 STAILQ_FOREACH(filter, &vnic->filter, next) {
1414 if (filter->mac_index == index) {
1416 "MAC addr already existed for pool %d\n",
1422 filter = bnxt_alloc_filter(bp);
1424 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1428 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1429 * if the MAC that's been programmed now is a different one, then,
1430 * copy that addr to filter->l2_addr
1433 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1434 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1436 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1438 filter->mac_index = index;
1439 if (filter->mac_index == 0)
1440 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1442 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1444 bnxt_free_filter(bp, filter);
1450 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1451 struct rte_ether_addr *mac_addr,
1452 uint32_t index, uint32_t pool)
1454 struct bnxt *bp = eth_dev->data->dev_private;
1455 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1458 rc = is_bnxt_in_error(bp);
1462 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1463 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1468 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1472 /* Filter settings will get applied when port is started */
1473 if (!eth_dev->data->dev_started)
1476 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1481 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1482 bool exp_link_status)
1485 struct bnxt *bp = eth_dev->data->dev_private;
1486 struct rte_eth_link new;
1487 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1488 BNXT_LINK_DOWN_WAIT_CNT;
1490 rc = is_bnxt_in_error(bp);
1494 memset(&new, 0, sizeof(new));
1496 /* Retrieve link info from hardware */
1497 rc = bnxt_get_hwrm_link_config(bp, &new);
1499 new.link_speed = ETH_LINK_SPEED_100M;
1500 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1502 "Failed to retrieve link rc = 0x%x!\n", rc);
1506 if (!wait_to_complete || new.link_status == exp_link_status)
1509 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1513 /* Timed out or success */
1514 if (new.link_status != eth_dev->data->dev_link.link_status ||
1515 new.link_speed != eth_dev->data->dev_link.link_speed) {
1516 rte_eth_linkstatus_set(eth_dev, &new);
1518 _rte_eth_dev_callback_process(eth_dev,
1519 RTE_ETH_EVENT_INTR_LSC,
1522 bnxt_print_link_info(eth_dev);
1528 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1529 int wait_to_complete)
1531 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1534 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1536 struct bnxt *bp = eth_dev->data->dev_private;
1537 struct bnxt_vnic_info *vnic;
1541 rc = is_bnxt_in_error(bp);
1545 /* Filter settings will get applied when port is started */
1546 if (!eth_dev->data->dev_started)
1549 if (bp->vnic_info == NULL)
1552 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1554 old_flags = vnic->flags;
1555 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1556 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1558 vnic->flags = old_flags;
1563 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1565 struct bnxt *bp = eth_dev->data->dev_private;
1566 struct bnxt_vnic_info *vnic;
1570 rc = is_bnxt_in_error(bp);
1574 /* Filter settings will get applied when port is started */
1575 if (!eth_dev->data->dev_started)
1578 if (bp->vnic_info == NULL)
1581 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1583 old_flags = vnic->flags;
1584 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1585 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1587 vnic->flags = old_flags;
1589 bnxt_ulp_create_df_rules(bp);
1594 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1596 struct bnxt *bp = eth_dev->data->dev_private;
1597 struct bnxt_vnic_info *vnic;
1601 rc = is_bnxt_in_error(bp);
1605 /* Filter settings will get applied when port is started */
1606 if (!eth_dev->data->dev_started)
1609 if (bp->vnic_info == NULL)
1612 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1614 old_flags = vnic->flags;
1615 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1616 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1618 vnic->flags = old_flags;
1623 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1625 struct bnxt *bp = eth_dev->data->dev_private;
1626 struct bnxt_vnic_info *vnic;
1630 rc = is_bnxt_in_error(bp);
1634 /* Filter settings will get applied when port is started */
1635 if (!eth_dev->data->dev_started)
1638 if (bp->vnic_info == NULL)
1641 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1643 old_flags = vnic->flags;
1644 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1645 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1647 vnic->flags = old_flags;
1652 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1653 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1655 if (qid >= bp->rx_nr_rings)
1658 return bp->eth_dev->data->rx_queues[qid];
1661 /* Return rxq corresponding to a given rss table ring/group ID. */
1662 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1664 struct bnxt_rx_queue *rxq;
1667 if (!BNXT_HAS_RING_GRPS(bp)) {
1668 for (i = 0; i < bp->rx_nr_rings; i++) {
1669 rxq = bp->eth_dev->data->rx_queues[i];
1670 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1674 for (i = 0; i < bp->rx_nr_rings; i++) {
1675 if (bp->grp_info[i].fw_grp_id == fwr)
1680 return INVALID_HW_RING_ID;
1683 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1684 struct rte_eth_rss_reta_entry64 *reta_conf,
1687 struct bnxt *bp = eth_dev->data->dev_private;
1688 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1689 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1690 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1694 rc = is_bnxt_in_error(bp);
1698 if (!vnic->rss_table)
1701 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1704 if (reta_size != tbl_size) {
1705 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1706 "(%d) must equal the size supported by the hardware "
1707 "(%d)\n", reta_size, tbl_size);
1711 for (i = 0; i < reta_size; i++) {
1712 struct bnxt_rx_queue *rxq;
1714 idx = i / RTE_RETA_GROUP_SIZE;
1715 sft = i % RTE_RETA_GROUP_SIZE;
1717 if (!(reta_conf[idx].mask & (1ULL << sft)))
1720 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1722 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1726 if (BNXT_CHIP_THOR(bp)) {
1727 vnic->rss_table[i * 2] =
1728 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1729 vnic->rss_table[i * 2 + 1] =
1730 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1732 vnic->rss_table[i] =
1733 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1737 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1741 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1742 struct rte_eth_rss_reta_entry64 *reta_conf,
1745 struct bnxt *bp = eth_dev->data->dev_private;
1746 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1747 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1748 uint16_t idx, sft, i;
1751 rc = is_bnxt_in_error(bp);
1755 /* Retrieve from the default VNIC */
1758 if (!vnic->rss_table)
1761 if (reta_size != tbl_size) {
1762 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1763 "(%d) must equal the size supported by the hardware "
1764 "(%d)\n", reta_size, tbl_size);
1768 for (idx = 0, i = 0; i < reta_size; i++) {
1769 idx = i / RTE_RETA_GROUP_SIZE;
1770 sft = i % RTE_RETA_GROUP_SIZE;
1772 if (reta_conf[idx].mask & (1ULL << sft)) {
1775 if (BNXT_CHIP_THOR(bp))
1776 qid = bnxt_rss_to_qid(bp,
1777 vnic->rss_table[i * 2]);
1779 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1781 if (qid == INVALID_HW_RING_ID) {
1782 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1785 reta_conf[idx].reta[sft] = qid;
1792 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1793 struct rte_eth_rss_conf *rss_conf)
1795 struct bnxt *bp = eth_dev->data->dev_private;
1796 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1797 struct bnxt_vnic_info *vnic;
1800 rc = is_bnxt_in_error(bp);
1805 * If RSS enablement were different than dev_configure,
1806 * then return -EINVAL
1808 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1809 if (!rss_conf->rss_hf)
1810 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1812 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1816 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1817 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1821 /* Update the default RSS VNIC(s) */
1822 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1823 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1826 * If hashkey is not specified, use the previously configured
1829 if (!rss_conf->rss_key)
1832 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1834 "Invalid hashkey length, should be 16 bytes\n");
1837 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1840 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1844 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1845 struct rte_eth_rss_conf *rss_conf)
1847 struct bnxt *bp = eth_dev->data->dev_private;
1848 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1850 uint32_t hash_types;
1852 rc = is_bnxt_in_error(bp);
1856 /* RSS configuration is the same for all VNICs */
1857 if (vnic && vnic->rss_hash_key) {
1858 if (rss_conf->rss_key) {
1859 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1860 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1861 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1864 hash_types = vnic->hash_type;
1865 rss_conf->rss_hf = 0;
1866 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1867 rss_conf->rss_hf |= ETH_RSS_IPV4;
1868 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1870 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1871 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1873 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1875 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1876 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1878 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1880 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1881 rss_conf->rss_hf |= ETH_RSS_IPV6;
1882 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1884 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1885 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1887 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1889 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1890 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1892 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1896 "Unknown RSS config from firmware (%08x), RSS disabled",
1901 rss_conf->rss_hf = 0;
1906 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1907 struct rte_eth_fc_conf *fc_conf)
1909 struct bnxt *bp = dev->data->dev_private;
1910 struct rte_eth_link link_info;
1913 rc = is_bnxt_in_error(bp);
1917 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1921 memset(fc_conf, 0, sizeof(*fc_conf));
1922 if (bp->link_info->auto_pause)
1923 fc_conf->autoneg = 1;
1924 switch (bp->link_info->pause) {
1926 fc_conf->mode = RTE_FC_NONE;
1928 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1929 fc_conf->mode = RTE_FC_TX_PAUSE;
1931 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1932 fc_conf->mode = RTE_FC_RX_PAUSE;
1934 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1935 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1936 fc_conf->mode = RTE_FC_FULL;
1942 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1943 struct rte_eth_fc_conf *fc_conf)
1945 struct bnxt *bp = dev->data->dev_private;
1948 rc = is_bnxt_in_error(bp);
1952 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1953 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1957 switch (fc_conf->mode) {
1959 bp->link_info->auto_pause = 0;
1960 bp->link_info->force_pause = 0;
1962 case RTE_FC_RX_PAUSE:
1963 if (fc_conf->autoneg) {
1964 bp->link_info->auto_pause =
1965 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1966 bp->link_info->force_pause = 0;
1968 bp->link_info->auto_pause = 0;
1969 bp->link_info->force_pause =
1970 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1973 case RTE_FC_TX_PAUSE:
1974 if (fc_conf->autoneg) {
1975 bp->link_info->auto_pause =
1976 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1977 bp->link_info->force_pause = 0;
1979 bp->link_info->auto_pause = 0;
1980 bp->link_info->force_pause =
1981 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1985 if (fc_conf->autoneg) {
1986 bp->link_info->auto_pause =
1987 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1988 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1989 bp->link_info->force_pause = 0;
1991 bp->link_info->auto_pause = 0;
1992 bp->link_info->force_pause =
1993 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1994 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1998 return bnxt_set_hwrm_link_config(bp, true);
2001 /* Add UDP tunneling port */
2003 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2004 struct rte_eth_udp_tunnel *udp_tunnel)
2006 struct bnxt *bp = eth_dev->data->dev_private;
2007 uint16_t tunnel_type = 0;
2010 rc = is_bnxt_in_error(bp);
2014 switch (udp_tunnel->prot_type) {
2015 case RTE_TUNNEL_TYPE_VXLAN:
2016 if (bp->vxlan_port_cnt) {
2017 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2018 udp_tunnel->udp_port);
2019 if (bp->vxlan_port != udp_tunnel->udp_port) {
2020 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2023 bp->vxlan_port_cnt++;
2027 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2028 bp->vxlan_port_cnt++;
2030 case RTE_TUNNEL_TYPE_GENEVE:
2031 if (bp->geneve_port_cnt) {
2032 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2033 udp_tunnel->udp_port);
2034 if (bp->geneve_port != udp_tunnel->udp_port) {
2035 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2038 bp->geneve_port_cnt++;
2042 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2043 bp->geneve_port_cnt++;
2046 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2049 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2055 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2056 struct rte_eth_udp_tunnel *udp_tunnel)
2058 struct bnxt *bp = eth_dev->data->dev_private;
2059 uint16_t tunnel_type = 0;
2063 rc = is_bnxt_in_error(bp);
2067 switch (udp_tunnel->prot_type) {
2068 case RTE_TUNNEL_TYPE_VXLAN:
2069 if (!bp->vxlan_port_cnt) {
2070 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2073 if (bp->vxlan_port != udp_tunnel->udp_port) {
2074 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2075 udp_tunnel->udp_port, bp->vxlan_port);
2078 if (--bp->vxlan_port_cnt)
2082 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2083 port = bp->vxlan_fw_dst_port_id;
2085 case RTE_TUNNEL_TYPE_GENEVE:
2086 if (!bp->geneve_port_cnt) {
2087 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2090 if (bp->geneve_port != udp_tunnel->udp_port) {
2091 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2092 udp_tunnel->udp_port, bp->geneve_port);
2095 if (--bp->geneve_port_cnt)
2099 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2100 port = bp->geneve_fw_dst_port_id;
2103 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2107 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2110 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2113 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2114 bp->geneve_port = 0;
2119 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2121 struct bnxt_filter_info *filter;
2122 struct bnxt_vnic_info *vnic;
2124 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2126 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2127 filter = STAILQ_FIRST(&vnic->filter);
2129 /* Search for this matching MAC+VLAN filter */
2130 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2131 /* Delete the filter */
2132 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2135 STAILQ_REMOVE(&vnic->filter, filter,
2136 bnxt_filter_info, next);
2137 bnxt_free_filter(bp, filter);
2139 "Deleted vlan filter for %d\n",
2143 filter = STAILQ_NEXT(filter, next);
2148 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2150 struct bnxt_filter_info *filter;
2151 struct bnxt_vnic_info *vnic;
2153 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2154 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2155 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2157 /* Implementation notes on the use of VNIC in this command:
2159 * By default, these filters belong to default vnic for the function.
2160 * Once these filters are set up, only destination VNIC can be modified.
2161 * If the destination VNIC is not specified in this command,
2162 * then the HWRM shall only create an l2 context id.
2165 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2166 filter = STAILQ_FIRST(&vnic->filter);
2167 /* Check if the VLAN has already been added */
2169 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2172 filter = STAILQ_NEXT(filter, next);
2175 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2176 * command to create MAC+VLAN filter with the right flags, enables set.
2178 filter = bnxt_alloc_filter(bp);
2181 "MAC/VLAN filter alloc failed\n");
2184 /* MAC + VLAN ID filter */
2185 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2186 * untagged packets are received
2188 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2189 * packets and only the programmed vlan's packets are received
2191 filter->l2_ivlan = vlan_id;
2192 filter->l2_ivlan_mask = 0x0FFF;
2193 filter->enables |= en;
2194 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2196 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2198 /* Free the newly allocated filter as we were
2199 * not able to create the filter in hardware.
2201 bnxt_free_filter(bp, filter);
2205 filter->mac_index = 0;
2206 /* Add this new filter to the list */
2208 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2210 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2213 "Added Vlan filter for %d\n", vlan_id);
2217 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2218 uint16_t vlan_id, int on)
2220 struct bnxt *bp = eth_dev->data->dev_private;
2223 rc = is_bnxt_in_error(bp);
2227 if (!eth_dev->data->dev_started) {
2228 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2232 /* These operations apply to ALL existing MAC/VLAN filters */
2234 return bnxt_add_vlan_filter(bp, vlan_id);
2236 return bnxt_del_vlan_filter(bp, vlan_id);
2239 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2240 struct bnxt_vnic_info *vnic)
2242 struct bnxt_filter_info *filter;
2245 filter = STAILQ_FIRST(&vnic->filter);
2247 if (filter->mac_index == 0 &&
2248 !memcmp(filter->l2_addr, bp->mac_addr,
2249 RTE_ETHER_ADDR_LEN)) {
2250 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2252 STAILQ_REMOVE(&vnic->filter, filter,
2253 bnxt_filter_info, next);
2254 bnxt_free_filter(bp, filter);
2258 filter = STAILQ_NEXT(filter, next);
2264 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2266 struct bnxt_vnic_info *vnic;
2270 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2271 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2272 /* Remove any VLAN filters programmed */
2273 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2274 bnxt_del_vlan_filter(bp, i);
2276 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2280 /* Default filter will allow packets that match the
2281 * dest mac. So, it has to be deleted, otherwise, we
2282 * will endup receiving vlan packets for which the
2283 * filter is not programmed, when hw-vlan-filter
2284 * configuration is ON
2286 bnxt_del_dflt_mac_filter(bp, vnic);
2287 /* This filter will allow only untagged packets */
2288 bnxt_add_vlan_filter(bp, 0);
2290 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2291 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2296 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2298 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2302 /* Destroy vnic filters and vnic */
2303 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2304 DEV_RX_OFFLOAD_VLAN_FILTER) {
2305 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2306 bnxt_del_vlan_filter(bp, i);
2308 bnxt_del_dflt_mac_filter(bp, vnic);
2310 rc = bnxt_hwrm_vnic_free(bp, vnic);
2314 rte_free(vnic->fw_grp_ids);
2315 vnic->fw_grp_ids = NULL;
2317 vnic->rx_queue_cnt = 0;
2323 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2325 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2328 /* Destroy, recreate and reconfigure the default vnic */
2329 rc = bnxt_free_one_vnic(bp, 0);
2333 /* default vnic 0 */
2334 rc = bnxt_setup_one_vnic(bp, 0);
2338 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2339 DEV_RX_OFFLOAD_VLAN_FILTER) {
2340 rc = bnxt_add_vlan_filter(bp, 0);
2343 rc = bnxt_restore_vlan_filters(bp);
2347 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2352 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2356 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2357 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2363 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2365 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2366 struct bnxt *bp = dev->data->dev_private;
2369 rc = is_bnxt_in_error(bp);
2373 /* Filter settings will get applied when port is started */
2374 if (!dev->data->dev_started)
2377 if (mask & ETH_VLAN_FILTER_MASK) {
2378 /* Enable or disable VLAN filtering */
2379 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2384 if (mask & ETH_VLAN_STRIP_MASK) {
2385 /* Enable or disable VLAN stripping */
2386 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2391 if (mask & ETH_VLAN_EXTEND_MASK) {
2392 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2393 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2395 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2402 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2405 struct bnxt *bp = dev->data->dev_private;
2406 int qinq = dev->data->dev_conf.rxmode.offloads &
2407 DEV_RX_OFFLOAD_VLAN_EXTEND;
2409 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2410 vlan_type != ETH_VLAN_TYPE_OUTER) {
2412 "Unsupported vlan type.");
2417 "QinQ not enabled. Needs to be ON as we can "
2418 "accelerate only outer vlan\n");
2422 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2424 case RTE_ETHER_TYPE_QINQ:
2426 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2428 case RTE_ETHER_TYPE_VLAN:
2430 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2432 case RTE_ETHER_TYPE_QINQ1:
2434 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2436 case RTE_ETHER_TYPE_QINQ2:
2438 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2440 case RTE_ETHER_TYPE_QINQ3:
2442 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2445 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2448 bp->outer_tpid_bd |= tpid;
2449 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2450 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2452 "Can accelerate only outer vlan in QinQ\n");
2460 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2461 struct rte_ether_addr *addr)
2463 struct bnxt *bp = dev->data->dev_private;
2464 /* Default Filter is tied to VNIC 0 */
2465 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2468 rc = is_bnxt_in_error(bp);
2472 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2475 if (rte_is_zero_ether_addr(addr))
2478 /* Filter settings will get applied when port is started */
2479 if (!dev->data->dev_started)
2482 /* Check if the requested MAC is already added */
2483 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2486 /* Destroy filter and re-create it */
2487 bnxt_del_dflt_mac_filter(bp, vnic);
2489 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2490 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2491 /* This filter will allow only untagged packets */
2492 rc = bnxt_add_vlan_filter(bp, 0);
2494 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2497 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2502 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2503 struct rte_ether_addr *mc_addr_set,
2504 uint32_t nb_mc_addr)
2506 struct bnxt *bp = eth_dev->data->dev_private;
2507 char *mc_addr_list = (char *)mc_addr_set;
2508 struct bnxt_vnic_info *vnic;
2509 uint32_t off = 0, i = 0;
2512 rc = is_bnxt_in_error(bp);
2516 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2518 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2519 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2523 /* TODO Check for Duplicate mcast addresses */
2524 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2525 for (i = 0; i < nb_mc_addr; i++) {
2526 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2527 RTE_ETHER_ADDR_LEN);
2528 off += RTE_ETHER_ADDR_LEN;
2531 vnic->mc_addr_cnt = i;
2532 if (vnic->mc_addr_cnt)
2533 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2535 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2538 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2542 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2544 struct bnxt *bp = dev->data->dev_private;
2545 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2546 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2547 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2548 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2551 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2552 fw_major, fw_minor, fw_updt, fw_rsvd);
2554 ret += 1; /* add the size of '\0' */
2555 if (fw_size < (uint32_t)ret)
2562 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2563 struct rte_eth_rxq_info *qinfo)
2565 struct bnxt *bp = dev->data->dev_private;
2566 struct bnxt_rx_queue *rxq;
2568 if (is_bnxt_in_error(bp))
2571 rxq = dev->data->rx_queues[queue_id];
2573 qinfo->mp = rxq->mb_pool;
2574 qinfo->scattered_rx = dev->data->scattered_rx;
2575 qinfo->nb_desc = rxq->nb_rx_desc;
2577 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2578 qinfo->conf.rx_drop_en = 0;
2579 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2583 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2584 struct rte_eth_txq_info *qinfo)
2586 struct bnxt *bp = dev->data->dev_private;
2587 struct bnxt_tx_queue *txq;
2589 if (is_bnxt_in_error(bp))
2592 txq = dev->data->tx_queues[queue_id];
2594 qinfo->nb_desc = txq->nb_tx_desc;
2596 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2597 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2598 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2600 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2601 qinfo->conf.tx_rs_thresh = 0;
2602 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2606 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2607 struct rte_eth_burst_mode *mode)
2609 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2611 if (pkt_burst == bnxt_recv_pkts) {
2612 snprintf(mode->info, sizeof(mode->info), "%s",
2616 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2617 if (pkt_burst == bnxt_recv_pkts_vec) {
2618 snprintf(mode->info, sizeof(mode->info), "%s",
2628 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2629 struct rte_eth_burst_mode *mode)
2631 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2633 if (pkt_burst == bnxt_xmit_pkts) {
2634 snprintf(mode->info, sizeof(mode->info), "%s",
2638 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2639 if (pkt_burst == bnxt_xmit_pkts_vec) {
2640 snprintf(mode->info, sizeof(mode->info), "%s",
2649 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2651 struct bnxt *bp = eth_dev->data->dev_private;
2652 uint32_t new_pkt_size;
2656 rc = is_bnxt_in_error(bp);
2660 /* Exit if receive queues are not configured yet */
2661 if (!eth_dev->data->nb_rx_queues)
2664 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2665 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2667 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2669 * If vector-mode tx/rx is active, disallow any MTU change that would
2670 * require scattered receive support.
2672 if (eth_dev->data->dev_started &&
2673 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2674 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2676 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2678 "MTU change would require scattered rx support. ");
2679 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2684 if (new_mtu > RTE_ETHER_MTU) {
2685 bp->flags |= BNXT_FLAG_JUMBO;
2686 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2687 DEV_RX_OFFLOAD_JUMBO_FRAME;
2689 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2690 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2691 bp->flags &= ~BNXT_FLAG_JUMBO;
2694 /* Is there a change in mtu setting? */
2695 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2698 for (i = 0; i < bp->nr_vnics; i++) {
2699 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2702 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2703 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2707 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2708 size -= RTE_PKTMBUF_HEADROOM;
2710 if (size < new_mtu) {
2711 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2718 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2720 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2726 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2728 struct bnxt *bp = dev->data->dev_private;
2729 uint16_t vlan = bp->vlan;
2732 rc = is_bnxt_in_error(bp);
2736 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2738 "PVID cannot be modified for this function\n");
2741 bp->vlan = on ? pvid : 0;
2743 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2750 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2752 struct bnxt *bp = dev->data->dev_private;
2755 rc = is_bnxt_in_error(bp);
2759 return bnxt_hwrm_port_led_cfg(bp, true);
2763 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2765 struct bnxt *bp = dev->data->dev_private;
2768 rc = is_bnxt_in_error(bp);
2772 return bnxt_hwrm_port_led_cfg(bp, false);
2776 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2778 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2779 uint32_t desc = 0, raw_cons = 0, cons;
2780 struct bnxt_cp_ring_info *cpr;
2781 struct bnxt_rx_queue *rxq;
2782 struct rx_pkt_cmpl *rxcmp;
2785 rc = is_bnxt_in_error(bp);
2789 rxq = dev->data->rx_queues[rx_queue_id];
2791 raw_cons = cpr->cp_raw_cons;
2794 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2795 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2796 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2798 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2810 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2812 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2813 struct bnxt_rx_ring_info *rxr;
2814 struct bnxt_cp_ring_info *cpr;
2815 struct bnxt_sw_rx_bd *rx_buf;
2816 struct rx_pkt_cmpl *rxcmp;
2817 uint32_t cons, cp_cons;
2823 rc = is_bnxt_in_error(rxq->bp);
2830 if (offset >= rxq->nb_rx_desc)
2833 cons = RING_CMP(cpr->cp_ring_struct, offset);
2834 cp_cons = cpr->cp_raw_cons;
2835 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2837 if (cons > cp_cons) {
2838 if (CMPL_VALID(rxcmp, cpr->valid))
2839 return RTE_ETH_RX_DESC_DONE;
2841 if (CMPL_VALID(rxcmp, !cpr->valid))
2842 return RTE_ETH_RX_DESC_DONE;
2844 rx_buf = &rxr->rx_buf_ring[cons];
2845 if (rx_buf->mbuf == NULL)
2846 return RTE_ETH_RX_DESC_UNAVAIL;
2849 return RTE_ETH_RX_DESC_AVAIL;
2853 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2855 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2856 struct bnxt_tx_ring_info *txr;
2857 struct bnxt_cp_ring_info *cpr;
2858 struct bnxt_sw_tx_bd *tx_buf;
2859 struct tx_pkt_cmpl *txcmp;
2860 uint32_t cons, cp_cons;
2866 rc = is_bnxt_in_error(txq->bp);
2873 if (offset >= txq->nb_tx_desc)
2876 cons = RING_CMP(cpr->cp_ring_struct, offset);
2877 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2878 cp_cons = cpr->cp_raw_cons;
2880 if (cons > cp_cons) {
2881 if (CMPL_VALID(txcmp, cpr->valid))
2882 return RTE_ETH_TX_DESC_UNAVAIL;
2884 if (CMPL_VALID(txcmp, !cpr->valid))
2885 return RTE_ETH_TX_DESC_UNAVAIL;
2887 tx_buf = &txr->tx_buf_ring[cons];
2888 if (tx_buf->mbuf == NULL)
2889 return RTE_ETH_TX_DESC_DONE;
2891 return RTE_ETH_TX_DESC_FULL;
2894 static struct bnxt_filter_info *
2895 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2896 struct rte_eth_ethertype_filter *efilter,
2897 struct bnxt_vnic_info *vnic0,
2898 struct bnxt_vnic_info *vnic,
2901 struct bnxt_filter_info *mfilter = NULL;
2905 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2906 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2907 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2908 " ethertype filter.", efilter->ether_type);
2912 if (efilter->queue >= bp->rx_nr_rings) {
2913 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2918 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2919 vnic = &bp->vnic_info[efilter->queue];
2921 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2926 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2927 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2928 if ((!memcmp(efilter->mac_addr.addr_bytes,
2929 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2931 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2932 mfilter->ethertype == efilter->ether_type)) {
2938 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2939 if ((!memcmp(efilter->mac_addr.addr_bytes,
2940 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2941 mfilter->ethertype == efilter->ether_type &&
2943 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2957 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2958 enum rte_filter_op filter_op,
2961 struct bnxt *bp = dev->data->dev_private;
2962 struct rte_eth_ethertype_filter *efilter =
2963 (struct rte_eth_ethertype_filter *)arg;
2964 struct bnxt_filter_info *bfilter, *filter1;
2965 struct bnxt_vnic_info *vnic, *vnic0;
2968 if (filter_op == RTE_ETH_FILTER_NOP)
2972 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2977 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2978 vnic = &bp->vnic_info[efilter->queue];
2980 switch (filter_op) {
2981 case RTE_ETH_FILTER_ADD:
2982 bnxt_match_and_validate_ether_filter(bp, efilter,
2987 bfilter = bnxt_get_unused_filter(bp);
2988 if (bfilter == NULL) {
2990 "Not enough resources for a new filter.\n");
2993 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2994 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2995 RTE_ETHER_ADDR_LEN);
2996 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2997 RTE_ETHER_ADDR_LEN);
2998 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2999 bfilter->ethertype = efilter->ether_type;
3000 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3002 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3003 if (filter1 == NULL) {
3008 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3009 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3011 bfilter->dst_id = vnic->fw_vnic_id;
3013 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3015 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3018 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3021 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3023 case RTE_ETH_FILTER_DELETE:
3024 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3026 if (ret == -EEXIST) {
3027 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3029 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3031 bnxt_free_filter(bp, filter1);
3032 } else if (ret == 0) {
3033 PMD_DRV_LOG(ERR, "No matching filter found\n");
3037 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3043 bnxt_free_filter(bp, bfilter);
3049 parse_ntuple_filter(struct bnxt *bp,
3050 struct rte_eth_ntuple_filter *nfilter,
3051 struct bnxt_filter_info *bfilter)
3055 if (nfilter->queue >= bp->rx_nr_rings) {
3056 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3060 switch (nfilter->dst_port_mask) {
3062 bfilter->dst_port_mask = -1;
3063 bfilter->dst_port = nfilter->dst_port;
3064 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3065 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3068 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3072 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3073 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3075 switch (nfilter->proto_mask) {
3077 if (nfilter->proto == 17) /* IPPROTO_UDP */
3078 bfilter->ip_protocol = 17;
3079 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3080 bfilter->ip_protocol = 6;
3083 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3086 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3090 switch (nfilter->dst_ip_mask) {
3092 bfilter->dst_ipaddr_mask[0] = -1;
3093 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3094 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3095 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3098 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3102 switch (nfilter->src_ip_mask) {
3104 bfilter->src_ipaddr_mask[0] = -1;
3105 bfilter->src_ipaddr[0] = nfilter->src_ip;
3106 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3107 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3110 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3114 switch (nfilter->src_port_mask) {
3116 bfilter->src_port_mask = -1;
3117 bfilter->src_port = nfilter->src_port;
3118 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3119 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3122 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3126 bfilter->enables = en;
3130 static struct bnxt_filter_info*
3131 bnxt_match_ntuple_filter(struct bnxt *bp,
3132 struct bnxt_filter_info *bfilter,
3133 struct bnxt_vnic_info **mvnic)
3135 struct bnxt_filter_info *mfilter = NULL;
3138 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3139 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3140 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3141 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3142 bfilter->src_ipaddr_mask[0] ==
3143 mfilter->src_ipaddr_mask[0] &&
3144 bfilter->src_port == mfilter->src_port &&
3145 bfilter->src_port_mask == mfilter->src_port_mask &&
3146 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3147 bfilter->dst_ipaddr_mask[0] ==
3148 mfilter->dst_ipaddr_mask[0] &&
3149 bfilter->dst_port == mfilter->dst_port &&
3150 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3151 bfilter->flags == mfilter->flags &&
3152 bfilter->enables == mfilter->enables) {
3163 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3164 struct rte_eth_ntuple_filter *nfilter,
3165 enum rte_filter_op filter_op)
3167 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3168 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3171 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3172 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3176 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3177 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3181 bfilter = bnxt_get_unused_filter(bp);
3182 if (bfilter == NULL) {
3184 "Not enough resources for a new filter.\n");
3187 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3191 vnic = &bp->vnic_info[nfilter->queue];
3192 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3193 filter1 = STAILQ_FIRST(&vnic0->filter);
3194 if (filter1 == NULL) {
3199 bfilter->dst_id = vnic->fw_vnic_id;
3200 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3202 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3203 bfilter->ethertype = 0x800;
3204 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3206 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3208 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3209 bfilter->dst_id == mfilter->dst_id) {
3210 PMD_DRV_LOG(ERR, "filter exists.\n");
3213 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3214 bfilter->dst_id != mfilter->dst_id) {
3215 mfilter->dst_id = vnic->fw_vnic_id;
3216 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3217 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3218 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3219 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3220 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3223 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3224 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3229 if (filter_op == RTE_ETH_FILTER_ADD) {
3230 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3231 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3234 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3236 if (mfilter == NULL) {
3237 /* This should not happen. But for Coverity! */
3241 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3243 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3244 bnxt_free_filter(bp, mfilter);
3245 bnxt_free_filter(bp, bfilter);
3250 bnxt_free_filter(bp, bfilter);
3255 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3256 enum rte_filter_op filter_op,
3259 struct bnxt *bp = dev->data->dev_private;
3262 if (filter_op == RTE_ETH_FILTER_NOP)
3266 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3271 switch (filter_op) {
3272 case RTE_ETH_FILTER_ADD:
3273 ret = bnxt_cfg_ntuple_filter(bp,
3274 (struct rte_eth_ntuple_filter *)arg,
3277 case RTE_ETH_FILTER_DELETE:
3278 ret = bnxt_cfg_ntuple_filter(bp,
3279 (struct rte_eth_ntuple_filter *)arg,
3283 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3291 bnxt_parse_fdir_filter(struct bnxt *bp,
3292 struct rte_eth_fdir_filter *fdir,
3293 struct bnxt_filter_info *filter)
3295 enum rte_fdir_mode fdir_mode =
3296 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3297 struct bnxt_vnic_info *vnic0, *vnic;
3298 struct bnxt_filter_info *filter1;
3302 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3305 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3306 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3308 switch (fdir->input.flow_type) {
3309 case RTE_ETH_FLOW_IPV4:
3310 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3312 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3313 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3314 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3315 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3316 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3317 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3318 filter->ip_addr_type =
3319 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3320 filter->src_ipaddr_mask[0] = 0xffffffff;
3321 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3322 filter->dst_ipaddr_mask[0] = 0xffffffff;
3323 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3324 filter->ethertype = 0x800;
3325 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3327 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3328 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3329 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3330 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3331 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3332 filter->dst_port_mask = 0xffff;
3333 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3334 filter->src_port_mask = 0xffff;
3335 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3336 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3337 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3338 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3339 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3340 filter->ip_protocol = 6;
3341 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3342 filter->ip_addr_type =
3343 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3344 filter->src_ipaddr_mask[0] = 0xffffffff;
3345 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3346 filter->dst_ipaddr_mask[0] = 0xffffffff;
3347 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3348 filter->ethertype = 0x800;
3349 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3351 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3352 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3353 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3354 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3355 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3356 filter->dst_port_mask = 0xffff;
3357 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3358 filter->src_port_mask = 0xffff;
3359 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3360 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3362 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3363 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3364 filter->ip_protocol = 17;
3365 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3366 filter->ip_addr_type =
3367 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3368 filter->src_ipaddr_mask[0] = 0xffffffff;
3369 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3370 filter->dst_ipaddr_mask[0] = 0xffffffff;
3371 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3372 filter->ethertype = 0x800;
3373 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3375 case RTE_ETH_FLOW_IPV6:
3376 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3378 filter->ip_addr_type =
3379 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3380 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3381 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3382 rte_memcpy(filter->src_ipaddr,
3383 fdir->input.flow.ipv6_flow.src_ip, 16);
3384 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3385 rte_memcpy(filter->dst_ipaddr,
3386 fdir->input.flow.ipv6_flow.dst_ip, 16);
3387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3388 memset(filter->dst_ipaddr_mask, 0xff, 16);
3389 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3390 memset(filter->src_ipaddr_mask, 0xff, 16);
3391 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3392 filter->ethertype = 0x86dd;
3393 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3395 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3396 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3398 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3399 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3400 filter->dst_port_mask = 0xffff;
3401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3402 filter->src_port_mask = 0xffff;
3403 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3404 filter->ip_addr_type =
3405 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3406 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3407 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3408 rte_memcpy(filter->src_ipaddr,
3409 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3410 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3411 rte_memcpy(filter->dst_ipaddr,
3412 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3413 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3414 memset(filter->dst_ipaddr_mask, 0xff, 16);
3415 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3416 memset(filter->src_ipaddr_mask, 0xff, 16);
3417 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3418 filter->ethertype = 0x86dd;
3419 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3421 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3422 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3423 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3424 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3425 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3426 filter->dst_port_mask = 0xffff;
3427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3428 filter->src_port_mask = 0xffff;
3429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3430 filter->ip_addr_type =
3431 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3432 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3433 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3434 rte_memcpy(filter->src_ipaddr,
3435 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3436 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3437 rte_memcpy(filter->dst_ipaddr,
3438 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3440 memset(filter->dst_ipaddr_mask, 0xff, 16);
3441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3442 memset(filter->src_ipaddr_mask, 0xff, 16);
3443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3444 filter->ethertype = 0x86dd;
3445 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3447 case RTE_ETH_FLOW_L2_PAYLOAD:
3448 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3449 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3451 case RTE_ETH_FLOW_VXLAN:
3452 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3454 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3455 filter->tunnel_type =
3456 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3457 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3459 case RTE_ETH_FLOW_NVGRE:
3460 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3462 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3463 filter->tunnel_type =
3464 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3465 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3467 case RTE_ETH_FLOW_UNKNOWN:
3468 case RTE_ETH_FLOW_RAW:
3469 case RTE_ETH_FLOW_FRAG_IPV4:
3470 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3471 case RTE_ETH_FLOW_FRAG_IPV6:
3472 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3473 case RTE_ETH_FLOW_IPV6_EX:
3474 case RTE_ETH_FLOW_IPV6_TCP_EX:
3475 case RTE_ETH_FLOW_IPV6_UDP_EX:
3476 case RTE_ETH_FLOW_GENEVE:
3482 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3483 vnic = &bp->vnic_info[fdir->action.rx_queue];
3485 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3489 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3490 rte_memcpy(filter->dst_macaddr,
3491 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3492 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3495 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3496 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3497 filter1 = STAILQ_FIRST(&vnic0->filter);
3498 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3500 filter->dst_id = vnic->fw_vnic_id;
3501 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3502 if (filter->dst_macaddr[i] == 0x00)
3503 filter1 = STAILQ_FIRST(&vnic0->filter);
3505 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3508 if (filter1 == NULL)
3511 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3512 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3514 filter->enables = en;
3519 static struct bnxt_filter_info *
3520 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3521 struct bnxt_vnic_info **mvnic)
3523 struct bnxt_filter_info *mf = NULL;
3526 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3527 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3529 STAILQ_FOREACH(mf, &vnic->filter, next) {
3530 if (mf->filter_type == nf->filter_type &&
3531 mf->flags == nf->flags &&
3532 mf->src_port == nf->src_port &&
3533 mf->src_port_mask == nf->src_port_mask &&
3534 mf->dst_port == nf->dst_port &&
3535 mf->dst_port_mask == nf->dst_port_mask &&
3536 mf->ip_protocol == nf->ip_protocol &&
3537 mf->ip_addr_type == nf->ip_addr_type &&
3538 mf->ethertype == nf->ethertype &&
3539 mf->vni == nf->vni &&
3540 mf->tunnel_type == nf->tunnel_type &&
3541 mf->l2_ovlan == nf->l2_ovlan &&
3542 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3543 mf->l2_ivlan == nf->l2_ivlan &&
3544 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3545 !memcmp(mf->l2_addr, nf->l2_addr,
3546 RTE_ETHER_ADDR_LEN) &&
3547 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3548 RTE_ETHER_ADDR_LEN) &&
3549 !memcmp(mf->src_macaddr, nf->src_macaddr,
3550 RTE_ETHER_ADDR_LEN) &&
3551 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3552 RTE_ETHER_ADDR_LEN) &&
3553 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3554 sizeof(nf->src_ipaddr)) &&
3555 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3556 sizeof(nf->src_ipaddr_mask)) &&
3557 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3558 sizeof(nf->dst_ipaddr)) &&
3559 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3560 sizeof(nf->dst_ipaddr_mask))) {
3571 bnxt_fdir_filter(struct rte_eth_dev *dev,
3572 enum rte_filter_op filter_op,
3575 struct bnxt *bp = dev->data->dev_private;
3576 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3577 struct bnxt_filter_info *filter, *match;
3578 struct bnxt_vnic_info *vnic, *mvnic;
3581 if (filter_op == RTE_ETH_FILTER_NOP)
3584 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3587 switch (filter_op) {
3588 case RTE_ETH_FILTER_ADD:
3589 case RTE_ETH_FILTER_DELETE:
3591 filter = bnxt_get_unused_filter(bp);
3592 if (filter == NULL) {
3594 "Not enough resources for a new flow.\n");
3598 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3601 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3603 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3604 vnic = &bp->vnic_info[0];
3606 vnic = &bp->vnic_info[fdir->action.rx_queue];
3608 match = bnxt_match_fdir(bp, filter, &mvnic);
3609 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3610 if (match->dst_id == vnic->fw_vnic_id) {
3611 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3615 match->dst_id = vnic->fw_vnic_id;
3616 ret = bnxt_hwrm_set_ntuple_filter(bp,
3619 STAILQ_REMOVE(&mvnic->filter, match,
3620 bnxt_filter_info, next);
3621 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3623 "Filter with matching pattern exist\n");
3625 "Updated it to new destination q\n");
3629 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3630 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3635 if (filter_op == RTE_ETH_FILTER_ADD) {
3636 ret = bnxt_hwrm_set_ntuple_filter(bp,
3641 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3643 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3644 STAILQ_REMOVE(&vnic->filter, match,
3645 bnxt_filter_info, next);
3646 bnxt_free_filter(bp, match);
3647 bnxt_free_filter(bp, filter);
3650 case RTE_ETH_FILTER_FLUSH:
3651 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3652 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3654 STAILQ_FOREACH(filter, &vnic->filter, next) {
3655 if (filter->filter_type ==
3656 HWRM_CFA_NTUPLE_FILTER) {
3658 bnxt_hwrm_clear_ntuple_filter(bp,
3660 STAILQ_REMOVE(&vnic->filter, filter,
3661 bnxt_filter_info, next);
3666 case RTE_ETH_FILTER_UPDATE:
3667 case RTE_ETH_FILTER_STATS:
3668 case RTE_ETH_FILTER_INFO:
3669 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3672 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3679 bnxt_free_filter(bp, filter);
3684 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3685 enum rte_filter_type filter_type,
3686 enum rte_filter_op filter_op, void *arg)
3688 struct bnxt *bp = dev->data->dev_private;
3691 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3692 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3693 bp = vfr->parent_dev->data->dev_private;
3696 ret = is_bnxt_in_error(bp);
3700 switch (filter_type) {
3701 case RTE_ETH_FILTER_TUNNEL:
3703 "filter type: %d: To be implemented\n", filter_type);
3705 case RTE_ETH_FILTER_FDIR:
3706 ret = bnxt_fdir_filter(dev, filter_op, arg);
3708 case RTE_ETH_FILTER_NTUPLE:
3709 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3711 case RTE_ETH_FILTER_ETHERTYPE:
3712 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3714 case RTE_ETH_FILTER_GENERIC:
3715 if (filter_op != RTE_ETH_FILTER_GET)
3717 if (BNXT_TRUFLOW_EN(bp))
3718 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3720 *(const void **)arg = &bnxt_flow_ops;
3724 "Filter type (%d) not supported", filter_type);
3731 static const uint32_t *
3732 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3734 static const uint32_t ptypes[] = {
3735 RTE_PTYPE_L2_ETHER_VLAN,
3736 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3737 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3741 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3742 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3743 RTE_PTYPE_INNER_L4_ICMP,
3744 RTE_PTYPE_INNER_L4_TCP,
3745 RTE_PTYPE_INNER_L4_UDP,
3749 if (!dev->rx_pkt_burst)
3755 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3758 uint32_t reg_base = *reg_arr & 0xfffff000;
3762 for (i = 0; i < count; i++) {
3763 if ((reg_arr[i] & 0xfffff000) != reg_base)
3766 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3767 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3771 static int bnxt_map_ptp_regs(struct bnxt *bp)
3773 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3777 reg_arr = ptp->rx_regs;
3778 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3782 reg_arr = ptp->tx_regs;
3783 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3787 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3788 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3790 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3791 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3796 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3798 rte_write32(0, (uint8_t *)bp->bar0 +
3799 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3800 rte_write32(0, (uint8_t *)bp->bar0 +
3801 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3804 static uint64_t bnxt_cc_read(struct bnxt *bp)
3808 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3809 BNXT_GRCPF_REG_SYNC_TIME));
3810 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3811 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3815 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3817 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3820 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3821 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3822 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3825 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3826 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3827 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3828 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3829 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3830 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3835 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3837 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3838 struct bnxt_pf_info *pf = bp->pf;
3845 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3846 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3847 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3850 port_id = pf->port_id;
3851 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3852 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3854 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3855 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3856 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3857 /* bnxt_clr_rx_ts(bp); TBD */
3861 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3862 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3863 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3864 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3870 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3873 struct bnxt *bp = dev->data->dev_private;
3874 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3879 ns = rte_timespec_to_ns(ts);
3880 /* Set the timecounters to a new value. */
3887 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3889 struct bnxt *bp = dev->data->dev_private;
3890 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3891 uint64_t ns, systime_cycles = 0;
3897 if (BNXT_CHIP_THOR(bp))
3898 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3901 systime_cycles = bnxt_cc_read(bp);
3903 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3904 *ts = rte_ns_to_timespec(ns);
3909 bnxt_timesync_enable(struct rte_eth_dev *dev)
3911 struct bnxt *bp = dev->data->dev_private;
3912 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3920 ptp->tx_tstamp_en = 1;
3921 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3923 rc = bnxt_hwrm_ptp_cfg(bp);
3927 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3928 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3929 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3931 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3932 ptp->tc.cc_shift = shift;
3933 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3935 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3936 ptp->rx_tstamp_tc.cc_shift = shift;
3937 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3939 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3940 ptp->tx_tstamp_tc.cc_shift = shift;
3941 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3943 if (!BNXT_CHIP_THOR(bp))
3944 bnxt_map_ptp_regs(bp);
3950 bnxt_timesync_disable(struct rte_eth_dev *dev)
3952 struct bnxt *bp = dev->data->dev_private;
3953 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3959 ptp->tx_tstamp_en = 0;
3962 bnxt_hwrm_ptp_cfg(bp);
3964 if (!BNXT_CHIP_THOR(bp))
3965 bnxt_unmap_ptp_regs(bp);
3971 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3972 struct timespec *timestamp,
3973 uint32_t flags __rte_unused)
3975 struct bnxt *bp = dev->data->dev_private;
3976 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3977 uint64_t rx_tstamp_cycles = 0;
3983 if (BNXT_CHIP_THOR(bp))
3984 rx_tstamp_cycles = ptp->rx_timestamp;
3986 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3988 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3989 *timestamp = rte_ns_to_timespec(ns);
3994 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3995 struct timespec *timestamp)
3997 struct bnxt *bp = dev->data->dev_private;
3998 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3999 uint64_t tx_tstamp_cycles = 0;
4006 if (BNXT_CHIP_THOR(bp))
4007 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4010 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4012 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4013 *timestamp = rte_ns_to_timespec(ns);
4019 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4021 struct bnxt *bp = dev->data->dev_private;
4022 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4027 ptp->tc.nsec += delta;
4033 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4035 struct bnxt *bp = dev->data->dev_private;
4037 uint32_t dir_entries;
4038 uint32_t entry_length;
4040 rc = is_bnxt_in_error(bp);
4044 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4045 bp->pdev->addr.domain, bp->pdev->addr.bus,
4046 bp->pdev->addr.devid, bp->pdev->addr.function);
4048 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4052 return dir_entries * entry_length;
4056 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4057 struct rte_dev_eeprom_info *in_eeprom)
4059 struct bnxt *bp = dev->data->dev_private;
4064 rc = is_bnxt_in_error(bp);
4068 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4069 bp->pdev->addr.domain, bp->pdev->addr.bus,
4070 bp->pdev->addr.devid, bp->pdev->addr.function,
4071 in_eeprom->offset, in_eeprom->length);
4073 if (in_eeprom->offset == 0) /* special offset value to get directory */
4074 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4077 index = in_eeprom->offset >> 24;
4078 offset = in_eeprom->offset & 0xffffff;
4081 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4082 in_eeprom->length, in_eeprom->data);
4087 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4090 case BNX_DIR_TYPE_CHIMP_PATCH:
4091 case BNX_DIR_TYPE_BOOTCODE:
4092 case BNX_DIR_TYPE_BOOTCODE_2:
4093 case BNX_DIR_TYPE_APE_FW:
4094 case BNX_DIR_TYPE_APE_PATCH:
4095 case BNX_DIR_TYPE_KONG_FW:
4096 case BNX_DIR_TYPE_KONG_PATCH:
4097 case BNX_DIR_TYPE_BONO_FW:
4098 case BNX_DIR_TYPE_BONO_PATCH:
4106 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4109 case BNX_DIR_TYPE_AVS:
4110 case BNX_DIR_TYPE_EXP_ROM_MBA:
4111 case BNX_DIR_TYPE_PCIE:
4112 case BNX_DIR_TYPE_TSCF_UCODE:
4113 case BNX_DIR_TYPE_EXT_PHY:
4114 case BNX_DIR_TYPE_CCM:
4115 case BNX_DIR_TYPE_ISCSI_BOOT:
4116 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4117 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4125 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4127 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4128 bnxt_dir_type_is_other_exec_format(dir_type);
4132 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4133 struct rte_dev_eeprom_info *in_eeprom)
4135 struct bnxt *bp = dev->data->dev_private;
4136 uint8_t index, dir_op;
4137 uint16_t type, ext, ordinal, attr;
4140 rc = is_bnxt_in_error(bp);
4144 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4145 bp->pdev->addr.domain, bp->pdev->addr.bus,
4146 bp->pdev->addr.devid, bp->pdev->addr.function,
4147 in_eeprom->offset, in_eeprom->length);
4150 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4154 type = in_eeprom->magic >> 16;
4156 if (type == 0xffff) { /* special value for directory operations */
4157 index = in_eeprom->magic & 0xff;
4158 dir_op = in_eeprom->magic >> 8;
4162 case 0x0e: /* erase */
4163 if (in_eeprom->offset != ~in_eeprom->magic)
4165 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4171 /* Create or re-write an NVM item: */
4172 if (bnxt_dir_type_is_executable(type) == true)
4174 ext = in_eeprom->magic & 0xffff;
4175 ordinal = in_eeprom->offset >> 16;
4176 attr = in_eeprom->offset & 0xffff;
4178 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4179 in_eeprom->data, in_eeprom->length);
4186 static const struct eth_dev_ops bnxt_dev_ops = {
4187 .dev_infos_get = bnxt_dev_info_get_op,
4188 .dev_close = bnxt_dev_close_op,
4189 .dev_configure = bnxt_dev_configure_op,
4190 .dev_start = bnxt_dev_start_op,
4191 .dev_stop = bnxt_dev_stop_op,
4192 .dev_set_link_up = bnxt_dev_set_link_up_op,
4193 .dev_set_link_down = bnxt_dev_set_link_down_op,
4194 .stats_get = bnxt_stats_get_op,
4195 .stats_reset = bnxt_stats_reset_op,
4196 .rx_queue_setup = bnxt_rx_queue_setup_op,
4197 .rx_queue_release = bnxt_rx_queue_release_op,
4198 .tx_queue_setup = bnxt_tx_queue_setup_op,
4199 .tx_queue_release = bnxt_tx_queue_release_op,
4200 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4201 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4202 .reta_update = bnxt_reta_update_op,
4203 .reta_query = bnxt_reta_query_op,
4204 .rss_hash_update = bnxt_rss_hash_update_op,
4205 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4206 .link_update = bnxt_link_update_op,
4207 .promiscuous_enable = bnxt_promiscuous_enable_op,
4208 .promiscuous_disable = bnxt_promiscuous_disable_op,
4209 .allmulticast_enable = bnxt_allmulticast_enable_op,
4210 .allmulticast_disable = bnxt_allmulticast_disable_op,
4211 .mac_addr_add = bnxt_mac_addr_add_op,
4212 .mac_addr_remove = bnxt_mac_addr_remove_op,
4213 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4214 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4215 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4216 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4217 .vlan_filter_set = bnxt_vlan_filter_set_op,
4218 .vlan_offload_set = bnxt_vlan_offload_set_op,
4219 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4220 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4221 .mtu_set = bnxt_mtu_set_op,
4222 .mac_addr_set = bnxt_set_default_mac_addr_op,
4223 .xstats_get = bnxt_dev_xstats_get_op,
4224 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4225 .xstats_reset = bnxt_dev_xstats_reset_op,
4226 .fw_version_get = bnxt_fw_version_get,
4227 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4228 .rxq_info_get = bnxt_rxq_info_get_op,
4229 .txq_info_get = bnxt_txq_info_get_op,
4230 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4231 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4232 .dev_led_on = bnxt_dev_led_on_op,
4233 .dev_led_off = bnxt_dev_led_off_op,
4234 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4235 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4236 .rx_queue_count = bnxt_rx_queue_count_op,
4237 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4238 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4239 .rx_queue_start = bnxt_rx_queue_start,
4240 .rx_queue_stop = bnxt_rx_queue_stop,
4241 .tx_queue_start = bnxt_tx_queue_start,
4242 .tx_queue_stop = bnxt_tx_queue_stop,
4243 .filter_ctrl = bnxt_filter_ctrl_op,
4244 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4245 .get_eeprom_length = bnxt_get_eeprom_length_op,
4246 .get_eeprom = bnxt_get_eeprom_op,
4247 .set_eeprom = bnxt_set_eeprom_op,
4248 .timesync_enable = bnxt_timesync_enable,
4249 .timesync_disable = bnxt_timesync_disable,
4250 .timesync_read_time = bnxt_timesync_read_time,
4251 .timesync_write_time = bnxt_timesync_write_time,
4252 .timesync_adjust_time = bnxt_timesync_adjust_time,
4253 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4254 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4257 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4261 /* Only pre-map the reset GRC registers using window 3 */
4262 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4263 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4265 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4270 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4272 struct bnxt_error_recovery_info *info = bp->recovery_info;
4273 uint32_t reg_base = 0xffffffff;
4276 /* Only pre-map the monitoring GRC registers using window 2 */
4277 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4278 uint32_t reg = info->status_regs[i];
4280 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4283 if (reg_base == 0xffffffff)
4284 reg_base = reg & 0xfffff000;
4285 if ((reg & 0xfffff000) != reg_base)
4288 /* Use mask 0xffc as the Lower 2 bits indicates
4289 * address space location
4291 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4295 if (reg_base == 0xffffffff)
4298 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4299 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4304 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4306 struct bnxt_error_recovery_info *info = bp->recovery_info;
4307 uint32_t delay = info->delay_after_reset[index];
4308 uint32_t val = info->reset_reg_val[index];
4309 uint32_t reg = info->reset_reg[index];
4310 uint32_t type, offset;
4312 type = BNXT_FW_STATUS_REG_TYPE(reg);
4313 offset = BNXT_FW_STATUS_REG_OFF(reg);
4316 case BNXT_FW_STATUS_REG_TYPE_CFG:
4317 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4319 case BNXT_FW_STATUS_REG_TYPE_GRC:
4320 offset = bnxt_map_reset_regs(bp, offset);
4321 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4323 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4324 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4327 /* wait on a specific interval of time until core reset is complete */
4329 rte_delay_ms(delay);
4332 static void bnxt_dev_cleanup(struct bnxt *bp)
4334 bnxt_set_hwrm_link_config(bp, false);
4335 bp->link_info->link_up = 0;
4336 if (bp->eth_dev->data->dev_started)
4337 bnxt_dev_stop_op(bp->eth_dev);
4339 bnxt_uninit_resources(bp, true);
4342 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4344 struct rte_eth_dev *dev = bp->eth_dev;
4345 struct rte_vlan_filter_conf *vfc;
4349 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4350 vfc = &dev->data->vlan_filter_conf;
4351 vidx = vlan_id / 64;
4352 vbit = vlan_id % 64;
4354 /* Each bit corresponds to a VLAN id */
4355 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4356 rc = bnxt_add_vlan_filter(bp, vlan_id);
4365 static int bnxt_restore_mac_filters(struct bnxt *bp)
4367 struct rte_eth_dev *dev = bp->eth_dev;
4368 struct rte_eth_dev_info dev_info;
4369 struct rte_ether_addr *addr;
4375 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4378 rc = bnxt_dev_info_get_op(dev, &dev_info);
4382 /* replay MAC address configuration */
4383 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4384 addr = &dev->data->mac_addrs[i];
4386 /* skip zero address */
4387 if (rte_is_zero_ether_addr(addr))
4391 pool_mask = dev->data->mac_pool_sel[i];
4394 if (pool_mask & 1ULL) {
4395 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4401 } while (pool_mask);
4407 static int bnxt_restore_filters(struct bnxt *bp)
4409 struct rte_eth_dev *dev = bp->eth_dev;
4412 if (dev->data->all_multicast) {
4413 ret = bnxt_allmulticast_enable_op(dev);
4417 if (dev->data->promiscuous) {
4418 ret = bnxt_promiscuous_enable_op(dev);
4423 ret = bnxt_restore_mac_filters(bp);
4427 ret = bnxt_restore_vlan_filters(bp);
4428 /* TODO restore other filters as well */
4432 static void bnxt_dev_recover(void *arg)
4434 struct bnxt *bp = arg;
4435 int timeout = bp->fw_reset_max_msecs;
4438 /* Clear Error flag so that device re-init should happen */
4439 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4442 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4445 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4446 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4447 } while (rc && timeout);
4450 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4454 rc = bnxt_init_resources(bp, true);
4457 "Failed to initialize resources after reset\n");
4460 /* clear reset flag as the device is initialized now */
4461 bp->flags &= ~BNXT_FLAG_FW_RESET;
4463 rc = bnxt_dev_start_op(bp->eth_dev);
4465 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4469 rc = bnxt_restore_filters(bp);
4473 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4476 bnxt_dev_stop_op(bp->eth_dev);
4478 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4479 bnxt_uninit_resources(bp, false);
4480 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4483 void bnxt_dev_reset_and_resume(void *arg)
4485 struct bnxt *bp = arg;
4488 bnxt_dev_cleanup(bp);
4490 bnxt_wait_for_device_shutdown(bp);
4492 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4493 bnxt_dev_recover, (void *)bp);
4495 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4498 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4500 struct bnxt_error_recovery_info *info = bp->recovery_info;
4501 uint32_t reg = info->status_regs[index];
4502 uint32_t type, offset, val = 0;
4504 type = BNXT_FW_STATUS_REG_TYPE(reg);
4505 offset = BNXT_FW_STATUS_REG_OFF(reg);
4508 case BNXT_FW_STATUS_REG_TYPE_CFG:
4509 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4511 case BNXT_FW_STATUS_REG_TYPE_GRC:
4512 offset = info->mapped_status_regs[index];
4514 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4515 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4523 static int bnxt_fw_reset_all(struct bnxt *bp)
4525 struct bnxt_error_recovery_info *info = bp->recovery_info;
4529 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4530 /* Reset through master function driver */
4531 for (i = 0; i < info->reg_array_cnt; i++)
4532 bnxt_write_fw_reset_reg(bp, i);
4533 /* Wait for time specified by FW after triggering reset */
4534 rte_delay_ms(info->master_func_wait_period_after_reset);
4535 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4536 /* Reset with the help of Kong processor */
4537 rc = bnxt_hwrm_fw_reset(bp);
4539 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4545 static void bnxt_fw_reset_cb(void *arg)
4547 struct bnxt *bp = arg;
4548 struct bnxt_error_recovery_info *info = bp->recovery_info;
4551 /* Only Master function can do FW reset */
4552 if (bnxt_is_master_func(bp) &&
4553 bnxt_is_recovery_enabled(bp)) {
4554 rc = bnxt_fw_reset_all(bp);
4556 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4561 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4562 * EXCEPTION_FATAL_ASYNC event to all the functions
4563 * (including MASTER FUNC). After receiving this Async, all the active
4564 * drivers should treat this case as FW initiated recovery
4566 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4567 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4568 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4570 /* To recover from error */
4571 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4576 /* Driver should poll FW heartbeat, reset_counter with the frequency
4577 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4578 * When the driver detects heartbeat stop or change in reset_counter,
4579 * it has to trigger a reset to recover from the error condition.
4580 * A “master PF” is the function who will have the privilege to
4581 * initiate the chimp reset. The master PF will be elected by the
4582 * firmware and will be notified through async message.
4584 static void bnxt_check_fw_health(void *arg)
4586 struct bnxt *bp = arg;
4587 struct bnxt_error_recovery_info *info = bp->recovery_info;
4588 uint32_t val = 0, wait_msec;
4590 if (!info || !bnxt_is_recovery_enabled(bp) ||
4591 is_bnxt_in_error(bp))
4594 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4595 if (val == info->last_heart_beat)
4598 info->last_heart_beat = val;
4600 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4601 if (val != info->last_reset_counter)
4604 info->last_reset_counter = val;
4606 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4607 bnxt_check_fw_health, (void *)bp);
4611 /* Stop DMA to/from device */
4612 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4613 bp->flags |= BNXT_FLAG_FW_RESET;
4615 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4617 if (bnxt_is_master_func(bp))
4618 wait_msec = info->master_func_wait_period;
4620 wait_msec = info->normal_func_wait_period;
4622 rte_eal_alarm_set(US_PER_MS * wait_msec,
4623 bnxt_fw_reset_cb, (void *)bp);
4626 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4628 uint32_t polling_freq;
4630 if (!bnxt_is_recovery_enabled(bp))
4633 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4636 polling_freq = bp->recovery_info->driver_polling_freq;
4638 rte_eal_alarm_set(US_PER_MS * polling_freq,
4639 bnxt_check_fw_health, (void *)bp);
4640 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4643 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4645 if (!bnxt_is_recovery_enabled(bp))
4648 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4649 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4652 static bool bnxt_vf_pciid(uint16_t device_id)
4654 switch (device_id) {
4655 case BROADCOM_DEV_ID_57304_VF:
4656 case BROADCOM_DEV_ID_57406_VF:
4657 case BROADCOM_DEV_ID_5731X_VF:
4658 case BROADCOM_DEV_ID_5741X_VF:
4659 case BROADCOM_DEV_ID_57414_VF:
4660 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4661 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4662 case BROADCOM_DEV_ID_58802_VF:
4663 case BROADCOM_DEV_ID_57500_VF1:
4664 case BROADCOM_DEV_ID_57500_VF2:
4672 static bool bnxt_thor_device(uint16_t device_id)
4674 switch (device_id) {
4675 case BROADCOM_DEV_ID_57508:
4676 case BROADCOM_DEV_ID_57504:
4677 case BROADCOM_DEV_ID_57502:
4678 case BROADCOM_DEV_ID_57508_MF1:
4679 case BROADCOM_DEV_ID_57504_MF1:
4680 case BROADCOM_DEV_ID_57502_MF1:
4681 case BROADCOM_DEV_ID_57508_MF2:
4682 case BROADCOM_DEV_ID_57504_MF2:
4683 case BROADCOM_DEV_ID_57502_MF2:
4684 case BROADCOM_DEV_ID_57500_VF1:
4685 case BROADCOM_DEV_ID_57500_VF2:
4693 bool bnxt_stratus_device(struct bnxt *bp)
4695 uint16_t device_id = bp->pdev->id.device_id;
4697 switch (device_id) {
4698 case BROADCOM_DEV_ID_STRATUS_NIC:
4699 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4700 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4708 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4710 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4711 struct bnxt *bp = eth_dev->data->dev_private;
4713 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4714 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4715 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4716 if (!bp->bar0 || !bp->doorbell_base) {
4717 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4721 bp->eth_dev = eth_dev;
4727 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4728 struct bnxt_ctx_pg_info *ctx_pg,
4733 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4734 const struct rte_memzone *mz = NULL;
4735 char mz_name[RTE_MEMZONE_NAMESIZE];
4736 rte_iova_t mz_phys_addr;
4737 uint64_t valid_bits = 0;
4744 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4746 rmem->page_size = BNXT_PAGE_SIZE;
4747 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4748 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4749 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4751 valid_bits = PTU_PTE_VALID;
4753 if (rmem->nr_pages > 1) {
4754 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4755 "bnxt_ctx_pg_tbl%s_%x_%d",
4756 suffix, idx, bp->eth_dev->data->port_id);
4757 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4758 mz = rte_memzone_lookup(mz_name);
4760 mz = rte_memzone_reserve_aligned(mz_name,
4764 RTE_MEMZONE_SIZE_HINT_ONLY |
4765 RTE_MEMZONE_IOVA_CONTIG,
4771 memset(mz->addr, 0, mz->len);
4772 mz_phys_addr = mz->iova;
4774 rmem->pg_tbl = mz->addr;
4775 rmem->pg_tbl_map = mz_phys_addr;
4776 rmem->pg_tbl_mz = mz;
4779 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4780 suffix, idx, bp->eth_dev->data->port_id);
4781 mz = rte_memzone_lookup(mz_name);
4783 mz = rte_memzone_reserve_aligned(mz_name,
4787 RTE_MEMZONE_SIZE_HINT_ONLY |
4788 RTE_MEMZONE_IOVA_CONTIG,
4794 memset(mz->addr, 0, mz->len);
4795 mz_phys_addr = mz->iova;
4797 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4798 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4799 rmem->dma_arr[i] = mz_phys_addr + sz;
4801 if (rmem->nr_pages > 1) {
4802 if (i == rmem->nr_pages - 2 &&
4803 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4804 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4805 else if (i == rmem->nr_pages - 1 &&
4806 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4807 valid_bits |= PTU_PTE_LAST;
4809 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4815 if (rmem->vmem_size)
4816 rmem->vmem = (void **)mz->addr;
4817 rmem->dma_arr[0] = mz_phys_addr;
4821 static void bnxt_free_ctx_mem(struct bnxt *bp)
4825 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4828 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4829 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4830 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4831 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4832 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4833 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4834 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4835 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4836 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4837 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4838 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4840 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4841 if (bp->ctx->tqm_mem[i])
4842 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4849 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4851 #define min_t(type, x, y) ({ \
4852 type __min1 = (x); \
4853 type __min2 = (y); \
4854 __min1 < __min2 ? __min1 : __min2; })
4856 #define max_t(type, x, y) ({ \
4857 type __max1 = (x); \
4858 type __max2 = (y); \
4859 __max1 > __max2 ? __max1 : __max2; })
4861 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4863 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4865 struct bnxt_ctx_pg_info *ctx_pg;
4866 struct bnxt_ctx_mem_info *ctx;
4867 uint32_t mem_size, ena, entries;
4868 uint32_t entries_sp, min;
4871 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4873 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4877 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4880 ctx_pg = &ctx->qp_mem;
4881 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4882 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4883 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4887 ctx_pg = &ctx->srq_mem;
4888 ctx_pg->entries = ctx->srq_max_l2_entries;
4889 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4890 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4894 ctx_pg = &ctx->cq_mem;
4895 ctx_pg->entries = ctx->cq_max_l2_entries;
4896 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4897 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4901 ctx_pg = &ctx->vnic_mem;
4902 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4903 ctx->vnic_max_ring_table_entries;
4904 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4905 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4909 ctx_pg = &ctx->stat_mem;
4910 ctx_pg->entries = ctx->stat_max_entries;
4911 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4912 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4916 min = ctx->tqm_min_entries_per_ring;
4918 entries_sp = ctx->qp_max_l2_entries +
4919 ctx->vnic_max_vnic_entries +
4920 2 * ctx->qp_min_qp1_entries + min;
4921 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4923 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4924 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4925 entries = clamp_t(uint32_t, entries, min,
4926 ctx->tqm_max_entries_per_ring);
4927 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4928 ctx_pg = ctx->tqm_mem[i];
4929 ctx_pg->entries = i ? entries : entries_sp;
4930 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4931 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4934 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4937 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4938 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4941 "Failed to configure context mem: rc = %d\n", rc);
4943 ctx->flags |= BNXT_CTX_FLAG_INITED;
4948 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4950 struct rte_pci_device *pci_dev = bp->pdev;
4951 char mz_name[RTE_MEMZONE_NAMESIZE];
4952 const struct rte_memzone *mz = NULL;
4953 uint32_t total_alloc_len;
4954 rte_iova_t mz_phys_addr;
4956 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4959 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4960 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4961 pci_dev->addr.bus, pci_dev->addr.devid,
4962 pci_dev->addr.function, "rx_port_stats");
4963 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4964 mz = rte_memzone_lookup(mz_name);
4966 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4967 sizeof(struct rx_port_stats_ext) + 512);
4969 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4972 RTE_MEMZONE_SIZE_HINT_ONLY |
4973 RTE_MEMZONE_IOVA_CONTIG);
4977 memset(mz->addr, 0, mz->len);
4978 mz_phys_addr = mz->iova;
4980 bp->rx_mem_zone = (const void *)mz;
4981 bp->hw_rx_port_stats = mz->addr;
4982 bp->hw_rx_port_stats_map = mz_phys_addr;
4984 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4985 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4986 pci_dev->addr.bus, pci_dev->addr.devid,
4987 pci_dev->addr.function, "tx_port_stats");
4988 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4989 mz = rte_memzone_lookup(mz_name);
4991 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4992 sizeof(struct tx_port_stats_ext) + 512);
4994 mz = rte_memzone_reserve(mz_name,
4998 RTE_MEMZONE_SIZE_HINT_ONLY |
4999 RTE_MEMZONE_IOVA_CONTIG);
5003 memset(mz->addr, 0, mz->len);
5004 mz_phys_addr = mz->iova;
5006 bp->tx_mem_zone = (const void *)mz;
5007 bp->hw_tx_port_stats = mz->addr;
5008 bp->hw_tx_port_stats_map = mz_phys_addr;
5009 bp->flags |= BNXT_FLAG_PORT_STATS;
5011 /* Display extended statistics if FW supports it */
5012 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5013 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5014 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5017 bp->hw_rx_port_stats_ext = (void *)
5018 ((uint8_t *)bp->hw_rx_port_stats +
5019 sizeof(struct rx_port_stats));
5020 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5021 sizeof(struct rx_port_stats);
5022 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5024 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5025 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5026 bp->hw_tx_port_stats_ext = (void *)
5027 ((uint8_t *)bp->hw_tx_port_stats +
5028 sizeof(struct tx_port_stats));
5029 bp->hw_tx_port_stats_ext_map =
5030 bp->hw_tx_port_stats_map +
5031 sizeof(struct tx_port_stats);
5032 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5038 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5040 struct bnxt *bp = eth_dev->data->dev_private;
5043 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5044 RTE_ETHER_ADDR_LEN *
5047 if (eth_dev->data->mac_addrs == NULL) {
5048 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5052 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5056 /* Generate a random MAC address, if none was assigned by PF */
5057 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5058 bnxt_eth_hw_addr_random(bp->mac_addr);
5060 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5061 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5062 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5064 rc = bnxt_hwrm_set_mac(bp);
5069 /* Copy the permanent MAC from the FUNC_QCAPS response */
5070 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5075 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5079 /* MAC is already configured in FW */
5080 if (BNXT_HAS_DFLT_MAC_SET(bp))
5083 /* Restore the old MAC configured */
5084 rc = bnxt_hwrm_set_mac(bp);
5086 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5091 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5096 #define ALLOW_FUNC(x) \
5098 uint32_t arg = (x); \
5099 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5100 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5103 /* Forward all requests if firmware is new enough */
5104 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5105 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5106 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5107 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5109 PMD_DRV_LOG(WARNING,
5110 "Firmware too old for VF mailbox functionality\n");
5111 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5115 * The following are used for driver cleanup. If we disallow these,
5116 * VF drivers can't clean up cleanly.
5118 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5119 ALLOW_FUNC(HWRM_VNIC_FREE);
5120 ALLOW_FUNC(HWRM_RING_FREE);
5121 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5122 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5123 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5124 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5125 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5126 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5130 bnxt_get_svif(uint16_t port_id, bool func_svif,
5131 enum bnxt_ulp_intf_type type)
5133 struct rte_eth_dev *eth_dev;
5136 eth_dev = &rte_eth_devices[port_id];
5137 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5138 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5142 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5145 eth_dev = vfr->parent_dev;
5148 bp = eth_dev->data->dev_private;
5150 return func_svif ? bp->func_svif : bp->port_svif;
5154 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5156 struct rte_eth_dev *eth_dev;
5157 struct bnxt_vnic_info *vnic;
5160 eth_dev = &rte_eth_devices[port];
5161 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5162 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5166 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5167 return vfr->dflt_vnic_id;
5169 eth_dev = vfr->parent_dev;
5172 bp = eth_dev->data->dev_private;
5174 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5176 return vnic->fw_vnic_id;
5180 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5182 struct rte_eth_dev *eth_dev;
5185 eth_dev = &rte_eth_devices[port];
5186 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5187 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5191 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5194 eth_dev = vfr->parent_dev;
5197 bp = eth_dev->data->dev_private;
5202 enum bnxt_ulp_intf_type
5203 bnxt_get_interface_type(uint16_t port)
5205 struct rte_eth_dev *eth_dev;
5208 eth_dev = &rte_eth_devices[port];
5209 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5210 return BNXT_ULP_INTF_TYPE_VF_REP;
5212 bp = eth_dev->data->dev_private;
5214 return BNXT_ULP_INTF_TYPE_PF;
5215 else if (BNXT_VF_IS_TRUSTED(bp))
5216 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5217 else if (BNXT_VF(bp))
5218 return BNXT_ULP_INTF_TYPE_VF;
5220 return BNXT_ULP_INTF_TYPE_INVALID;
5224 bnxt_get_phy_port_id(uint16_t port_id)
5226 struct bnxt_vf_representor *vfr;
5227 struct rte_eth_dev *eth_dev;
5230 eth_dev = &rte_eth_devices[port_id];
5231 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5232 vfr = eth_dev->data->dev_private;
5236 eth_dev = vfr->parent_dev;
5239 bp = eth_dev->data->dev_private;
5241 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5245 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5247 struct rte_eth_dev *eth_dev;
5250 eth_dev = &rte_eth_devices[port_id];
5251 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5252 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5256 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5257 return vfr->fw_fid - 1;
5259 eth_dev = vfr->parent_dev;
5262 bp = eth_dev->data->dev_private;
5264 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5268 bnxt_get_vport(uint16_t port_id)
5270 return (1 << bnxt_get_phy_port_id(port_id));
5273 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5275 struct bnxt_error_recovery_info *info = bp->recovery_info;
5278 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5279 memset(info, 0, sizeof(*info));
5283 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5286 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5289 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5291 bp->recovery_info = info;
5294 static void bnxt_check_fw_status(struct bnxt *bp)
5298 if (!(bp->recovery_info &&
5299 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5302 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5303 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5304 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5308 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5310 struct bnxt_error_recovery_info *info = bp->recovery_info;
5311 uint32_t status_loc;
5314 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5315 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5316 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5317 BNXT_GRCP_WINDOW_2_BASE +
5318 offsetof(struct hcomm_status,
5320 /* If the signature is absent, then FW does not support this feature */
5321 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5322 HCOMM_STATUS_SIGNATURE_VAL)
5326 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5330 bp->recovery_info = info;
5332 memset(info, 0, sizeof(*info));
5335 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5336 BNXT_GRCP_WINDOW_2_BASE +
5337 offsetof(struct hcomm_status,
5340 /* Only pre-map the FW health status GRC register */
5341 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5344 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5345 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5346 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5348 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5349 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5351 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5356 static int bnxt_init_fw(struct bnxt *bp)
5363 rc = bnxt_map_hcomm_fw_status_reg(bp);
5367 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5369 bnxt_check_fw_status(bp);
5373 rc = bnxt_hwrm_func_reset(bp);
5377 rc = bnxt_hwrm_vnic_qcaps(bp);
5381 rc = bnxt_hwrm_queue_qportcfg(bp);
5385 /* Get the MAX capabilities for this function.
5386 * This function also allocates context memory for TQM rings and
5387 * informs the firmware about this allocated backing store memory.
5389 rc = bnxt_hwrm_func_qcaps(bp);
5393 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5397 bnxt_hwrm_port_mac_qcfg(bp);
5399 bnxt_hwrm_parent_pf_qcfg(bp);
5401 bnxt_hwrm_port_phy_qcaps(bp);
5403 bnxt_alloc_error_recovery_info(bp);
5404 /* Get the adapter error recovery support info */
5405 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5407 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5409 bnxt_hwrm_port_led_qcaps(bp);
5415 bnxt_init_locks(struct bnxt *bp)
5419 err = pthread_mutex_init(&bp->flow_lock, NULL);
5421 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5425 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5427 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5431 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5435 rc = bnxt_init_fw(bp);
5439 if (!reconfig_dev) {
5440 rc = bnxt_setup_mac_addr(bp->eth_dev);
5444 rc = bnxt_restore_dflt_mac(bp);
5449 bnxt_config_vf_req_fwd(bp);
5451 rc = bnxt_hwrm_func_driver_register(bp);
5453 PMD_DRV_LOG(ERR, "Failed to register driver");
5458 if (bp->pdev->max_vfs) {
5459 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5461 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5465 rc = bnxt_hwrm_allocate_pf_only(bp);
5468 "Failed to allocate PF resources");
5474 rc = bnxt_alloc_mem(bp, reconfig_dev);
5478 rc = bnxt_setup_int(bp);
5482 rc = bnxt_request_int(bp);
5486 rc = bnxt_init_ctx_mem(bp);
5488 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5492 rc = bnxt_init_locks(bp);
5500 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5501 const char *value, void *opaque_arg)
5503 struct bnxt *bp = opaque_arg;
5504 unsigned long truflow;
5507 if (!value || !opaque_arg) {
5509 "Invalid parameter passed to truflow devargs.\n");
5513 truflow = strtoul(value, &end, 10);
5514 if (end == NULL || *end != '\0' ||
5515 (truflow == ULONG_MAX && errno == ERANGE)) {
5517 "Invalid parameter passed to truflow devargs.\n");
5521 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5523 "Invalid value passed to truflow devargs.\n");
5527 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5528 if (BNXT_TRUFLOW_EN(bp))
5529 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5535 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5536 const char *value, void *opaque_arg)
5538 struct bnxt *bp = opaque_arg;
5539 unsigned long flow_xstat;
5542 if (!value || !opaque_arg) {
5544 "Invalid parameter passed to flow_xstat devarg.\n");
5548 flow_xstat = strtoul(value, &end, 10);
5549 if (end == NULL || *end != '\0' ||
5550 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5552 "Invalid parameter passed to flow_xstat devarg.\n");
5556 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5558 "Invalid value passed to flow_xstat devarg.\n");
5562 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5563 if (BNXT_FLOW_XSTATS_EN(bp))
5564 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5570 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5571 const char *value, void *opaque_arg)
5573 struct bnxt *bp = opaque_arg;
5574 unsigned long max_num_kflows;
5577 if (!value || !opaque_arg) {
5579 "Invalid parameter passed to max_num_kflows devarg.\n");
5583 max_num_kflows = strtoul(value, &end, 10);
5584 if (end == NULL || *end != '\0' ||
5585 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5587 "Invalid parameter passed to max_num_kflows devarg.\n");
5591 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5593 "Invalid value passed to max_num_kflows devarg.\n");
5597 bp->max_num_kflows = max_num_kflows;
5598 if (bp->max_num_kflows)
5599 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5606 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5608 struct rte_kvargs *kvlist;
5610 if (devargs == NULL)
5613 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5618 * Handler for "truflow" devarg.
5619 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5621 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5622 bnxt_parse_devarg_truflow, bp);
5625 * Handler for "flow_xstat" devarg.
5626 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5628 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5629 bnxt_parse_devarg_flow_xstat, bp);
5632 * Handler for "max_num_kflows" devarg.
5633 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5635 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5636 bnxt_parse_devarg_max_num_kflows, bp);
5638 rte_kvargs_free(kvlist);
5641 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5645 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5646 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5649 "Failed to alloc switch domain: %d\n", rc);
5652 "Switch domain allocated %d\n",
5653 bp->switch_domain_id);
5660 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5662 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5663 static int version_printed;
5667 if (version_printed++ == 0)
5668 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5670 eth_dev->dev_ops = &bnxt_dev_ops;
5671 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5672 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5675 * For secondary processes, we don't initialise any further
5676 * as primary has already done this work.
5678 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5681 rte_eth_copy_pci_info(eth_dev, pci_dev);
5683 bp = eth_dev->data->dev_private;
5685 /* Parse dev arguments passed on when starting the DPDK application. */
5686 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5688 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5690 if (bnxt_vf_pciid(pci_dev->id.device_id))
5691 bp->flags |= BNXT_FLAG_VF;
5693 if (bnxt_thor_device(pci_dev->id.device_id))
5694 bp->flags |= BNXT_FLAG_THOR_CHIP;
5696 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5697 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5698 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5699 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5700 bp->flags |= BNXT_FLAG_STINGRAY;
5702 rc = bnxt_init_board(eth_dev);
5705 "Failed to initialize board rc: %x\n", rc);
5709 rc = bnxt_alloc_pf_info(bp);
5713 rc = bnxt_alloc_link_info(bp);
5717 rc = bnxt_alloc_parent_info(bp);
5721 rc = bnxt_alloc_hwrm_resources(bp);
5724 "Failed to allocate hwrm resource rc: %x\n", rc);
5727 rc = bnxt_alloc_leds_info(bp);
5731 rc = bnxt_alloc_cos_queues(bp);
5735 rc = bnxt_init_resources(bp, false);
5739 rc = bnxt_alloc_stats_mem(bp);
5743 bnxt_alloc_switch_domain(bp);
5745 /* Pass the information to the rte_eth_dev_close() that it should also
5746 * release the private port resources.
5748 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5751 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5752 pci_dev->mem_resource[0].phys_addr,
5753 pci_dev->mem_resource[0].addr);
5758 bnxt_dev_uninit(eth_dev);
5763 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5772 ctx->dma = RTE_BAD_IOVA;
5773 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5776 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5778 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5779 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5780 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5781 bp->flow_stat->max_fc,
5784 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5785 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5786 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5787 bp->flow_stat->max_fc,
5790 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5791 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5792 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5794 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5795 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5796 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5798 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5799 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5800 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5802 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5803 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5804 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5807 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5809 bnxt_unregister_fc_ctx_mem(bp);
5811 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5812 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5813 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5814 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5817 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5819 if (BNXT_FLOW_XSTATS_EN(bp))
5820 bnxt_uninit_fc_ctx_mem(bp);
5824 bnxt_free_error_recovery_info(struct bnxt *bp)
5826 rte_free(bp->recovery_info);
5827 bp->recovery_info = NULL;
5828 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5832 bnxt_uninit_locks(struct bnxt *bp)
5834 pthread_mutex_destroy(&bp->flow_lock);
5835 pthread_mutex_destroy(&bp->def_cp_lock);
5837 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5841 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5846 bnxt_free_mem(bp, reconfig_dev);
5847 bnxt_hwrm_func_buf_unrgtr(bp);
5848 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5849 bp->flags &= ~BNXT_FLAG_REGISTERED;
5850 bnxt_free_ctx_mem(bp);
5851 if (!reconfig_dev) {
5852 bnxt_free_hwrm_resources(bp);
5853 bnxt_free_error_recovery_info(bp);
5856 bnxt_uninit_ctx_mem(bp);
5858 bnxt_uninit_locks(bp);
5859 bnxt_free_flow_stats_info(bp);
5860 bnxt_free_rep_info(bp);
5861 rte_free(bp->ptp_cfg);
5867 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5869 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5872 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5874 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5875 bnxt_dev_close_op(eth_dev);
5880 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5882 struct bnxt *bp = eth_dev->data->dev_private;
5883 struct rte_eth_dev *vf_rep_eth_dev;
5889 for (i = 0; i < bp->num_reps; i++) {
5890 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5891 if (!vf_rep_eth_dev)
5893 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5895 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5900 static void bnxt_free_rep_info(struct bnxt *bp)
5902 rte_free(bp->rep_info);
5903 bp->rep_info = NULL;
5904 rte_free(bp->cfa_code_map);
5905 bp->cfa_code_map = NULL;
5908 static int bnxt_init_rep_info(struct bnxt *bp)
5915 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5916 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5918 if (!bp->rep_info) {
5919 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5922 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5923 sizeof(*bp->cfa_code_map) *
5924 BNXT_MAX_CFA_CODE, 0);
5925 if (!bp->cfa_code_map) {
5926 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5927 bnxt_free_rep_info(bp);
5931 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5932 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5934 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5936 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5937 bnxt_free_rep_info(bp);
5943 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5944 struct rte_eth_devargs eth_da,
5945 struct rte_eth_dev *backing_eth_dev)
5947 struct rte_eth_dev *vf_rep_eth_dev;
5948 char name[RTE_ETH_NAME_MAX_LEN];
5949 struct bnxt *backing_bp;
5953 num_rep = eth_da.nb_representor_ports;
5954 if (num_rep > BNXT_MAX_VF_REPS) {
5955 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5956 num_rep, BNXT_MAX_VF_REPS);
5960 if (num_rep > RTE_MAX_ETHPORTS) {
5962 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5963 num_rep, RTE_MAX_ETHPORTS);
5967 backing_bp = backing_eth_dev->data->dev_private;
5969 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5971 "Not a PF or trusted VF. No Representor support\n");
5972 /* Returning an error is not an option.
5973 * Applications are not handling this correctly
5978 if (bnxt_init_rep_info(backing_bp))
5981 for (i = 0; i < num_rep; i++) {
5982 struct bnxt_vf_representor representor = {
5983 .vf_id = eth_da.representor_ports[i],
5984 .switch_domain_id = backing_bp->switch_domain_id,
5985 .parent_dev = backing_eth_dev
5988 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5989 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5990 representor.vf_id, BNXT_MAX_VF_REPS);
5994 /* representor port net_bdf_port */
5995 snprintf(name, sizeof(name), "net_%s_representor_%d",
5996 pci_dev->device.name, eth_da.representor_ports[i]);
5998 ret = rte_eth_dev_create(&pci_dev->device, name,
5999 sizeof(struct bnxt_vf_representor),
6001 bnxt_vf_representor_init,
6005 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6006 if (!vf_rep_eth_dev) {
6007 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6008 " for VF-Rep: %s.", name);
6009 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6013 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6015 backing_bp->num_reps++;
6017 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6018 "representor %s.", name);
6019 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6026 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6027 struct rte_pci_device *pci_dev)
6029 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6030 struct rte_eth_dev *backing_eth_dev;
6034 if (pci_dev->device.devargs) {
6035 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6041 num_rep = eth_da.nb_representor_ports;
6042 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6045 /* We could come here after first level of probe is already invoked
6046 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6047 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6049 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6050 if (backing_eth_dev == NULL) {
6051 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6052 sizeof(struct bnxt),
6053 eth_dev_pci_specific_init, pci_dev,
6054 bnxt_dev_init, NULL);
6056 if (ret || !num_rep)
6059 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6062 /* probe representor ports now */
6063 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6068 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6070 struct rte_eth_dev *eth_dev;
6072 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6074 return 0; /* Invoked typically only by OVS-DPDK, by the
6075 * time it comes here the eth_dev is already
6076 * deleted by rte_eth_dev_close(), so returning
6077 * +ve value will at least help in proper cleanup
6080 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6081 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6082 return rte_eth_dev_destroy(eth_dev,
6083 bnxt_vf_representor_uninit);
6085 return rte_eth_dev_destroy(eth_dev,
6088 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6092 static struct rte_pci_driver bnxt_rte_pmd = {
6093 .id_table = bnxt_pci_id_map,
6094 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6095 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6098 .probe = bnxt_pci_probe,
6099 .remove = bnxt_pci_remove,
6103 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6105 if (strcmp(dev->device->driver->name, drv->driver.name))
6111 bool is_bnxt_supported(struct rte_eth_dev *dev)
6113 return is_device_supported(dev, &bnxt_rte_pmd);
6116 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6117 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6118 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6119 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");