1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* This is limitation of libibverbs: in length variable type is u16. */
13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
16 struct mlx5_devx_mkey_attr {
21 uint32_t log_entity_size;
23 uint32_t relaxed_ordering:1;
24 struct mlx5_klm *klm_array;
28 /* HCA qos attributes. */
29 struct mlx5_hca_qos_attr {
30 uint32_t sup:1; /* Whether QOS is supported. */
31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
32 uint32_t packet_pacing:1; /* Packet pacing is supported. */
33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
34 uint32_t flow_meter_reg_share:1;
35 /* Whether reg_c share is supported. */
36 uint8_t log_max_flow_meter;
37 /* Power of the maximum supported meters. */
38 uint8_t flow_meter_reg_c_ids;
39 /* Bitmap of the reg_Cs available for flow meter to use. */
43 struct mlx5_hca_vdpa_attr {
44 uint8_t virtio_queue_type;
46 uint32_t desc_tunnel_offload_type:1;
47 uint32_t eth_frame_offload_type:1;
48 uint32_t virtio_version_1_0:1;
53 uint32_t event_mode:3;
54 uint32_t log_doorbell_stride:5;
55 uint32_t log_doorbell_bar_size:5;
56 uint32_t queue_counters_valid:1;
57 uint32_t max_num_virtio_queues;
62 uint64_t doorbell_bar_offset;
65 /* HCA supports this number of time periods for LRO. */
66 #define MLX5_LRO_NUM_SUPP_PERIODS 4
69 struct mlx5_hca_attr {
70 uint32_t eswitch_manager:1;
71 uint32_t flow_counters_dump:1;
72 uint32_t log_max_rqt_size:5;
73 uint32_t parse_graph_flex_node:1;
74 uint8_t flow_counter_bulk_alloc_bitmap;
75 uint32_t eth_net_offloads:1;
77 uint32_t wqe_vlan_insert:1;
78 uint32_t wqe_inline_mode:2;
79 uint32_t vport_inline_mode:3;
80 uint32_t tunnel_stateless_geneve_rx:1;
81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
82 uint32_t tunnel_stateless_gtp:1;
84 uint32_t tunnel_lro_gre:1;
85 uint32_t tunnel_lro_vxlan:1;
86 uint32_t lro_max_msg_sz_mode:2;
87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
88 uint32_t flex_parser_protocols;
90 uint32_t log_max_hairpin_queues:5;
91 uint32_t log_max_hairpin_wq_data_sz:5;
92 uint32_t log_max_hairpin_num_packets:5;
94 uint32_t relaxed_ordering_write:1;
95 uint32_t relaxed_ordering_read:1;
96 uint32_t access_register_user:1;
97 uint32_t wqe_index_ignore:1;
98 uint32_t cross_channel:1;
99 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
100 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
101 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
102 uint32_t scatter_fcs_w_decap_disable:1;
104 uint32_t regexp_num_of_engines;
105 uint32_t log_max_ft_sampler_num:8;
106 struct mlx5_hca_qos_attr qos;
107 struct mlx5_hca_vdpa_attr vdpa;
110 struct mlx5_devx_wq_attr {
112 uint32_t wq_signature:1;
113 uint32_t end_padding_mode:2;
115 uint32_t hds_skip_first_sge:1;
116 uint32_t log2_hds_buf_size:3;
117 uint32_t page_offset:5;
120 uint32_t uar_page:24;
124 uint32_t log_wq_stride:4;
125 uint32_t log_wq_pg_sz:5;
126 uint32_t log_wq_sz:5;
127 uint32_t dbr_umem_valid:1;
128 uint32_t wq_umem_valid:1;
129 uint32_t log_hairpin_num_packets:5;
130 uint32_t log_hairpin_data_sz:5;
131 uint32_t single_wqe_log_num_of_strides:4;
132 uint32_t two_byte_shift_en:1;
133 uint32_t single_stride_log_num_of_bytes:3;
134 uint32_t dbr_umem_id;
136 uint64_t wq_umem_offset;
139 /* Create RQ attributes structure, used by create RQ operation. */
140 struct mlx5_devx_create_rq_attr {
142 uint32_t delay_drop_en:1;
143 uint32_t scatter_fcs:1;
145 uint32_t mem_rq_type:4;
147 uint32_t flush_in_error_en:1;
149 uint32_t user_index:24;
151 uint32_t counter_set_id:8;
153 struct mlx5_devx_wq_attr wq_attr;
156 /* Modify RQ attributes structure, used by modify RQ operation. */
157 struct mlx5_devx_modify_rq_attr {
159 uint32_t rq_state:4; /* Current RQ state. */
160 uint32_t state:4; /* Required RQ state. */
161 uint32_t scatter_fcs:1;
163 uint32_t counter_set_id:8;
164 uint32_t hairpin_peer_sq:24;
165 uint32_t hairpin_peer_vhca:16;
166 uint64_t modify_bitmask;
167 uint32_t lwm:16; /* Contained WQ lwm. */
170 struct mlx5_rx_hash_field_select {
171 uint32_t l3_prot_type:1;
172 uint32_t l4_prot_type:1;
173 uint32_t selected_fields:30;
176 /* TIR attributes structure, used by TIR operations. */
177 struct mlx5_devx_tir_attr {
178 uint32_t disp_type:4;
179 uint32_t lro_timeout_period_usecs:16;
180 uint32_t lro_enable_mask:4;
181 uint32_t lro_max_msg_sz:8;
182 uint32_t inline_rqn:24;
183 uint32_t rx_hash_symmetric:1;
184 uint32_t tunneled_offload_en:1;
185 uint32_t indirect_table:24;
186 uint32_t rx_hash_fn:4;
187 uint32_t self_lb_block:2;
188 uint32_t transport_domain:24;
189 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
190 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
191 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
194 /* RQT attributes structure, used by RQT operations. */
195 struct mlx5_devx_rqt_attr {
197 uint32_t rqt_max_size:16;
198 uint32_t rqt_actual_size:16;
202 /* TIS attributes structure. */
203 struct mlx5_devx_tis_attr {
204 uint32_t strict_lag_tx_port_affinity:1;
206 uint32_t lag_tx_port_affinity:4;
208 uint32_t transport_domain:24;
211 /* SQ attributes structure, used by SQ create operation. */
212 struct mlx5_devx_create_sq_attr {
214 uint32_t cd_master:1;
216 uint32_t flush_in_error_en:1;
217 uint32_t allow_multi_pkt_send_wqe:1;
218 uint32_t min_wqe_inline_mode:3;
221 uint32_t allow_swp:1;
224 uint32_t static_sq_wq:1;
225 uint32_t user_index:24;
227 uint32_t packet_pacing_rate_limit_index:16;
228 uint32_t tis_lst_sz:16;
230 struct mlx5_devx_wq_attr wq_attr;
233 /* SQ attributes structure, used by SQ modify operation. */
234 struct mlx5_devx_modify_sq_attr {
237 uint32_t hairpin_peer_rq:24;
238 uint32_t hairpin_peer_vhca:16;
242 /* CQ attributes structure, used by CQ operations. */
243 struct mlx5_devx_cq_attr {
244 uint32_t q_umem_valid:1;
245 uint32_t db_umem_valid:1;
246 uint32_t use_first_only:1;
247 uint32_t overrun_ignore:1;
248 uint32_t cqe_comp_en:1;
249 uint32_t mini_cqe_res_format:2;
251 uint32_t log_cq_size:5;
252 uint32_t log_page_size:5;
253 uint32_t uar_page_id;
255 uint64_t q_umem_offset;
257 uint64_t db_umem_offset;
262 /* Virtq attributes structure, used by VIRTQ operations. */
263 struct mlx5_devx_virtq_attr {
264 uint16_t hw_available_index;
265 uint16_t hw_used_index;
268 uint32_t virtio_version_1_0:1;
273 uint32_t event_mode:3;
275 uint32_t dirty_bitmap_dump_enable:1;
276 uint32_t dirty_bitmap_mkey;
277 uint32_t dirty_bitmap_size;
280 uint32_t queue_index;
282 uint32_t counters_obj_id;
283 uint64_t dirty_bitmap_addr;
287 uint64_t available_addr;
296 struct mlx5_devx_qp_attr {
298 uint32_t uar_index:24;
300 uint32_t log_page_size:5;
301 uint32_t rq_size:17; /* Must be power of 2. */
302 uint32_t log_rq_stride:3;
303 uint32_t sq_size:17; /* Must be power of 2. */
304 uint32_t dbr_umem_valid:1;
305 uint32_t dbr_umem_id;
306 uint64_t dbr_address;
308 uint64_t wq_umem_offset;
311 struct mlx5_devx_virtio_q_couners_attr {
312 uint64_t received_desc;
313 uint64_t completed_desc;
315 uint32_t bad_desc_errors;
316 uint32_t exceed_max_chain;
317 uint32_t invalid_buffer;
321 * graph flow match sample attributes structure,
322 * used by flex parser operations.
324 struct mlx5_devx_match_sample_attr {
325 uint32_t flow_match_sample_en:1;
326 uint32_t flow_match_sample_field_offset:16;
327 uint32_t flow_match_sample_offset_mode:4;
328 uint32_t flow_match_sample_field_offset_mask;
329 uint32_t flow_match_sample_field_offset_shift:4;
330 uint32_t flow_match_sample_field_base_offset:8;
331 uint32_t flow_match_sample_tunnel_mode:3;
332 uint32_t flow_match_sample_field_id;
335 /* graph node arc attributes structure, used by flex parser operations. */
336 struct mlx5_devx_graph_arc_attr {
337 uint32_t compare_condition_value:16;
338 uint32_t start_inner_tunnel:1;
339 uint32_t arc_parse_graph_node:8;
340 uint32_t parse_graph_node_handle;
343 /* Maximal number of samples per graph node. */
344 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
346 /* Maximal number of input/output arcs per graph node. */
347 #define MLX5_GRAPH_NODE_ARC_NUM 8
349 /* parse graph node attributes structure, used by flex parser operations. */
350 struct mlx5_devx_graph_node_attr {
351 uint32_t modify_field_select;
352 uint32_t header_length_mode:4;
353 uint32_t header_length_base_value:16;
354 uint32_t header_length_field_shift:4;
355 uint32_t header_length_field_offset:16;
356 uint32_t header_length_field_mask;
357 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
358 uint32_t next_header_field_offset:16;
359 uint32_t next_header_field_size:5;
360 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
361 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
364 /* mlx5_devx_cmds.c */
367 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
370 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
372 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
373 int clear, uint32_t n_counters,
374 uint64_t *pkts, uint64_t *bytes,
375 uint32_t mkey, void *addr,
379 int mlx5_devx_cmd_query_hca_attr(void *ctx,
380 struct mlx5_hca_attr *attr);
382 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
383 struct mlx5_devx_mkey_attr *attr);
385 int mlx5_devx_get_out_command_status(void *out);
387 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
390 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
391 struct mlx5_devx_create_rq_attr *rq_attr,
394 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
395 struct mlx5_devx_modify_rq_attr *rq_attr);
397 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
398 struct mlx5_devx_tir_attr *tir_attr);
400 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
401 struct mlx5_devx_rqt_attr *rqt_attr);
403 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
404 struct mlx5_devx_create_sq_attr *sq_attr);
406 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
407 struct mlx5_devx_modify_sq_attr *sq_attr);
409 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
410 struct mlx5_devx_tis_attr *tis_attr);
412 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
414 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
417 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
418 struct mlx5_devx_cq_attr *attr);
420 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
421 struct mlx5_devx_virtq_attr *attr);
423 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
424 struct mlx5_devx_virtq_attr *attr);
426 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
427 struct mlx5_devx_virtq_attr *attr);
429 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
430 struct mlx5_devx_qp_attr *attr);
432 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
433 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
435 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
436 struct mlx5_devx_rqt_attr *rqt_attr);
438 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
439 uint32_t ids[], uint32_t num);
442 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
443 struct mlx5_devx_graph_node_attr *data);
446 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
447 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
449 * Create virtio queue counters object DevX API.
455 * The DevX object created, NULL otherwise and rte_errno is set.
458 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
461 * Query virtio queue counters object using DevX API.
463 * @param[in] couners_obj
464 * Pointer to virtq object structure.
465 * @param [in/out] attr
466 * Pointer to virtio queue counters attributes structure.
469 * 0 on success, a negative errno value otherwise and rte_errno is set.
472 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
473 struct mlx5_devx_virtio_q_couners_attr *attr);
475 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */