1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
6 #ifndef __CHELSIO_COMMON_H
7 #define __CHELSIO_COMMON_H
9 #include "../cxgbe_compat.h"
12 #include "t4_chip_type.h"
13 #include "t4fw_interface.h"
15 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
17 #define T4_MEMORY_WRITE 0
18 #define T4_MEMORY_READ 1
21 MAX_NPORTS = 4, /* max # of ports */
25 T5_REGMAP_SIZE = (332 * 1024),
29 MEMWIN0_APERTURE = 2048,
30 MEMWIN0_BASE = 0x1b800,
33 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
35 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
37 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
40 u64 tx_octets; /* total # of octets in good frames */
41 u64 tx_frames; /* all good frames */
42 u64 tx_bcast_frames; /* all broadcast frames */
43 u64 tx_mcast_frames; /* all multicast frames */
44 u64 tx_ucast_frames; /* all unicast frames */
45 u64 tx_error_frames; /* all error frames */
47 u64 tx_frames_64; /* # of Tx frames in a particular range */
49 u64 tx_frames_128_255;
50 u64 tx_frames_256_511;
51 u64 tx_frames_512_1023;
52 u64 tx_frames_1024_1518;
53 u64 tx_frames_1519_max;
55 u64 tx_drop; /* # of dropped Tx frames */
56 u64 tx_pause; /* # of transmitted pause frames */
57 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
58 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
59 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
60 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
61 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
62 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
63 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
64 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
66 u64 rx_octets; /* total # of octets in good frames */
67 u64 rx_frames; /* all good frames */
68 u64 rx_bcast_frames; /* all broadcast frames */
69 u64 rx_mcast_frames; /* all multicast frames */
70 u64 rx_ucast_frames; /* all unicast frames */
71 u64 rx_too_long; /* # of frames exceeding MTU */
72 u64 rx_jabber; /* # of jabber frames */
73 u64 rx_fcs_err; /* # of received frames with bad FCS */
74 u64 rx_len_err; /* # of received frames with length error */
75 u64 rx_symbol_err; /* symbol errors */
76 u64 rx_runt; /* # of short frames */
78 u64 rx_frames_64; /* # of Rx frames in a particular range */
80 u64 rx_frames_128_255;
81 u64 rx_frames_256_511;
82 u64 rx_frames_512_1023;
83 u64 rx_frames_1024_1518;
84 u64 rx_frames_1519_max;
86 u64 rx_pause; /* # of received pause frames */
87 u64 rx_ppp0; /* # of received PPP prio 0 frames */
88 u64 rx_ppp1; /* # of received PPP prio 1 frames */
89 u64 rx_ppp2; /* # of received PPP prio 2 frames */
90 u64 rx_ppp3; /* # of received PPP prio 3 frames */
91 u64 rx_ppp4; /* # of received PPP prio 4 frames */
92 u64 rx_ppp5; /* # of received PPP prio 5 frames */
93 u64 rx_ppp6; /* # of received PPP prio 6 frames */
94 u64 rx_ppp7; /* # of received PPP prio 7 frames */
96 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
97 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
98 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
99 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
100 u64 rx_trunc0; /* buffer-group 0 truncated packets */
101 u64 rx_trunc1; /* buffer-group 1 truncated packets */
102 u64 rx_trunc2; /* buffer-group 2 truncated packets */
103 u64 rx_trunc3; /* buffer-group 3 truncated packets */
105 u64 rx_tp_tnl_cong_drops[NCHAN]; /* TP frame drops due to congestion */
109 u32 hps; /* host page size for our PF/VF */
110 u32 eq_qpp; /* egress queues/page for our PF/VF */
111 u32 iq_qpp; /* egress queues/page for our PF/VF */
115 unsigned int ntxchan; /* # of Tx channels */
116 unsigned int tre; /* log2 of core clocks per TP tick */
117 unsigned int dack_re; /* DACK timer resolution */
118 unsigned int la_mask; /* what events are recorded by TP LA */
119 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
121 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
123 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
125 /* cached TP_OUT_CONFIG compressed error vector
126 * and passing outer header info for encapsulated packets.
131 * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
132 * subset of the set of fields which may be present in the Compressed
133 * Filter Tuple portion of filters and TCP TCB connections. The
134 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
135 * Since a variable number of fields may or may not be present, their
136 * shifted field positions within the Compressed Filter Tuple may
137 * vary, or not even be present if the field isn't selected in
138 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
139 * places we store their offsets here, or a -1 if the field isn't
150 u64 hash_filter_mask;
160 uint32_t vpd_cap_addr;
166 * Firmware device log.
168 struct devlog_params {
169 u32 memtype; /* which memory (EDC0, EDC1, MC) */
170 u32 start; /* start of log in firmware memory */
171 u32 size; /* size of log */
174 struct arch_specific_params {
176 u8 cng_ch_bits_log; /* congestion channel map bits width */
184 * Global Receive Side Scaling (RSS) parameters in host-native format.
187 unsigned int mode; /* RSS mode */
190 unsigned int synmapen:1; /* SYN Map Enable */
191 unsigned int syn4tupenipv6:1; /* en 4-tuple IPv6 SYNs hash */
192 unsigned int syn2tupenipv6:1; /* en 2-tuple IPv6 SYNs hash */
193 unsigned int syn4tupenipv4:1; /* en 4-tuple IPv4 SYNs hash */
194 unsigned int syn2tupenipv4:1; /* en 2-tuple IPv4 SYNs hash */
195 unsigned int ofdmapen:1; /* Offload Map Enable */
196 unsigned int tnlmapen:1; /* Tunnel Map Enable */
197 unsigned int tnlalllookup:1; /* Tunnel All Lookup */
198 unsigned int hashtoeplitz:1; /* use Toeplitz hash */
204 * Maximum resources provisioned for a PCI PF.
206 struct pf_resources {
207 unsigned int neq; /* N egress Qs */
208 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
209 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
213 * Maximum resources provisioned for a PCI VF.
215 struct vf_resources {
216 unsigned int nvi; /* N virtual interfaces */
217 unsigned int neq; /* N egress Qs */
218 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
219 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
220 unsigned int niq; /* N ingress Qs */
221 unsigned int tc; /* PCI-E traffic class */
222 unsigned int pmask; /* port access rights mask */
223 unsigned int nexactf; /* N exact MPS filters */
224 unsigned int r_caps; /* read capabilities */
225 unsigned int wx_caps; /* write/execute capabilities */
228 struct adapter_params {
229 struct sge_params sge;
231 struct vpd_params vpd;
232 struct pci_params pci;
233 struct devlog_params devlog;
234 struct rss_params rss;
235 struct pf_resources pfres;
236 struct vf_resources vfres;
237 enum pcie_memwin drv_memwin;
239 unsigned int sf_size; /* serial flash size in bytes */
240 unsigned int sf_nsec; /* # of flash sectors */
242 unsigned int fw_vers;
243 unsigned int bs_vers;
244 unsigned int tp_vers;
245 unsigned int er_vers;
247 unsigned short mtus[NMTUS];
248 unsigned short a_wnd[NCCTRL_WIN];
249 unsigned short b_wnd[NCCTRL_WIN];
251 unsigned int mc_size; /* MC memory size */
252 unsigned int cim_la_size;
254 unsigned char nports; /* # of ethernet ports */
255 unsigned char portvec;
257 unsigned char hash_filter;
259 enum chip_type chip; /* chip code */
260 struct arch_specific_params arch; /* chip specific params */
262 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
263 u8 filter2_wr_support; /* FW support for FILTER2_WR */
264 u32 viid_smt_extn_support:1; /* FW returns vin and smt index */
265 u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */
266 u8 vi_enable_rx; /* FW support for enable/disable VI Rx at runtime */
268 u16 rawf_start; /* FW supports RAW MAC match-all filters */
272 /* Firmware Port Capabilities types.
275 u32 pcaps; /* Physically supported link caps */
276 u32 acaps; /* Advertised link caps */
278 u32 link_caps; /* Current link caps */
279 u32 admin_caps; /* Admin configured link caps */
281 u8 mdio_addr; /* Address of the PHY */
282 u8 port_type; /* Firmware port type */
283 u8 mod_type; /* Firmware module type */
285 u8 link_ok; /* Link up? */
286 u8 link_down_rc; /* Link down reason */
291 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
293 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
295 int attempts, int delay, u32 *valp);
297 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
298 int polarity, int attempts, int delay)
300 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
304 static inline int is_pf4(struct adapter *adap)
306 return adap->pf == 4;
309 #define for_each_port(adapter, iter) \
310 for (iter = 0; iter < (adapter)->params.nports; ++iter)
312 static inline int is_hashfilter(const struct adapter *adap)
314 return adap->params.hash_filter;
317 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
318 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
319 unsigned int mask, unsigned int val);
320 void t4_intr_enable(struct adapter *adapter);
321 void t4_intr_disable(struct adapter *adapter);
322 int t4_link_l1cfg_core(struct port_info *pi, u32 caps, u8 sleep_ok);
323 static inline int t4_link_l1cfg(struct port_info *pi, u32 caps)
325 return t4_link_l1cfg_core(pi, caps, true);
328 static inline int t4_link_l1cfg_ns(struct port_info *pi, u32 caps)
330 return t4_link_l1cfg_core(pi, caps, false);
333 int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps);
334 int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx,
335 u8 pause_rx, u32 *new_caps);
336 int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser,
337 u8 fec_none, u32 *new_caps);
338 unsigned int t4_fwcap_to_speed(u32 caps);
339 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
340 const unsigned short *alpha, const unsigned short *beta);
341 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
342 enum dev_master master, enum dev_state *state);
343 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
344 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
345 int t4vf_fw_reset(struct adapter *adap);
346 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
347 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
348 int t4vf_get_vfres(struct adapter *adap);
349 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
350 unsigned int cache_line_size,
351 enum chip_type chip_compat);
352 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
353 unsigned int cache_line_size);
354 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
355 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
356 unsigned int vf, unsigned int nparams, const u32 *params,
358 int t4vf_query_params(struct adapter *adap, unsigned int nparams,
359 const u32 *params, u32 *vals);
360 int t4vf_get_dev_params(struct adapter *adap);
361 int t4vf_get_vpd_params(struct adapter *adap);
362 int t4vf_get_rss_glb_config(struct adapter *adap);
363 int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
364 const u32 *params, const u32 *vals);
365 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
366 unsigned int pf, unsigned int vf,
367 unsigned int nparams, const u32 *params,
368 const u32 *val, int timeout);
369 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
370 unsigned int vf, unsigned int nparams, const u32 *params,
372 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
373 unsigned int port, unsigned int pf, unsigned int vf,
374 unsigned int nmac, u8 *mac, unsigned int *rss_size,
375 unsigned int portfunc, unsigned int idstype,
377 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
378 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
379 unsigned int *rss_size, u8 *vivild, u8 *vin);
380 int t4_free_vi(struct adapter *adap, unsigned int mbox,
381 unsigned int pf, unsigned int vf,
383 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
384 int mtu, int promisc, int all_multi, int bcast, int vlanex,
386 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
387 const u8 *addr, const u8 *mask, unsigned int idx,
388 u8 lookup_type, u8 port_id, bool sleep_ok);
389 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
390 const u8 *addr, const u8 *mask, unsigned int idx,
391 u8 lookup_type, u8 port_id, bool sleep_ok);
392 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
393 int idx, const u8 *addr, bool persist, bool add_smt);
394 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
395 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
396 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
397 bool rx_en, bool tx_en);
398 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
399 unsigned int pf, unsigned int vf, unsigned int iqid,
400 unsigned int fl0id, unsigned int fl1id);
401 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
402 unsigned int vf, unsigned int iqtype, unsigned int iqid,
403 unsigned int fl0id, unsigned int fl1id);
404 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
405 unsigned int vf, unsigned int eqid);
406 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
407 unsigned int vf, unsigned int eqid);
409 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
411 return adap->params.vpd.cclk / 1000;
414 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
417 return (us * adap->params.vpd.cclk) / 1000;
420 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
423 /* add Core Clock / 2 to round ticks to nearest uS */
424 return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
425 adapter->params.vpd.cclk);
428 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
429 int size, void *rpl, bool sleep_ok, int timeout);
430 int t4_wr_mbox_meat(struct adapter *adap, int mbox,
431 const void __attribute__((__may_alias__)) *cmd, int size,
432 void *rpl, bool sleep_ok);
434 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
435 const void *cmd, int size, void *rpl,
438 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
442 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
444 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
447 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
450 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
453 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
456 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
458 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
461 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
464 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
467 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
471 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
472 unsigned int data_reg, u32 *vals, unsigned int nregs,
473 unsigned int start_idx);
474 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
475 unsigned int data_reg, const u32 *vals,
476 unsigned int nregs, unsigned int start_idx);
478 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
479 int t4_get_pfres(struct adapter *adapter);
480 int t4_read_flash(struct adapter *adapter, unsigned int addr,
481 unsigned int nwords, u32 *data, int byte_oriented);
482 int t4_flash_cfg_addr(struct adapter *adapter);
483 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
484 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
485 const char *t4_get_port_type_description(enum fw_port_type port_type);
486 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
487 void t4vf_get_port_stats(struct adapter *adapter, int pidx,
488 struct port_stats *p);
489 void t4_get_port_stats_offset(struct adapter *adap, int idx,
490 struct port_stats *stats,
491 struct port_stats *offset);
492 void t4_clr_port_stats(struct adapter *adap, int idx);
493 void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,
494 u8 mdio_addr, u8 port_type, u8 mod_type);
495 void t4_reset_link_config(struct adapter *adap, int idx);
496 int t4_get_version_info(struct adapter *adapter);
497 void t4_dump_version_info(struct adapter *adapter);
498 int t4_get_flash_params(struct adapter *adapter);
499 int t4_get_chip_type(struct adapter *adap, int ver);
500 int t4_prep_adapter(struct adapter *adapter);
501 int t4vf_prep_adapter(struct adapter *adapter);
502 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
503 int t4vf_port_init(struct adapter *adap);
504 int t4_init_rss_mode(struct adapter *adap, int mbox);
505 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
506 int start, int n, const u16 *rspq, unsigned int nrspq);
507 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
508 unsigned int flags, unsigned int defq);
509 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
510 u64 *flags, unsigned int *defq);
511 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
512 unsigned int start_index, unsigned int rw);
513 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
514 void t4_read_rss_key(struct adapter *adap, u32 *key);
516 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
517 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
518 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
519 unsigned int *pbar2_qid);
521 int t4_init_sge_params(struct adapter *adapter);
522 int t4_init_tp_params(struct adapter *adap);
523 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
524 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
525 unsigned int t4_get_regs_len(struct adapter *adap);
526 unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
527 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
528 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
529 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
530 int t4_seeprom_wp(struct adapter *adapter, int enable);
531 int t4_memory_rw_addr(struct adapter *adap, int win,
532 u32 addr, u32 len, void *hbuf, int dir);
533 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
534 u32 len, void *hbuf, int dir);
535 static inline int t4_memory_rw(struct adapter *adap, int win,
536 int mtype, u32 maddr, u32 len,
539 return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
541 #endif /* __CHELSIO_COMMON_H */