1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
5 # common flags to all aarch64 builds, with lowest priority
7 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
8 # to determine the best threshold in code. Refer to notes in source file
9 # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
10 ['RTE_ARCH_ARM64_MEMCPY', false],
11 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
12 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
13 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
14 # unless there are strong reasons.
15 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
16 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
17 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
19 ['RTE_NET_FM10K', false],
20 ['RTE_NET_AVP', false],
22 ['RTE_SCHED_VECTOR', false],
23 ['RTE_ARM_USE_WFE', false],
24 ['RTE_ARCH_ARM64', true],
25 ['RTE_CACHE_LINE_SIZE', 128]
28 ## Part numbers are specific to Arm implementers
29 # implementer specific aarch64 flags have middle priority
30 # (will overwrite common flags)
31 # part number specific aarch64 flags have the highest priority
32 # (will overwrite both common and implementer specific flags)
33 implementer_generic = {
34 'description': 'Generic armv8',
36 ['RTE_MACHINE', '"armv8a"'],
37 ['RTE_USE_C11_MEM_MODEL', true],
38 ['RTE_MAX_LCORE', 256],
39 ['RTE_MAX_NUMA_NODES', 4]
41 'part_number_config': {
42 'generic': {'machine_args': ['-march=armv8-a+crc',
47 part_number_config_arm = {
48 '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
49 '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
50 '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
51 '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
52 '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
53 '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
54 '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
56 'machine_args': ['-march=armv8.2-a+crypto',
59 ['RTE_MACHINE', '"neoverse-n1"'],
60 ['RTE_ARM_FEATURE_ATOMICS', true],
61 ['RTE_MAX_MEM_MB', 1048576],
66 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
68 ['RTE_MACHINE', '"neoverse-n2"'],
69 ['RTE_ARM_FEATURE_ATOMICS', true],
77 ['RTE_MACHINE', '"armv8a"'],
78 ['RTE_USE_C11_MEM_MODEL', true],
79 ['RTE_CACHE_LINE_SIZE', 64],
80 ['RTE_MAX_LCORE', 16],
81 ['RTE_MAX_NUMA_NODES', 1]
83 'part_number_config': part_number_config_arm
86 flags_part_number_thunderx = [
87 ['RTE_MACHINE', '"thunderx"'],
88 ['RTE_USE_C11_MEM_MODEL', false]
90 implementer_cavium = {
91 'description': 'Cavium',
93 ['RTE_MAX_VFIO_GROUPS', 128],
94 ['RTE_MAX_LCORE', 96],
95 ['RTE_MAX_NUMA_NODES', 2]
97 'part_number_config': {
99 'machine_args': ['-mcpu=thunderxt88'],
100 'flags': flags_part_number_thunderx
103 'machine_args': ['-mcpu=thunderxt81'],
104 'flags': flags_part_number_thunderx
107 'machine_args': ['-mcpu=thunderxt83'],
108 'flags': flags_part_number_thunderx
111 'machine_args': ['-march=armv8.1-a+crc+crypto',
112 '-mcpu=thunderx2t99'],
114 ['RTE_MACHINE', '"thunderx2"'],
115 ['RTE_ARM_FEATURE_ATOMICS', true],
116 ['RTE_USE_C11_MEM_MODEL', true],
117 ['RTE_CACHE_LINE_SIZE', 64],
118 ['RTE_MAX_LCORE', 256]
122 'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
125 ['RTE_MACHINE', '"octeontx2"'],
126 ['RTE_ARM_FEATURE_ATOMICS', true],
127 ['RTE_USE_C11_MEM_MODEL', true],
128 ['RTE_EAL_IGB_UIO', false],
129 ['RTE_MAX_LCORE', 36],
130 ['RTE_MAX_NUMA_NODES', 1]
136 implementer_ampere = {
137 'description': 'Ampere Computing',
139 ['RTE_MACHINE', '"emag"'],
140 ['RTE_CACHE_LINE_SIZE', 64],
141 ['RTE_MAX_LCORE', 32],
142 ['RTE_MAX_NUMA_NODES', 1]
144 'part_number_config': {
145 '0x0': {'machine_args': ['-march=armv8-a+crc+crypto',
150 implementer_qualcomm = {
151 'description': 'Qualcomm',
153 ['RTE_MACHINE', '"armv8a"'],
154 ['RTE_USE_C11_MEM_MODEL', true],
155 ['RTE_CACHE_LINE_SIZE', 64],
156 ['RTE_MAX_LCORE', 64],
157 ['RTE_MAX_NUMA_NODES', 1]
159 'part_number_config': {
160 '0xc00': {'machine_args': ['-march=armv8-a+crc']}
164 implementer_marvell = {
165 'description': 'Marvell ARMADA',
167 ['RTE_MACHINE', '"armv8a"'],
168 ['RTE_CACHE_LINE_SIZE', 64],
169 ['RTE_MAX_LCORE', 16],
170 ['RTE_MAX_NUMA_NODES', 1]
172 'part_number_config': part_number_config_arm
176 'description': 'NXP DPAA',
178 ['RTE_MACHINE', '"dpaa"'],
179 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
180 ['RTE_USE_C11_MEM_MODEL', true],
181 ['RTE_CACHE_LINE_SIZE', 64],
182 ['RTE_MAX_LCORE', 16],
183 ['RTE_MAX_NUMA_NODES', 1]
185 'part_number_config': part_number_config_arm
188 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
190 'generic': implementer_generic,
191 '0x41': implementer_arm,
192 '0x43': implementer_cavium,
193 '0x50': implementer_ampere,
194 '0x51': implementer_qualcomm,
195 '0x56': implementer_marvell,
196 'dpaa': implementer_dpaa
199 dpdk_conf.set('RTE_ARCH_ARM', 1)
200 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
202 if dpdk_conf.get('RTE_ARCH_32')
204 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
205 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
206 # the minimum architecture supported, armv7-a, needs the following,
207 machine_args += '-mfpu=neon'
210 if not meson.is_cross_build()
211 if machine == 'default'
213 implementer_id = 'generic'
214 part_number = 'generic'
217 # The script returns ['Implementer', 'Variant', 'Architecture',
218 # 'Primary Part number', 'Revision']
219 detect_vendor = find_program(join_paths(
220 meson.current_source_dir(), 'armv8_machine.py'))
221 cmd = run_command(detect_vendor.path())
222 if cmd.returncode() == 0
223 cmd_output = cmd.stdout().to_lower().strip().split(' ')
224 implementer_id = cmd_output[0]
225 part_number = cmd_output[3]
227 error('Error when getting Arm Implementer ID and part number.')
232 implementer_id = meson.get_cross_property('implementer_id')
233 part_number = meson.get_cross_property('part_number')
236 if implementers.has_key(implementer_id)
237 implementer_config = implementers[implementer_id]
239 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
240 'Please add support for it or use the generic ' +
241 '(-Dmachine=generic) build.')
244 message('Arm implementer: ' + implementer_config['description'])
245 message('Arm part number: ' + part_number)
247 part_number_config = implementer_config['part_number_config']
248 if part_number_config.has_key(part_number)
249 # use the specified part_number machine args if found
250 part_number_config = part_number_config[part_number]
252 # unknown part number
253 error('Unsupported part number @0@ of implementer @1@. '
254 .format(part_number, implementer_id) +
255 'Please add support for it or use the generic ' +
256 '(-Dmachine=generic) build.')
259 # use default flags with implementer flags
260 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', [])
262 # apply supported machine args
263 machine_args = [] # Clear previous machine args
264 foreach flag: part_number_config['machine_args']
265 if cc.has_argument(flag)
271 foreach flag: dpdk_flags
273 dpdk_conf.set(flag[0], flag[1])
277 message('Using machine args: @0@'.format(machine_args))
279 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
280 cc.get_define('__aarch64__', args: machine_args) != '')
281 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
284 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
285 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
288 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
289 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
290 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']