config/arm/meson.build

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright(c) 2017 Intel Corporation.
   3 # Copyright(c) 2017 Cavium, Inc
   4
   5 arm_force_native_march = false
   6
   7 flags_common = [
   8         # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
   9         # to determine the best threshold in code. Refer to notes in source file
  10         # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
  11         ['RTE_ARCH_ARM64_MEMCPY', false],
  12         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
  13         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
  14         # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
  15         # strong reasons.
  16         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
  17         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
  18         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
  19
  20         ['RTE_NET_FM10K', false],
  21         ['RTE_NET_AVP', false],
  22
  23         ['RTE_SCHED_VECTOR', false],
  24         ['RTE_ARM_USE_WFE', false],
  25 ]
  26
  27 flags_implementer_generic = [
  28         ['RTE_MACHINE', '"armv8a"'],
  29         ['RTE_MAX_LCORE', 256],
  30         ['RTE_USE_C11_MEM_MODEL', true],
  31         ['RTE_CACHE_LINE_SIZE', 128]]
  32 flags_implementer_arm = [
  33         ['RTE_MACHINE', '"armv8a"'],
  34         ['RTE_MAX_LCORE', 16],
  35         ['RTE_USE_C11_MEM_MODEL', true],
  36         ['RTE_CACHE_LINE_SIZE', 64]]
  37 flags_implementer_cavium = [
  38         ['RTE_CACHE_LINE_SIZE', 128],
  39         ['RTE_MAX_NUMA_NODES', 2],
  40         ['RTE_MAX_LCORE', 96],
  41         ['RTE_MAX_VFIO_GROUPS', 128]]
  42 flags_implementer_dpaa = [
  43         ['RTE_MACHINE', '"dpaa"'],
  44         ['RTE_USE_C11_MEM_MODEL', true],
  45         ['RTE_CACHE_LINE_SIZE', 64],
  46         ['RTE_MAX_NUMA_NODES', 1],
  47         ['RTE_MAX_LCORE', 16],
  48         ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
  49 flags_implementer_emag = [
  50         ['RTE_MACHINE', '"emag"'],
  51         ['RTE_CACHE_LINE_SIZE', 64],
  52         ['RTE_MAX_NUMA_NODES', 1],
  53         ['RTE_MAX_LCORE', 32]]
  54 flags_implementer_armada = [
  55         ['RTE_MACHINE', '"armv8a"'],
  56         ['RTE_CACHE_LINE_SIZE', 64],
  57         ['RTE_MAX_NUMA_NODES', 1],
  58         ['RTE_MAX_LCORE', 16]]
  59
  60 flags_part_number_thunderx = [
  61         ['RTE_MACHINE', '"thunderx"'],
  62         ['RTE_USE_C11_MEM_MODEL', false]]
  63 flags_part_number_thunderx2 = [
  64         ['RTE_MACHINE', '"thunderx2"'],
  65         ['RTE_CACHE_LINE_SIZE', 64],
  66         ['RTE_MAX_NUMA_NODES', 2],
  67         ['RTE_MAX_LCORE', 256],
  68         ['RTE_ARM_FEATURE_ATOMICS', true],
  69         ['RTE_USE_C11_MEM_MODEL', true]]
  70 flags_part_number_octeontx2 = [
  71         ['RTE_MACHINE', '"octeontx2"'],
  72         ['RTE_MAX_NUMA_NODES', 1],
  73         ['RTE_MAX_LCORE', 36],
  74         ['RTE_ARM_FEATURE_ATOMICS', true],
  75         ['RTE_EAL_IGB_UIO', false],
  76         ['RTE_USE_C11_MEM_MODEL', true]]
  77 flags_part_number_n1generic = [
  78         ['RTE_MACHINE', '"neoverse-n1"'],
  79         ['RTE_MAX_LCORE', 64],
  80         ['RTE_CACHE_LINE_SIZE', 64],
  81         ['RTE_ARM_FEATURE_ATOMICS', true],
  82         ['RTE_USE_C11_MEM_MODEL', true],
  83         ['RTE_MAX_MEM_MB', 1048576],
  84         ['RTE_MAX_NUMA_NODES', 1],
  85         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
  86         ['RTE_LIBRTE_VHOST_NUMA', false]]
  87 flags_part_number_n2generic = [
  88         ['RTE_MACHINE', '"neoverse-n2"'],
  89         ['RTE_MAX_LCORE', 64],
  90         ['RTE_CACHE_LINE_SIZE', 64],
  91         ['RTE_ARM_FEATURE_ATOMICS', true],
  92         ['RTE_USE_C11_MEM_MODEL', true],
  93         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
  94         ['RTE_LIBRTE_VHOST_NUMA', false]]
  95
  96 part_number_config_arm = [
  97         ['generic', ['-march=armv8-a+crc', '-moutline-atomics']],
  98         ['native', ['-march=native']],
  99         ['0xd03', ['-mcpu=cortex-a53']],
 100         ['0xd04', ['-mcpu=cortex-a35']],
 101         ['0xd07', ['-mcpu=cortex-a57']],
 102         ['0xd08', ['-mcpu=cortex-a72']],
 103         ['0xd09', ['-mcpu=cortex-a73']],
 104         ['0xd0a', ['-mcpu=cortex-a75']],
 105         ['0xd0b', ['-mcpu=cortex-a76']],
 106         ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic],
 107         ['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_part_number_n2generic]]
 108
 109 part_number_config_cavium = [
 110         ['generic', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
 111         ['native', ['-march=native']],
 112         ['0xa1', ['-mcpu=thunderxt88'], flags_part_number_thunderx],
 113         ['0xa2', ['-mcpu=thunderxt81'], flags_part_number_thunderx],
 114         ['0xa3', ['-mcpu=thunderxt83'], flags_part_number_thunderx],
 115         ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_part_number_thunderx2],
 116         ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2]]
 117
 118 part_number_config_emag = [
 119         ['generic', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
 120         ['native', ['-march=native']]]
 121
 122 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 123 implementer_generic = ['Generic armv8', flags_implementer_generic, part_number_config_arm]
 124 implementer_0x41 = ['Arm', flags_implementer_arm, part_number_config_arm]
 125 implementer_0x43 = ['Cavium', flags_implementer_cavium, part_number_config_cavium]
 126 implementer_0x50 = ['Ampere Computing', flags_implementer_emag, part_number_config_emag]
 127 implementer_0x56 = ['Marvell ARMADA', flags_implementer_armada, part_number_config_arm]
 128 implementer_dpaa = ['NXP DPAA', flags_implementer_dpaa, part_number_config_arm]
 129
 130 dpdk_conf.set('RTE_ARCH_ARM', 1)
 131 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
 132
 133 if dpdk_conf.get('RTE_ARCH_32')
 134         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
 135         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
 136         # the minimum architecture supported, armv7-a, needs the following,
 137         # mk/machine/armv7a/rte.vars.mk sets it too
 138         machine_args += '-mfpu=neon'
 139 else
 140         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
 141         dpdk_conf.set('RTE_ARCH_ARM64', 1)
 142
 143         implementer_id = 'generic'
 144         machine_args = [] # Clear previous machine args
 145         if machine == 'default' and not meson.is_cross_build()
 146                 implementer_config = implementer_generic
 147                 part_number = 'generic'
 148         elif not meson.is_cross_build()
 149                 # The script returns ['Implementer', 'Variant', 'Architecture',
 150                 # 'Primary Part number', 'Revision']
 151                 detect_vendor = find_program(join_paths(
 152                                 meson.current_source_dir(), 'armv8_machine.py'))
 153                 cmd = run_command(detect_vendor.path())
 154                 if cmd.returncode() == 0
 155                         cmd_output = cmd.stdout().to_lower().strip().split(' ')
 156                         implementer_id = cmd_output[0]
 157                         part_number = cmd_output[3]
 158                 endif
 159                 # Set to generic if variable is not found
 160                 implementer_config = get_variable('implementer_' + implementer_id, ['generic'])
 161                 if implementer_config[0] == 'generic'
 162                         implementer_config = implementer_generic
 163                         part_number = 'generic'
 164                 endif
 165                 if arm_force_native_march == true
 166                         part_number = 'native'
 167                 endif
 168         else
 169                 implementer_id = meson.get_cross_property('implementer_id', 'generic')
 170                 part_number = meson.get_cross_property('part_number', 'generic')
 171                 implementer_config = get_variable('implementer_' + implementer_id)
 172         endif
 173
 174         # Apply Common Defaults. These settings may be overwritten by machine
 175         # settings later.
 176         foreach flag: flags_common
 177                 if flag.length() > 0
 178                         dpdk_conf.set(flag[0], flag[1])
 179                 endif
 180         endforeach
 181
 182         message('Implementer : ' + implementer_config[0])
 183         foreach flag: implementer_config[1]
 184                 if flag.length() > 0
 185                         dpdk_conf.set(flag[0], flag[1])
 186                 endif
 187         endforeach
 188
 189         foreach marg: implementer_config[2]
 190                 if marg[0] == part_number
 191                         foreach flag: marg[1]
 192                                 if cc.has_argument(flag)
 193                                         machine_args += flag
 194                                 endif
 195                         endforeach
 196                         # Apply any extra machine specific flags.
 197                         foreach flag: marg.get(2, [])
 198                                 if flag.length() > 0
 199                                         dpdk_conf.set(flag[0], flag[1])
 200                                 endif
 201                         endforeach
 202                 endif
 203         endforeach
 204 endif
 205 message(machine_args)
 206
 207 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 208     cc.get_define('__aarch64__', args: machine_args) != '')
 209         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 210 endif
 211
 212 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
 213         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
 214 endif
 215
 216 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
 217         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
 218         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 219 endif