1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific armv8 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific armv8 flags have higher priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
41 'machine_args': ['-march=armv8-a+crc', '-moutline-atomics']
44 'machine_args': ['-march=armv8-a', '-mfpu=neon'],
46 ['RTE_ARCH_ARM_NEON_MEMCPY', false],
47 ['RTE_ARCH_STRICT_ALIGN', true],
48 ['RTE_ARCH_ARMv8_AARCH32', true],
49 ['RTE_CACHE_LINE_SIZE', 64]
55 part_number_config_arm = {
56 '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
57 '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
58 '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
59 '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
60 '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
61 '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
62 '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
64 'machine_args': ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
66 ['RTE_MACHINE', '"neoverse-n1"'],
67 ['RTE_ARM_FEATURE_ATOMICS', true],
68 ['RTE_MAX_MEM_MB', 1048576],
69 ['RTE_MAX_LCORE', 160],
70 ['RTE_MAX_NUMA_NODES', 2]
74 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
76 ['RTE_MACHINE', '"neoverse-n2"'],
77 ['RTE_ARM_FEATURE_ATOMICS', true],
78 ['RTE_MAX_LCORE', 64],
79 ['RTE_MAX_NUMA_NODES', 1]
86 ['RTE_MACHINE', '"armv8a"'],
87 ['RTE_USE_C11_MEM_MODEL', true],
88 ['RTE_CACHE_LINE_SIZE', 64],
89 ['RTE_MAX_LCORE', 64],
90 ['RTE_MAX_NUMA_NODES', 4]
92 'part_number_config': part_number_config_arm
95 flags_part_number_thunderx = [
96 ['RTE_MACHINE', '"thunderx"'],
97 ['RTE_USE_C11_MEM_MODEL', false]
99 implementer_cavium = {
100 'description': 'Cavium',
102 ['RTE_MAX_VFIO_GROUPS', 128],
103 ['RTE_MAX_LCORE', 96],
104 ['RTE_MAX_NUMA_NODES', 2]
106 'part_number_config': {
108 'machine_args': ['-mcpu=thunderxt88'],
109 'flags': flags_part_number_thunderx
112 'machine_args': ['-mcpu=thunderxt81'],
113 'flags': flags_part_number_thunderx
116 'machine_args': ['-mcpu=thunderxt83'],
117 'flags': flags_part_number_thunderx
120 'machine_args': ['-march=armv8.1-a+crc+crypto', '-mcpu=thunderx2t99'],
122 ['RTE_MACHINE', '"thunderx2"'],
123 ['RTE_ARM_FEATURE_ATOMICS', true],
124 ['RTE_USE_C11_MEM_MODEL', true],
125 ['RTE_CACHE_LINE_SIZE', 64],
126 ['RTE_MAX_LCORE', 256]
130 'machine_args': ['-march=armv8.2-a+crc+crypto+lse', '-mcpu=octeontx2'],
132 ['RTE_MACHINE', '"octeontx2"'],
133 ['RTE_ARM_FEATURE_ATOMICS', true],
134 ['RTE_USE_C11_MEM_MODEL', true],
135 ['RTE_MAX_LCORE', 36],
136 ['RTE_MAX_NUMA_NODES', 1]
142 implementer_ampere = {
143 'description': 'Ampere Computing',
145 ['RTE_MACHINE', '"emag"'],
146 ['RTE_CACHE_LINE_SIZE', 64],
147 ['RTE_MAX_LCORE', 32],
148 ['RTE_MAX_NUMA_NODES', 1]
150 'part_number_config': {
151 '0x0': {'machine_args': ['-march=armv8-a+crc+crypto', '-mtune=emag']}
155 implementer_hisilicon = {
156 'description': 'HiSilicon',
158 ['RTE_USE_C11_MEM_MODEL', true],
159 ['RTE_CACHE_LINE_SIZE', 128]
161 'part_number_config': {
163 'machine_args': ['-march=armv8.2-a+crypto', '-mtune=tsv110'],
165 ['RTE_MACHINE', '"Kunpeng 920"'],
166 ['RTE_ARM_FEATURE_ATOMICS', true],
167 ['RTE_MAX_LCORE', 256],
168 ['RTE_MAX_NUMA_NODES', 8]
172 'machine_args': ['-march=armv8.2-a+crypto+sve'],
174 ['RTE_MACHINE', '"Kunpeng 930"'],
175 ['RTE_ARM_FEATURE_ATOMICS', true],
176 ['RTE_MAX_LCORE', 1280],
177 ['RTE_MAX_NUMA_NODES', 16]
183 implementer_qualcomm = {
184 'description': 'Qualcomm',
186 ['RTE_MACHINE', '"armv8a"'],
187 ['RTE_USE_C11_MEM_MODEL', true],
188 ['RTE_CACHE_LINE_SIZE', 64],
189 ['RTE_MAX_LCORE', 64],
190 ['RTE_MAX_NUMA_NODES', 1]
192 'part_number_config': {
193 '0x800': {'machine_args': ['-march=armv8-a+crc']},
194 '0xc00': {'machine_args': ['-march=armv8-a+crc']},
198 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
200 'generic': implementer_generic,
201 '0x41': implementer_arm,
202 '0x43': implementer_cavium,
203 '0x48': implementer_hisilicon,
204 '0x50': implementer_ampere,
205 '0x51': implementer_qualcomm
208 # SoC specific armv8 flags have the highest priority
209 # (will overwrite all other flags)
211 'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
212 'implementer': 'generic',
213 'part_number': 'generic'
216 soc_generic_aarch32 = {
217 'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
218 'implementer': 'generic',
219 'part_number': 'generic_aarch32'
223 'description': 'Marvell ARMADA',
224 'implementer': '0x41',
225 'part_number': '0xd08',
227 ['RTE_MAX_LCORE', 16],
228 ['RTE_MAX_NUMA_NODES', 1]
234 'description': 'NVIDIA BlueField',
235 'implementer': '0x41',
236 'part_number': '0xd08',
238 ['RTE_MAX_LCORE', 16],
239 ['RTE_MAX_NUMA_NODES', 1]
245 'description': 'Qualcomm Centriq 2400',
246 'implementer': '0x51',
247 'part_number': '0xc00',
252 'description' : 'Marvell OCTEON 10',
253 'implementer' : '0x41',
255 ['RTE_MAX_LCORE', 24],
256 ['RTE_MAX_NUMA_NODES', 1]
258 'part_number': '0xd49',
263 'description': 'NXP DPAA',
264 'implementer': '0x41',
265 'part_number': '0xd08',
267 ['RTE_MACHINE', '"dpaa"'],
268 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
269 ['RTE_MAX_LCORE', 16],
270 ['RTE_MAX_NUMA_NODES', 1]
276 'description': 'Ampere eMAG',
277 'implementer': '0x50',
282 'description': 'AWS Graviton2',
283 'implementer': '0x41',
284 'part_number': '0xd0c',
289 'description': 'HiSilicon Kunpeng 920',
290 'implementer': '0x48',
291 'part_number': '0xd01',
296 'description': 'HiSilicon Kunpeng 930',
297 'implementer': '0x48',
298 'part_number': '0xd02',
303 'description': 'Arm Neoverse N1SDP',
304 'implementer': '0x41',
305 'part_number': '0xd0c',
313 'description': 'Arm Neoverse N2',
314 'implementer': '0x41',
315 'part_number': '0xd49',
320 'description': 'Marvell OCTEON TX2',
321 'implementer': '0x43',
322 'part_number': '0xb2',
327 'description': 'Broadcom Stingray',
328 'implementer': '0x41',
330 ['RTE_MAX_LCORE', 16],
331 ['RTE_MAX_NUMA_NODES', 1]
333 'part_number': '0xd08',
338 'description': 'Marvell ThunderX2 T99',
339 'implementer': '0x43',
340 'part_number': '0xaf'
344 'description': 'Marvell ThunderX T88',
345 'implementer': '0x43',
346 'part_number': '0xa1'
351 generic: Generic un-optimized build for armv8 aarch64 execution mode.
352 generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.
353 armada: Marvell ARMADA
354 bluefield: NVIDIA BlueField
355 centriq2400: Qualcomm Centriq 2400
356 cn10k: Marvell OCTEON 10
359 graviton2: AWS Graviton2
360 kunpeng920: HiSilicon Kunpeng 920
361 kunpeng930: HiSilicon Kunpeng 930
362 n1sdp: Arm Neoverse N1SDP
364 octeontx2: Marvell OCTEON TX2
365 stingray: Broadcom Stingray
366 thunderx2: Marvell ThunderX2 T99
367 thunderxt88: Marvell ThunderX T88
370 # The string above is included in the documentation, keep it in sync with the
373 'generic': soc_generic,
374 'generic_aarch32': soc_generic_aarch32,
375 'armada': soc_armada,
376 'bluefield': soc_bluefield,
377 'centriq2400': soc_centriq2400,
381 'graviton2': soc_graviton2,
382 'kunpeng920': soc_kunpeng920,
383 'kunpeng930': soc_kunpeng930,
386 'octeontx2': soc_octeontx2,
387 'stingray': soc_stingray,
388 'thunderx2': soc_thunderx2,
389 'thunderxt88': soc_thunderxt88
392 dpdk_conf.set('RTE_ARCH_ARM', 1)
393 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
397 if dpdk_conf.get('RTE_ARCH_32')
399 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
400 if meson.is_cross_build()
402 soc = meson.get_cross_property('platform', '')
404 error('Arm SoC must be specified in the cross file.')
406 soc_config = socs.get(soc, {'not_supported': true})
410 dpdk_conf.set('RTE_ARCH_ARMv7', true)
411 # the minimum architecture supported, armv7-a, needs the following,
412 machine_args += '-mfpu=neon'
418 if not meson.is_cross_build()
419 # for backwards compatibility:
420 # machine=native is the same behavior as soc=native
421 # machine=generic/default is the same as soc=generic
422 # cpu_instruction_set holds the proper value - native, generic or cpu
423 # the old behavior only distinguished between generic and native build
425 if cpu_instruction_set == 'generic'
435 # The script returns ['Implementer', 'Variant', 'Architecture',
436 # 'Primary Part number', 'Revision']
437 detect_vendor = find_program(join_paths(meson.current_source_dir(),
439 cmd = run_command(detect_vendor.path())
440 if cmd.returncode() == 0
441 cmd_output = cmd.stdout().to_lower().strip().split(' ')
442 implementer_id = cmd_output[0]
443 part_number = cmd_output[3]
445 error('Error when getting Arm Implementer ID and part number.')
449 soc_config = socs.get(soc, {'not_supported': true})
453 soc = meson.get_cross_property('platform', '')
455 error('Arm SoC must be specified in the cross file.')
457 soc_config = socs.get(soc, {'not_supported': true})
462 if soc_config.has_key('not_supported')
463 error('SoC @0@ not supported.'.format(soc))
464 elif soc_config != {}
465 implementer_id = soc_config['implementer']
466 implementer_config = implementers[implementer_id]
467 part_number = soc_config['part_number']
468 soc_flags = soc_config.get('flags', [])
469 if not soc_config.get('numa', true)
473 disable_drivers += ',' + soc_config.get('disable_drivers', '')
474 enable_drivers += ',' + soc_config.get('enable_drivers', '')
477 if implementers.has_key(implementer_id)
478 implementer_config = implementers[implementer_id]
480 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
481 'Please add support for it or use the generic ' +
482 '(-Dplatform=generic) build.')
485 message('Arm implementer: ' + implementer_config['description'])
486 message('Arm part number: ' + part_number)
488 part_number_config = implementer_config['part_number_config']
489 if part_number_config.has_key(part_number)
490 # use the specified part_number machine args if found
491 part_number_config = part_number_config[part_number]
493 # unknown part number
494 error('Unsupported part number @0@ of implementer @1@. '
495 .format(part_number, implementer_id) +
496 'Please add support for it or use the generic ' +
497 '(-Dplatform=generic) build.')
500 # add/overwrite flags in the proper order
501 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags
503 # apply supported machine args
504 machine_args = [] # Clear previous machine args
505 foreach flag: part_number_config['machine_args']
506 if cc.has_argument(flag)
512 foreach flag: dpdk_flags
514 dpdk_conf.set(flag[0], flag[1])
518 message('Using machine args: @0@'.format(machine_args))
520 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
521 cc.get_define('__aarch64__', args: machine_args) != '')
522 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
525 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
526 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
527 if (cc.check_header('arm_sve.h'))
528 dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
532 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
533 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
536 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
537 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
538 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']