1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright(c) 2017 Intel Corporation.
3 # Copyright(c) 2017 Cavium, Inc
4 # Copyright(c) 2021 PANTHEON.tech s.r.o.
6 # common flags to all aarch64 builds, with lowest priority
8 # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
9 # to determine the best threshold in code. Refer to notes in source file
10 # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
11 ['RTE_ARCH_ARM64_MEMCPY', false],
12 # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
13 # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
14 # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
15 # unless there are strong reasons.
16 # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
17 # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
18 # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
20 ['RTE_SCHED_VECTOR', false],
21 ['RTE_ARM_USE_WFE', false],
22 ['RTE_ARCH_ARM64', true],
23 ['RTE_CACHE_LINE_SIZE', 128]
26 ## Part numbers are specific to Arm implementers
27 # implementer specific aarch64 flags have middle priority
28 # (will overwrite common flags)
29 # part number specific aarch64 flags have the highest priority
30 # (will overwrite both common and implementer specific flags)
31 implementer_generic = {
32 'description': 'Generic armv8',
34 ['RTE_MACHINE', '"armv8a"'],
35 ['RTE_USE_C11_MEM_MODEL', true],
36 ['RTE_MAX_LCORE', 256],
37 ['RTE_MAX_NUMA_NODES', 4]
39 'part_number_config': {
40 'generic': {'machine_args': ['-march=armv8-a+crc',
45 part_number_config_arm = {
46 '0xd03': {'machine_args': ['-mcpu=cortex-a53']},
47 '0xd04': {'machine_args': ['-mcpu=cortex-a35']},
48 '0xd07': {'machine_args': ['-mcpu=cortex-a57']},
49 '0xd08': {'machine_args': ['-mcpu=cortex-a72']},
50 '0xd09': {'machine_args': ['-mcpu=cortex-a73']},
51 '0xd0a': {'machine_args': ['-mcpu=cortex-a75']},
52 '0xd0b': {'machine_args': ['-mcpu=cortex-a76']},
54 'machine_args': ['-march=armv8.2-a+crypto',
57 ['RTE_MACHINE', '"neoverse-n1"'],
58 ['RTE_ARM_FEATURE_ATOMICS', true],
59 ['RTE_MAX_MEM_MB', 1048576],
64 'machine_args': ['-march=armv8.5-a+crypto+sve2'],
66 ['RTE_MACHINE', '"neoverse-n2"'],
67 ['RTE_ARM_FEATURE_ATOMICS', true],
75 ['RTE_MACHINE', '"armv8a"'],
76 ['RTE_USE_C11_MEM_MODEL', true],
77 ['RTE_CACHE_LINE_SIZE', 64],
78 ['RTE_MAX_LCORE', 16],
79 ['RTE_MAX_NUMA_NODES', 1]
81 'part_number_config': part_number_config_arm
84 flags_part_number_thunderx = [
85 ['RTE_MACHINE', '"thunderx"'],
86 ['RTE_USE_C11_MEM_MODEL', false]
88 implementer_cavium = {
89 'description': 'Cavium',
91 ['RTE_MAX_VFIO_GROUPS', 128],
92 ['RTE_MAX_LCORE', 96],
93 ['RTE_MAX_NUMA_NODES', 2]
95 'part_number_config': {
97 'machine_args': ['-mcpu=thunderxt88'],
98 'flags': flags_part_number_thunderx
101 'machine_args': ['-mcpu=thunderxt81'],
102 'flags': flags_part_number_thunderx
105 'machine_args': ['-mcpu=thunderxt83'],
106 'flags': flags_part_number_thunderx
109 'machine_args': ['-march=armv8.1-a+crc+crypto',
110 '-mcpu=thunderx2t99'],
112 ['RTE_MACHINE', '"thunderx2"'],
113 ['RTE_ARM_FEATURE_ATOMICS', true],
114 ['RTE_USE_C11_MEM_MODEL', true],
115 ['RTE_CACHE_LINE_SIZE', 64],
116 ['RTE_MAX_LCORE', 256]
120 'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
123 ['RTE_MACHINE', '"octeontx2"'],
124 ['RTE_ARM_FEATURE_ATOMICS', true],
125 ['RTE_USE_C11_MEM_MODEL', true],
126 ['RTE_MAX_LCORE', 36],
127 ['RTE_MAX_NUMA_NODES', 1]
133 implementer_ampere = {
134 'description': 'Ampere Computing',
136 ['RTE_MACHINE', '"emag"'],
137 ['RTE_CACHE_LINE_SIZE', 64],
138 ['RTE_MAX_LCORE', 32],
139 ['RTE_MAX_NUMA_NODES', 1]
141 'part_number_config': {
142 '0x0': {'machine_args': ['-march=armv8-a+crc+crypto',
147 implementer_qualcomm = {
148 'description': 'Qualcomm',
150 ['RTE_MACHINE', '"armv8a"'],
151 ['RTE_USE_C11_MEM_MODEL', true],
152 ['RTE_CACHE_LINE_SIZE', 64],
153 ['RTE_MAX_LCORE', 64],
154 ['RTE_MAX_NUMA_NODES', 1]
156 'part_number_config': {
157 '0xc00': {'machine_args': ['-march=armv8-a+crc']}
161 implementer_marvell = {
162 'description': 'Marvell ARMADA',
164 ['RTE_MACHINE', '"armv8a"'],
165 ['RTE_CACHE_LINE_SIZE', 64],
166 ['RTE_MAX_LCORE', 16],
167 ['RTE_MAX_NUMA_NODES', 1]
169 'part_number_config': part_number_config_arm
173 'description': 'NXP DPAA',
175 ['RTE_MACHINE', '"dpaa"'],
176 ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
177 ['RTE_USE_C11_MEM_MODEL', true],
178 ['RTE_CACHE_LINE_SIZE', 64],
179 ['RTE_MAX_LCORE', 16],
180 ['RTE_MAX_NUMA_NODES', 1]
182 'part_number_config': part_number_config_arm
185 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
187 'generic': implementer_generic,
188 '0x41': implementer_arm,
189 '0x43': implementer_cavium,
190 '0x50': implementer_ampere,
191 '0x51': implementer_qualcomm,
192 '0x56': implementer_marvell,
193 'dpaa': implementer_dpaa
196 dpdk_conf.set('RTE_ARCH_ARM', 1)
197 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
199 if dpdk_conf.get('RTE_ARCH_32')
201 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
202 dpdk_conf.set('RTE_ARCH_ARMv7', 1)
203 # the minimum architecture supported, armv7-a, needs the following,
204 machine_args += '-mfpu=neon'
207 if not meson.is_cross_build()
208 if machine == 'generic'
210 implementer_id = 'generic'
211 part_number = 'generic'
214 # The script returns ['Implementer', 'Variant', 'Architecture',
215 # 'Primary Part number', 'Revision']
216 detect_vendor = find_program(join_paths(
217 meson.current_source_dir(), 'armv8_machine.py'))
218 cmd = run_command(detect_vendor.path())
219 if cmd.returncode() == 0
220 cmd_output = cmd.stdout().to_lower().strip().split(' ')
221 implementer_id = cmd_output[0]
222 part_number = cmd_output[3]
224 error('Error when getting Arm Implementer ID and part number.')
229 implementer_id = meson.get_cross_property('implementer_id')
230 part_number = meson.get_cross_property('part_number')
233 if implementers.has_key(implementer_id)
234 implementer_config = implementers[implementer_id]
236 error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
237 'Please add support for it or use the generic ' +
238 '(-Dmachine=generic) build.')
241 message('Arm implementer: ' + implementer_config['description'])
242 message('Arm part number: ' + part_number)
244 part_number_config = implementer_config['part_number_config']
245 if part_number_config.has_key(part_number)
246 # use the specified part_number machine args if found
247 part_number_config = part_number_config[part_number]
249 # unknown part number
250 error('Unsupported part number @0@ of implementer @1@. '
251 .format(part_number, implementer_id) +
252 'Please add support for it or use the generic ' +
253 '(-Dmachine=generic) build.')
256 # use common flags with implementer flags
257 dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', [])
259 # apply supported machine args
260 machine_args = [] # Clear previous machine args
261 foreach flag: part_number_config['machine_args']
262 if cc.has_argument(flag)
268 foreach flag: dpdk_flags
270 dpdk_conf.set(flag[0], flag[1])
274 message('Using machine args: @0@'.format(machine_args))
276 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
277 cc.get_define('__aarch64__', args: machine_args) != '')
278 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
281 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
282 compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
285 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
286 compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
287 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']